Digital Cellular Neural Network Research Articles

Efficient segmentation method using quantised and non‐linear CeNN for breast tumour classification

A new segmentation method for mammography imaging system is proposed. Segmentation of masses is always a difficult problem in radiological image interpretation. Conventional methods such as region growing suffer from their computational complexity and hence can hardly be used for segmentation of high-resolution images. In order to achieve efficiency in both computational complexity and accuracy, a novel digital cellular neural network (CeNN) based approach is presented for segmentation. The approach is featured with quantisation to significantly reduce the computational complexity and non-linear template for robustness. After segmentation, a multilayer perceptron classifier is used for feature extraction and classification. Compared with other prior works, the proposed work is able to reduce resource overhead up to 63% and energy consumption up to 41% on FPGA while maintaining only up to 1.5 and 0.6% accuracy deviations for mediolateral-oblique and cranial-caudal views, respectively.

On the Impact of Energy-Accuracy Tradeoff in a Digital Cellular Neural Network for Image Processing

This paper studies the opportunities of energy-accuracy tradeoff in cellular neural network (CNN). Algorithmic characteristics of CNN is coupled with hardware-induced error distribution of a digital CNN cell to evaluate energy-accuracy tradeoff for simple image processing tasks as well as a complex application. The analysis shows that errors modulate the cell dynamics and propagate through the network degrading the output quality and increasing the convergence time. The error propagation is determined by the task being performed by the CNN, specifically, the strength of the feedback template. Controlling precision is observed to be a more effective approach for energy-accuracy tradeoff in CNN than voltage over scaling.

24-GOPS 4.5-<formula formulatype="inline"><tex Notation="TeX">${\rm mm}^{2}$</tex></formula> Digital Cellular Neural Network for Rapid Visual Attention in an Object-Recognition SoC

This paper presents the Visual Attention Engine (VAE), which is a digital cellular neural network (CNN) that executes the VA algorithm to speed up object-recognition. The proposed time-multiplexed processing element (TMPE) CNN topology achieves high performance and small area by integrating 4800 (80 × 60) cells and 120 PEs. Pipelined operation of the PEs and single-cycle global shift capability of the cells result in a high PE utilization ratio of 93%. The cells are implemented by 6T static random access memory-based register files and dynamic shift registers to enable a small area of 4.5 mm(2). The bus connections between PEs and cells are optimized to minimize power consumption. The VAE is integrated within an object-recognition system-on-chip (SoC) fabricated in the 0.13- μm complementary metal-oxide-semiconductor process. It achieves 24 GOPS peak performance and 22 GOPS sustained performance at 200 MHz enabling one CNN iteration on an 80 × 60 pixel image to be completed in just 4.3 μs. With VA enabled using the VAE, the workload of the object-recognition SoC is significantly reduced, resulting in 83% higher frame rate while consuming 45% less energy per frame without degradation of recognition accuracy.

A Configurable Digital Cellular Neural Network with Template Decomposition

A configurable digital cellular neural network (DCNN) with decomposable templates is presented. A template decomposition method based on physical circuit decomposition and synthesis is proposed to meet the large template requirement in CNN. The complexity of the template decomposition scheme is only O(⌈(2n+1)/3⌉2), which is significantly reduced when compared to the other methods in the literature. Moreover, the proposed method supports both binary and gray-scale images.

New Digital Architecture of CNN for Pattern Recognition

New Digital Architecture of CNN for Pattern RecognitionThe paper deals with the design of a new digital CNN (Cellular Neural Network) architecture for pattern recognition. The main parameters of the new design were the area consumption of the chip and the speed of calculation in one iteration. The CNN was designed as a digital synchronous circuit. The largest area of the chip belongs to the multiplication unit. In the new architecture we replaced the parallel multiplication unit by a simple AND gate performing serial multiplication. The natural property of this method of multiplication is rounding. We verified some basic properties of the proposed CNN such as edge detection, filling of the edges and noise removing. At the end we compared the designed network with other two CNNs. The new architecture allows to save till 86% gates in comparison with CNN with parallel multipliers.

Bifurcation in a nonlinear steady state system

The steady state solutions of a nonlinear digital cellular neural network with \(\omega\) neural units and a nonnegative variable parameter \(\lambda\) are sought. We show that \(\lambda = 1\) is a critical value such that the qualitative behavior of our network changes. More specifically, when \(\omega\) is odd, then for \(\lambda \in [0,1)\), there is one positive and one negative steady state, and for \(\lambda \in [1,\infty)\), steady states cannot exist; while when \(\omega\) is even, then for \(\lambda \in [0,1)\), there is one positive and one negative steady state, and for \(\lambda = 1\), there are no nontrivial steady states, and for \(\lambda \in (1,\infty)\), there are two fully oscillatory steady states. Furthermore, the number of existing nontrivial solutions cannot be improved. It is hoped that our results are of interest to digital neural network designers.

A CNN-Specific Integrated Processor

Integrated Processors (IP) are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN) to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNNdesigns, giving the systema 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

Configurable multilayer CNN-UM emulator on FPGA

A new emulated digital multilayer cellular neural network (universal machine (CNN-UM) chip architecture called Falcon has been developed. In this brief, the main steps of the field-programmable gate array (FPGA) implementation are introduced. The main results are as follows. The CNN-UM architecture emulated on Xilinx Virtex series FPGA, three-dimensional nonlinear spatio-temporal dynamics can be implemented on this architecture. The critical parameters of the implementation in a single-layer configuration are 55 million cell update/s/processor core, or, equivalently 1 giga-operation per second (GOPS) computing performance. In the face of the high performance, the power requirements of the architecture are relatively low only /spl sim/3 W per processor core. Using reconfigurable devices to implement emulated digital architectures provides more flexibility compared to the custom very large-scale integration designs because different Falcon architectures can be used on the same FPGA device.

Implementation of Neural Network for Image Processing on the FPGA Programmable Systems

In this paper the implementation of fragment digital Cellular Neural Network (CNN) for image processing on the Field Programmable Gate Array (FPGA) and it's experiment results are present. The high processing speed of the network is use to provide real time processing. Results shows that the architecture CNN and FPGA and implementation has good corespondent.

Texture Classification and Segmentation by Cellular Neural Networks Using Genetic Learning

We present a new single-chip texture classifier based on the cellular neural network (CNN) architecture. Exploiting the dynamics of a locally interconnected 2D cell array of CNNs we have developed a theoretically new method for texture classification and segmentation. This technique differs from other convolution-based feature extraction methods since we utilize feedback convolution, and we use a genetic learning algorithm to determine the optimal kernel matrices of the network. The CNN operators we have found for texture recognition may combine different early vision effects. We show how the kernel matrices can be derived from the state equations of the network for convolution/deconvolution and nonlinear effects. The whole process includes histogram equalization of the textured images, filtering with the trained kernel matrices, and decision-making based on average gray-scale or texture energy of the filtered images. We present experimental results using digital CNN simulation with sensitivity analysis for noise, rotation, and scale. We also report a tested application performed on a programmable 22 × 20 CNN chip with optical inputs and an execution time of a few microseconds. We have found that this CNN chip with a simple 3 × 3 CNN kernel can reliably classify four textures. Using more templates for decision-making, we believe that more textures can be separated and adequate texture segmentation (< 1% error) can be achieved.

VLSI Design of Digital Cellular Neural Networks for Image Processing

Biologically inspired analog VLSI systems have attracted more and more studies. For system consistency and for quick application of neural systems, we have established digital models for neuron operations such that the cell operations can be implemented with simple digital adders and multipliers. To provide fast data transfer and minimum reconfiguration for various sizes of networks, the architecture is designed for low hardware complexity and high mask flexibility, and is perfectly suited for VLSI array implementation. The parallel computation model derived here is used to realize parallel array processor architectures for digital neural networks. Some image processing operations have been simulated. The tolerable error rate compared to the analog model and the competent speed performance make this applicable to digital systems and suitable for 2-D signal processing.