Diffused Metal Oxide Semiconductor Field-Effect Transistors Research Articles

Analysis of SEGR in Silicon Planar Gate Super-Junction Power MOSFETs

This article compares and analyzes the single-event gate rupture (SEGR) response of silicon planar gate super-junction (SJ) power metal oxide semiconductor field effect transistors (MOSFETs) and vertical double diffused power MOSFETs (VDMOSs). When an incident heavy-ion strike is perpendicular to the gate oxide, the SEGR tolerances of SJ power MOSFETs (SJMOSs) and VDMOSs are similar. But, for heavy-ion strikes that are at different angles, SJMOS has better SEGR tolerance than VDMOS. This improved performance of SJMOS is due to the presence of an additional horizontal electric field component in SJMOS devices. This is validated using the experimental data and simulation results in this article.

Robust ESD-Reliability Design of 300-V Power N-Channel LDMOSs with the Elliptical Cylinder Super-Junctions in the Drain Side

The weak ESD-immunity problem has been deeply persecuted in ultra high-voltage (UHV) metal-oxide-semiconductor field-effect transistors (MOSFETs) and urgently needs to be solved. In this paper, a UHV 300 V circular n-channel (n) lateral diffused MOSFET (nLDMOS) is taken as the benchmarked reference device for the electrostatic discharge (ESD) capability improvement. However, a super-junction (SJ) structure in the drain region will cause extra depletion zones in the long drain region and reduce the peak value of the channel electric field. Therefore, it may directly increase the resistance of the device to ESD. Then, in this reformation project for UHV nLDMOSs to ESD, two strengthening methods were used. Firstly, the SJ area ratio changed by the symmetric eight-zone elliptical-cylinder length (X) variance (i.e., X = 5, 10, 15 and 20 μm) is added into the drift region of drain side to explore the influence on ESD reliability. From the experimental results, it could be found that the breakdown voltages (VBK) were changed slightly after adding this SJ structure. The VBK values are filled between 391 and 393.5 V. Initially, the original reference sample is 393 V; the VBK changing does not exceed 0.51%, which means that these components can be regarded as little changing in the conduction characteristic after adding these SJ structures under the normal operating conditions. In addition, in the ESD transient high-voltage bombardment situation, the human-body model (HBM) capability of the original reference device is 2500 V. Additionally, as SJs with the length X high-voltage P-type well (HVPW) are inserted into the drain-side drift region, the HBM robustness of these UHV nLDMOSs increases with the length X of the HVPW. When the length X (HVPW) is 20 μm, the HBM value can be upgraded to a maximum value of 5500 V, the ESD capability is increased by 120%. A linear relationship between the HBM immunity level and area ratio of SJs in the drains side in this work can be extracted. The second part revealed that, in the symmetric four-zone elliptical cylinder SJ modulation, the HBM robustness is generally promoted with the increase of HVPW SJ numbers (the highest HBM value (4500 V) of the M5 device improved by 80% as compared with the reference device under test (DUT)). Therefore, from this work, we can conclude that the addition of symmetric elliptical-cylinder SJ structures into the drain-side drift region of a UHV nLDMOS is a good strategy for improving the ESD immunity.

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

Variable-K double trenches SOI LDMOS with high-concentration P-pillar**Project supported by the Scientific Research Fund of Hunan Provincial Education Department, China (Grant No. 19K001).

A variable-K trenches silicon-on-insulator (SOI) lateral diffused metal–oxide–semiconductor field-effect transistor (MOSFET) with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields. The device features variable-K dielectric double trenches and a P-pillar between the trenches (VK DT-P LDMOS). The low-K dielectric layer on the surface increases electric field of it. Adding a variable-K material introduces a new electric field peak to the drift region, so as to optimize electric field inside the device. Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it. Thereby, breakdown voltage (BV) of the device is increased. The double conductive channels provide two current paths that significantly reduce specific on-resistance (Ron,sp). Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ⋅cm2. The Ron,sp of VK DT-P LDMOS is reduced by 78.9% compared with the conventional structure.

Impact of interface traps/defects and self‐heating on the degradation of performance of a 4H‐SiC VDMOSFET

The reliability of silicon carbide metal oxide semiconductor field-effect transistors remains a challenge in power applications and relates to the SiO2–SiC interface. The presence of unwanted interface traps/defects degrades the device performance. The impact of acceptor traps/defects on the performance of a 4H-SiC vertical Diffused Metal Oxide Semiconductor Field Effect Transistor (DMOSFET) with a breakdown voltage of 1700 V is investigated. - and - characteristics were simulated, using a drift-diffusion model coupled to Fourier heat equations, and are in a good agreement with experimental results. The presence of interface traps/defects were shown to produce degradation of threshold voltage, but the impact diminishes as temperature increases. A threshold voltage shift of 3.5 V occurs for a trap concentration of 2 × 1013 cm–2/eV at room temperature. The transfer characteristics obtained from electro-thermal modelling show a larger degradation than those at a constant temperature. This degradation increases with the drain bias increase. The threshold voltage from the electro-thermal simulations is 5 V compared to 4 V observed in constant 423 K temperature simulations at. Finally, the interface traps/defects increases breakdown voltage exhibiting a strong dependency on the trap density and their energy decay characteristics.

Numerical and Experimental Investigation of TID Radiation Effects on the Breakdown Voltage of 400-V SOI NLDMOSFETs

The breakdown voltage (BVDS) variation of 400-V silicon-on-insulator (SOI) n-channel laterally diffused metal–oxide–semiconductor field-effect transistors (NLDMOSFETs) is examined after exposure to a total ionizing dose (TID). The results for OFF bias and ON bias are explored. For the OFF bias, BVDS increases first and then degrades with accumulated dose. For the ON bias, the irradiated device shows soft breakdown after irradiation. The physical mechanisms for these variations are analyzed and confirmed by technology computer-aided design (TCAD) simulation.

Power trench gate MOSFET with an integrated 6-pack configuration for a 3-phase inverter

In this paper, we present a new 6-pack power module for a 3-phase inverter that is integrated with the six trench gate double diffused metal-oxide semiconductor field-effect transistor (TDMOS) on a single chip. An integration of each power device is performed through a trench isolation technique using deep reactive-ion etching trench technologies. Through this new technology, the integrated power metal-oxide semiconductor field-effect transistor (MOSFET) produces a high current of above 30 A at a gate bias of 10 V. In addition, each trench power MOSFET (1-pack) has a minimum specific on-resistance of 21 mohm.cm2 and a typical breakdown voltage of 95 V. The trench isolation provides good isolation up to 120 V. The measurement results show that this 6-pack structure can successfully be integrated with other analog/driver integrated circuit on a single chip. Furthermore, to monitor the operating current of the MOSFET under an inverter-operating condition, sensing FET is integrated a FET into the main MOSFET source region without compromising either the area or the operation of the MOSFET.

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET**Project supported by the Fund from the Ministry of Education, Science and Technological Development of the Republic of Serbia (Grant Nos. OI-171026 and TR-32026) and the Ei PCB Factory, Niš.

In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.

Investigation of Hot Carrier Degradation in Shallow-Trench-Isolation-Based High-Voltage Laterally Diffused Metal–Oxide–Semiconductor Field-Effect Transistors by a Novel Direct Current Current–Voltage Technique

Investigation of Hot Carrier Degradation in Shallow-Trench-Isolation-Based High-Voltage Laterally Diffused Metal–Oxide–Semiconductor Field-Effect Transistors by a Novel Direct Current Current–Voltage Technique

Investigation of Hot Carrier Degradation in Shallow-Trench-Isolation-Based High-Voltage Laterally Diffused Metal–Oxide–Semiconductor Field-Effect Transistors by a Novel Direct Current Current–Voltage Technique

Shallow trench isolation (STI) based laterally diffused metal–oxide–semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal–oxide–semiconductor (CMOS) process. A novel direct current current–voltage (DCIV) technique demonstrated with multiple sharp peak signals is proposed to characterize interface state generation in the channel and in the STI drift regions separately. Degradation of STI-based LDMOS transistors in various hot-carrier stress modes is investigated experimentally by proposed technique. A two-dimensional numerical device simulation is performed to obtain insight into the proposed technique and device degradation characteristics under hot-carrier stress conditions. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our results show that the maximum Isub stress becomes the worst hot-carrier degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.

An Investigation on Hot-Carrier Reliability and Degradation Index in Lateral Diffused Metal–Oxide–Semiconductor Field-Effect Transistors

The hot-carrier-induced degradation in the high-voltage n-type lateral diffused metal–oxide–semiconductor (LDMOS) field-effect transistor is investigated. Interface state generation caused by hot-electron injection in the channel region is identified to be the main degradation mechanism. Since the gate current (Ig) consists mainly of the electron injection, Ig correlates well with the hot-carrier lifetime of the device. The impact of varying device layout parameter on the performance and hot-carrier lifetime of the device are also evaluated. Such an analysis can achieve a better design of LDMOS transistors when considering both device performance and hot-carrier reliability.

Optimizing the Gate-to-Drift Overlap Length of Lateral Double Diffused Metal–Oxide–Semiconductor Field Effect Transistor Devices to Improve Hot-Carrier Device Lifetime

In this study, the gate-to-drift overlap length of lateral double diffused metal–oxide–semiconductor field effect transistor (LDMOST) devices is optimized in order to increase their hot-carrier lifetime. LDMOST devices with drift regions are fabricated using a 0.25 µm complementary metal–oxide–semiconductor (CMOS) process. The gate-to-drift overlap lengths in the drift region are 0.1, 0.4, 0.8, and 1.1 µm, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with a gate-to-drift overlap length of 0.4 µm showed the longest on-resistance hot-carrier lifetime of 9.34 ×105 s, along with a breakdown voltage of 22 V and an on-resistance of 23 mΩ·mm2.

A New Conductivity Modulated LDMOSFET Employing Buried P Region and P+ Drain

We have proposed and fabricated a new lateral double diffused metal–oxide–semiconductor field effect transistor (LDMOSFET) entitled conductivity modulated (CM)-LDMOSFET which increases the saturation current and decreases the on-state voltage drop. The current capability of the proposed device was improved due to conductivity modulation by employing a buried p region and a p+ drain junction. Experimental results showed that the on-state voltage drop of the CM-LDMOSFET was lower than that of the conventional LDMOSFET when the current density was higher than 200 A/cm2 and the saturation current of the CM-LDMOSFET at the gate voltage of 15 V was 50% greater than that of the conventional LDMOSFET. The fabrication process of the CM-LDMOSFET is not complicated and is compatible with the conventional LDMOSFET and lateral insulated gated bipolar transistor (LIGBT) processes.

Hot-Carrier Degradation Rate of High-Voltage Lateral Diffused Metal–Oxide–Semiconductor Field-Effect Transistors under Maximum Substrate Current Stress Conditions

In this study, hot-carrier stresses in high-voltage (HV) lateral diffused metal-oxide-semiconductor field-effect transistors (LDMOSFETs) are applied under maximum substrate current (ISub,max) conditions with different VDS and VGS. The power index of the hot-carrier degradation rates is not always 0.5 upon stressing under different ISub,max conditions, and the HV LDMOSFETs do not exhibit the hot-carrier degradation behavior observed in low-voltage (LV) metal–oxide–semiconductor field-effect transistors (MOSFETs). In order to explain why the degradation rates under ISub,max conditions differ with different biases, two-dimensional simulators are used to elucidate the degradation mechanism in HV LDMOSFETs. It is found that under different ISub,max conditions, the highest impact ionization is located at different positions in the drift region of the device. Due to the different gate-control abilities of these regions, the current densities affected by the hot-carrier-induced interface-trapped charges are different. Thus the hot-carrier degradation rates also differ. Furthermore, due to the different depths of the impact ionization region, the amounts of initial hot-carrier-induced interface-trapped charges differ and thus the power-law pre-coefficient A also differs.

Time-Dependent Drain- and Source-Series Resistance of High-Voltage Lateral Diffused Metal–Oxide–Semiconductor Field-Effect Transistors during Hot-Carrier Stress

In this paper, a new reverse transconductance method for investigating the effect of hot-carrier degradation on high-voltage (HV) lateral diffused metal–oxide–semiconductor field-effect transistors (LDMOSFETs) is presented. This new method can extract asymmetric drain and source series resistance separately with only one single device. By using this extraction method in HV LDMOSFETs before and after the application of hot-carrier stress, drain series resistance is extracted and found to increase while source series resistance remains the same. In addition, the threshold voltage and subthreshold slope suffer no degradation after the application of hot-carrier stress. Therefore, it is suggested that the current degradation in HV LDMOSFETs after the application of hot-carrier stress is not due to the damage under the channel but is due to the drift region under the spacer oxide. This is confirmed by the simulation results of a two-dimensional (2D) simulator. In addition, the differences in hot-carrier degradation between HV LDMOSFETs and low-voltage lightly doped drain (LV LDD) MOSFETs are also discussed in detail.

Automotive HID headlamps producing compact electronic ballasts using power ICs

Incandescent halogen lamps have been the standard for automotive headlamps; however, metal halide high-intensity discharge (HID) lamps have slowly begun to be commercially used since the mid-1990s. The lighting system of the metal halide HID headlamp makes a great contribution to energy savings, longer lamp life and better visibility in traffic zones compared with halogen lamps. (Lamp life is lengthened because it prevents the loss of sodium metal as plus ions through the quartz of the lamp bulb.) This article describes power ICs consisting of full bridge inverters and their drivers in detail. Market requirements for electronic ballasts include more compact size, lighter weight, and lower cost. On the other hand, lamp manufacturers recommend that automotive metal halide HID lamps should be operated at negative voltage potential to the body of automotive headlight fixture in order to lengthen lamp life. In order to meet these requirements, a new multichip power integrated circuit (IC) for electronic ballast of automotive HID headlamps has been developed. Discrete power metal-oxide-semiconductor field-effect transistors (MOSFETs) are used for the inverter of the HID electronic ballast. It contains a high-voltage driver IC including a P-channel lateral double diffused MOSFET (LDMOS) to control the full bridge power MOSFETs.

Silicon Field Emitter Arrays Integrated with MOSFET Devices

AbstractWe report a metal oxide semiconductor field effect transistor (MOSFET) controlled field emission array (FEA) device. The device uses a lateral double diffused MOSFET (LD-MOSFET) to control electron supply to the surface. The FEAs were fabricated using isotropic etch of silicon, oxidation sharpening and chemical mechanical polishing. The LD-MOSFETs have a threshold voltage of 0.48V while the FEAs have a turn-on voltage of 28V. Analysis using the FN formulation indicates that a silicon tip radius of 11 nm would fit the FEA IV data. The tip radius from the electrical data is very close to the average tip radius of 10 nm obtained from transmission electron microscope (TEM) analysis. The IV characterization of the MOSFET/FEA demonstrated control of electron emission by the MOSFET gate voltage.