Differential On-resistance Research Articles

Design and Fabrication of Vertical Metal/TiO2/β-Ga2O3Dielectric Heterojunction Diode With Reverse Blocking Voltage of 1010 V

This work provides insight into the design principles and the reasonable construction of Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> heterojunction diode. We chose TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> grown by atomic layer deposition (ALD) as a suitable insulator with a small conduction band offset of TiO<;span style="font-size: 14.5px;"> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /<;/span> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">β</i> -Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> heterojunction and a large dielectric constant. The type-I band alignment of the TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">β</i> -Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> heterojunction was obtained using X-ray photoelectron spectroscopy (XPS). We demonstrated a high-performance vertical metal/TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">β</i> -Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> dielectric heterojunction diode with reverse blocking voltage of 1010 V and differential ON-resistance of 3.3 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The proposed design principles of dielectric heterojunction diode and the insulator selection can also provide a simple, effective, and feasible technology for other wideband and ultrawideband semiconductors in which bipolar doping is challenging to achieve high power device performance.

Over 1 kV Vertical GaN-on-GaN p-n Diodes With Low On-Resistance Using Ammonia Molecular Beam Epitaxy

Vertical GaN-on-GaN p-n diodes grown by ammonia molecular beam epitaxy (NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> MBE) are reported in this letter for prospective high-power application devices. The diodes, consisting of only 4 μm drift layer with low unintentionalbackgrounddoping of ~ 3×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> , showed a maximum breakdown voltage of >1.0 kV and a low differential specific on-resistance of 0.28 mΩ-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Moreover, these diodes exhibited an excellent rectifying behavior with a low minimum ideality factor of 1.36 and a punch-through electric field comparable to the state-of-the-art vertical GaN-on-GaN p-n diodes grown by metalorganic chemical vapor deposition (MOCVD). These results suggest that all-MBE vertical GaN-on-GaN p-n diodes grown by NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> MBE can be promising for small-size high-power electronic devices.

20 kV-Class Ultra-High Voltage 4H-SiC n-IE-IGBTs

We demonstrate 20 kV-class 4H-SiC n-channel implantation and epitaxial (IE)-IGBTs having both low on-state voltage and high blocking characteristics. We fabricated n-IE-IGBTs on a (0001) silicon face with free-standing epitaxial layers. Effective carrier lifetime increased significantly from 0.9 μs to 9.6 μs by a lifetime enhancement process. We used the IE structure to suppress an increase of the surface p+-well concentration, reduce implantation damage at the p+-well, and reduce junction field effect transistor (JFET) region resistance by ion implantation as a counter doping. The n-IE-IGBT at 100 A/cm2 on-state voltage and specific differential on-resistance was 8.2 V and 36.9 mΩcm2, respectively, at room temperature with a 30 V gate voltage. The blocking voltage was 26.8 kV at 45.7 μA.

Impact of graphene interlayer on performance parameters of sandwich structure Pt/GaN Schottky barrier diodes

In this work, we have designed excellent performance GaN-based Schottky barrier diode (SBD) with a sandwich structure by inserting a graphene (Gr) interlayer. The electrical properties of Pt/Gr/GaN and Pt/GaN SBDs have been systematically investigated by the temperature-dependent current—voltage (I–V) and capacitance–voltage measurements in order to explore the effects of Gr on main diode parameters. At room temperature, the Pt/Gr/GaN SBD exhibited lower turn-on voltage (Von), ideality factor (n), differential specific on-resistance (Ron), and higher Schottky barrier height (SBH), signifying enhanced device attributes. Furthermore, the ideality factor and SBH for the Pt/Gr/GaN SBD were found to be insensitive to temperature from the temperature-dependent I–V analysis. The results revealed a highly homogeneous Schottky barrier interface in the case of Pt/Gr/GaN SBD. This facile strategy opened a pathway to improve the performance of the nitride Schottky rectifiers.

Low VF 4H-SiC N-i-P diodes using newly developed low-resistivity p-type substrates

We fabricated 4H-SiC N-i-P (N-intrinsic-P) diodes using newly developed low-resistivity p-type substrates with higher acceptor concentrations than conventional substrate. N-i-P diodes with 10 μm thick n− drift layers were fabricated on both a low-resistivity p-type substrate and a conventional one to investigate the difference in substrate resistance and bipolar degradation with a heavily doped p-type buffer layer. The differential on-resistance of N-i-P diode, using low-resistivity p-type substrates was decreased to one third compared to the conventional case, and the difference was similar to the p-type substrates resistivity. No stacking faults expansion was observed up to 1100 A cm−2. N-i-P diodes with 233 μm thick n− drift layers were fabricated to demonstrate forward characteristics instead of an ultra-high voltage n-channel IGBTs. The forward characteristics of the N-i-P diodes with 233 μm thick n− drift layers at 200 °C showed low on-voltage 6.9 V and low differential on-resistance 32.2 mΩ cm2.

Theoretical and Experimental Study of 13.4 kV/55 A SiC PiN Diodes with an Improved Trade-Off between Blocking Voltage and Differential On-Resistance.

In this paper, a 13.4 kV/55 A 4H-silicon carbide (SiC) PiN diode with a better trade-off between blocking voltage, differential on-resistance, and technological process complexity has been successfully developed. A multiple zone gradient modulation field limiting ring (MGM-FLR) for extremely high-power handling applications was applied and investigated. The reverse blocking voltage of 13.4 kV, close to 95% of the theoretical value of parallel plane breakdown voltage, was obtained at a leakage current of 10 μA for a 100 μm thick, lightly doped, 5 × 1014 cm−3 n-type SiC epitaxial layer. Meanwhile, a fairly low differential on-resistance of 2.5 mΩ·cm2 at 55 A forward current (4.1 mΩ·cm2 at a current density of 100 A/cm2) was calculated for the fabricated SiC PiN with 0.1 cm2 active area. The highest Baliga’s figure-of-merit (BFOM) of 72 GW/cm2 was obtained for the fabricated SiC PiN diode. Additionally, the dependence of the breakdown voltage on transition region width, number of rings in each zone, as well as the junction-to-ring spacing of SiC PiN diodes is also discussed. Our findings indicate that this proposed device structure is one potential candidate for an ultra-high voltage power system, and it represents an option to maximize power density and reduce system complexity.

Field-Plated Ga2O3 Trench Schottky Barrier Diodes With a BV2/$R_{\text{on,sp}}$ of up to 0.95 GW/cm2

We report the realization of field-plated vertical Ga2O3 trench Schottky barrier diodes (SBDs). The trench SBDs show significantly lower leakage current than regular SBDs. With employment of field plate, a breakdown voltage (BV) of 2.89 kV is achieved, which is ~ 500 V higher than those without field plate. Trench sidewall depletion is observed, and the average depletion width is extracted using an analytical model. The trench SBDs have a differential specific on-resistance ( $\text {R}_{\text {on,sp}}$ ) of 10.5 (8.8) $\text{m}\Omega ~\cdot {\mathrm {cm}}^{\text {2}}$ from DC (pulsed) measurements, which leads to a Baliga’s figure-of-merit ( ${\mathrm {BV}}^{{2}}/\text {R}_{\text {on,sp}}$ ) of 0.80 (0.95) GW/cm2— the highest among Ga2O3 power devices to date.

Demonstration of 1.27 kV Etch-Then-Regrow GaN ${p}$ -${n}$ Junctions With Low Leakage for GaN Power Electronics

This letter reports high performance GaN ${p}$ - ${n}$ junctions with regrown ${p}$ -GaN by metalorganic chemical vapor deposition (MOCVD) on dry-etched surfaces. The breakdown voltage reaches 1.27 kV and the differential on-resistance is 0.8 $\text{m}\Omega \cdot \text {cm}^{{2}}$ . The effects of etching powers and surface treatments on the reverse leakage characteristics of the regrown ${p}$ - ${n}$ junctions have been investigated. It’s found that lowering the etching power and damage is very effective to reduce the leakage currents and increase the breakdown voltages. Further analysis reveals that the charge concentration at the regrowth interface plays a critical role in the performance of the regrown samples. To avoid sacrificing the etching rate by using only low power etching, a multiple-RF-power etching recipe was developed with gradually decreased etching power. This work has demonstrated a practical and viable method to realize high performance regrown p-n junctions for various advanced GaN power electronics.

High-performance quasi-vertical GaN Schottky barrier diode with anode selective fluorine treatment

In this letter, we report a high performance GaN quasi-vertical Schottky barrier diode (SBD) on sapphire substrate with a planar anode selective fluorine treatment (SFT). The presented SBD with anode SFT–SBD exhibits a large forward current density over 2 kA cm−2 and a low differential specific on-resistance of 0.49 mΩ cm2. Compared to the conventional SBD, the leakage current of SFT–SBD is suppressed over 4 orders of magnitude, leading to the breakdown voltage (BV) dramatically improved from 78 to 145 V, but without severe degradation of the on-state performance. The simulation results indicate that the anode SFT can effectively reduce the path of leakage current at reverse bias, leading to the suppressed leakage current thus enhanced BV.

(Invited) Development of SiC Schottky-PN Diode with Low on Resistance and High Blocking Voltage

4H-SiC is a promising material for low-loss, high frequency, and high temperature electronic devices. And nowadays, 4H-SiC Schottky diodes, MOSFETs, and its inverters were used in many applications. As well known, a conduction loss and a switching loss shows tread off relationship on these devices. Schottky diode shows high speed switching action and small recovery current based on its unipolar operation, but high series resistance of drift layer. On the other hand, PiN diode shows low series resistance of drift layer due to its conductivity modulation phenomenon based on the bipolar action. However, it causes an adverse reverse recovery current and limited switching speed. To break this tread off relationship, Schottky-PN diode structure so-called SPND or SNPD was proposed with a diamond semiconductor [1]. This diode has a structure with a low doped n- or p- drift layer where is sandwiched and completely depleted with Schottky junction and one side PN junction. Under forward bias condition, barrier height of PN junction is reduced and majority carrier was injected into the drift layer completely depleted with Schottky junction. Injected majority carrier drift to Schottky junction without recombining with minority carrier. It means minority carrier dose not contribute to current flow under forward bias. Then, this SPND structure is expected to show both very low on-resistance and high speed switching action. Under reverse bias condition, blocking voltage is shared throughout the drift layer. However, the diamond semiconductor material is under development and difficult to use production phase. In this study, we demonstrated the possibility of SPND by using 4H-SiC substrate under mass production. In this study, we grew low doped p-layer on n+ 4H-SiC C-face substrate by using hot-wall chemical vapor deposition (CVD) system with H2-SiH4-C3H8 gas system. Trimethylaluminum (TMA) was used as p-type dopant source. The thickness and doing concentration of grown p- layer is 1.1 μm and 5 x 1014 cm-3. Pt was evaporated in vacuum as Schottky electrode on as grown surface. The diameter of Schottky contact is 1mm. Al was used as ohmic back contact. The schematic cross-sectional structure of fabricated 4H-SiC SPND is shown inset of Figure 1. Figure 1 shows typical J-V characteristic of fabricated 4H-SiC SPND at room temperature. Good rectifying characteristic was observed. The blocking voltage of 300 V was obtained (Fig. 1(a)). From this result, we estimated dielectric breakdown field value of 2.5 MV/cm which is almost equal to ideal value of 4H-SiC one. On forward bias characteristic, the current raises at 2.2 V and the current density is reached at 1200 A/cm2 at 2.4 V (Fig. 1(b)). From this value, the differential on-resistance was estimated at 0.18 mΩcm2. In this study, we used 4H-SiC substrate with thickness of 200 μm and resistivity of 20 mΩcm. The calculated series on-resistance of 4H-SiC substrate part was estimated as 0.4 mΩcm2. This result means estimated differential on-resistance of 0.18 mΩcm2 is almost the resistance of substrate and the resistance of drift layer dose not contribute to the series resistance. These results mean 4H-SiC SPND structure was realized and its good performance of low on-resistance with high blocking voltage was confirmed. Details will be shown in this presentation.

Vertical Ga2O3Schottky Barrier Diodes With Small-Angle Beveled Field Plates: A Baliga’s Figure-of-Merit of 0.6 GW/cm2

This letter demonstrates vertical Ga2O3 Schottky barrier diodes (SBDs) with a novel edge termination, the small-angle beveled field plate (SABFP), fabricated on thinned $\text{G}_{{2}}\text{O}_{{3}}$ substrates. Non-punch-though design is used for the drift region with a donor concentration of ${3}\sim {3.5} \times {10} ^{{16}}$ cm−3, rendering a device differential ON-resistance of $\sim 2~\text{m}\Omega ~\cdot $ cm2. A new wet-etch technique is developed by using a bi-layer mask, which consists of spin-on-glass (SOG) and plasma-enhanced chemical vapor deposited (PECVD) SiO2, to fabricate a very small bevel angle (∼ 1°) in the mesa and field plates. This SABFP structure facilitates the electric field spreading at device edges, rendering a breakdown voltage of 1100 V, a peak electric field of 3.5 MV/cm in Ga2O3 at the Schottky contact edge, and an averaged electric field over 3.4 MV/cm underneath the contact. Our device demonstrates a Baliga’s figure of merit of 0.6 GW/cm2, which is among the highest in all reported Ga2O3 power devices and comparable to the state-of-the-art GaN SBDs. These results show the great potential of Ga2O3 SBDs for future power applications.

Design and fabrication of 10-kV silicon–carbide p-channel IGBTs with hexagonal cells and step space modulated junction termination extension**Project supported by the National Basic Research Program of China (Grant No. 2015CB759600), the Science Challenge Project, China (Grant No. TZ2018003), the National Natural Science Foundation of China (Grant Nos. 61474113, 61574140, and 61804149), the Beijing NOVA Program, China (Grant Nos. 2016071 and

10-kV 4H–SiC p-channel insulated gate bipolar transistors (IGBTs) are designed, fabricated, and characterized in this paper. The IGBTs have an active area of 2.25 mm2 with a die size of 3 mm × 3 mm. A step space modulated junction termination extension (SSM-JTE) structure is introduced and fabricated to improve the blocking performance of the IGBTs. The SiC p-channel IGBTs with SSM-JTE termination exhibit a leakage current of only 50 nA at −10 kV. To improve the on-state characteristics of SiC IGBTs, the hexagonal cell (H-cell) structure is designed and compared with the conventional interdigital cell (I-cell) structure. At an on-state current of 50 A/cm2, the voltage drops of I-cell IGBT and H-cell IGBT are 10.1 V and 8.3 V respectively. Meanwhile, on the assumption that the package power density is 300 W/cm2, the maximum permissible current densities of the I-cell IGBT and H-cell IGBT are determined to be 34.2 A/cm2 and 38.9 A/cm2 with forward voltage drops of 8.8 V and 7.8 V, respectively. The differential specific on-resistance of I-cell structure and H-cell structure IGBT are and , respectively. These results demonstrate that H-cell structure silicon carbide IGBT with SSM-JTE is a promising candidate for high power applications.

Conductivity Modulated and Implantation-Free 4H-SiC Ultra-High-Voltage PiN Diodes

Implantation-free mesa etched ultra-high-voltage 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. The diode’s design allows a high breakdown voltage of about 19.3 kV according to simulations. No reverse breakdown is observed up to 13 kV with a very low leakage current of 0.1 μA. A forward voltage drop (VF) and differential on-resistance (Diff. Ron) of 9.1 V and 41.4 mΩ cm2 are measured at 100 A/cm2, respectively, indicating the effect of conductivity modulation.

Enhancement of breakdown voltage for fully-vertical GaN-on-Si p-n diode by using strained layer superlattice as drift layer

We have demonstrated a vertical GaN-on-Si p-n diode with breakdown voltage (BV) as high as 839 V by using a low Si-doped strained layer superlattice (SLS). The p-n vertical diode fabricated by using the n−-SLS layer as a part of the drift layer showed a remarkable enhancement in BV, when compared with the conventional n−-GaN drift layer of similar thickness. The vertical GaN-on-Si p-n diodes with 2.3 μm-thick n−-GaN drift layer and 3.0 μm-thick n−-SLS layer exhibited a differential on-resistance of 4.0 Ω · cm2 and a BV of 839 V.

720-V/0.35-m&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Omega \cdot$ &lt;/tex-math&gt; &lt;/inline-formula&gt;cm2Fully Vertical GaN-on-Si Power Diodes by Selective Removal of Si Substrates and Buffer Layers

This letter demonstrates a novel technology to fabricate fully vertical GaN-on-Si power diodes with state-of-the-art performance. Si substrate and buffer layers were selectively removed and the bottom cathode was formed in the backside trenches extending to an n+-GaN layer. A specific differential ON-resistance of 0.35–0.4 $\text{m}\Omega \cdot $ cm2 (normalized to the total device area) and a breakdown voltage of 720 V were demonstrated in this novel fully vertical GaN-on-Si p-n diode, rendering a Baliga’s figure of merit over 1.5 GW/cm2. These results set a new record performance in all vertical GaN power diodes on foreign substrates, and demonstrate the feasibility of making fully vertical GaN-on-Si power diodes and transistors by selective removal of Si substrates and buffer layers.

High-Voltage and High- $I_{\text {ON}}/I_{\text {OFF}}$ Vertical GaN-on-GaN Schottky Barrier Diode With Nitridation-Based Termination

We report a high-performance vertical GaN-on-GaN Schottky barrier diode (SBD) with a planar nitridation-based termination (NT) technique. The developed NT-SBD with nearly ideal Schottky contact exhibits a forward current density over kA/cm2, current swing over 1013, and differential specific ON-resistance of 1.2 $\text{m}\Omega \cdot $ cm2. The breakdown voltage is boosted from 335 V for unterminated-SBD to 995 V after termination, whereas a high ON/OFF current ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ at −600 V) of ~108 is realized in the NT-SBD. It has been verified that the NT technique can favorably modify GaN surface condition, leading to suppressed leakage current at the junction edge and enhanced breakdown voltage.

Temperature dependence of electrical characteristics for diamond Schottky-pn diode in forward bias

A diamond Schottky-pn diode (SPND) was fabricated and its electrical properties were investigated by measuring the current-voltage characteristics. The diode showed high current density (>104 A/cm2 at 7 V) at room temperature with low differential on-resistance (~10−5 Ωcm2) under a wide temperature range (295–600 K). We constructed Richardson plots based on the characteristics and then estimated the potential barrier height on the hole current. From these results combined with the results of Poisson equation analysis, we viewed the change in hole barrier as a function of applied voltage and obtained the value of the hole activation energy as ~0.06 eV in the p+-type layer around the flat-band voltage. We clarified the transport mechanisms of the SPND and the method for estimating the activation energy in heavily boron-doped diamond exhibiting hopping conduction.

Fabrication of 4H-SiC n-channel IGBTs with ultra high blocking voltage

Owing to the conductivity modulation of silicon carbide (SiC) bipolar devices, n-channel insulated gate bipolar transistors (n-IGBTs) have a significant advantage over metal oxide semiconductor field effect transistors (MOSFETs) in ultra high voltage (UHV) applications. In this paper, backside grinding and laser annealing process were carried out to fabricate 4H-SiC n-IGBTs. The thickness of a drift layer was 120 μm, which was designed for a blocking voltage of 13 kV. The n-IGBTs carried a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V, with a differential specific on-resistance of 140 mΩ·cm2.

Suppression of Punch-Through Current in 3 kV 4H-SiC Reverse-Blocking MOSFET by Using Highly Doped Drift Layer

Low on-resistance 4H-SiC reverse-blocking (RB) metal–oxide–semiconductor field-effect transistors (MOSFETs) have been developed by adopting a non-punch-through (NPT) drift layer in order to suppress the punch-through (PT) current under the reverse-blocking condition. The n-type NPT drift layer was 40- ${\mu }\text{m}$ thick doped to $3.7\times 10^{15} $ cm−3. The forward and reverse breakdown voltages of the fabricated NPT RB MOSFET were 3.6 kV and −3.0 kV, respectively. The differential specific on-resistance was 13.5 $\text{m}\Omega \cdot $ cm2 at room temperature, which was 33% lower than that of a 3 kV PT RB MOSFET, demonstrating superiority of the developed NPT RB MOSFET as a high-performance bidirectional switch.

A Multiple-Ring-Modulated JTE Technique for 4H-SiC Power Device With Improved JTE-Dose Window

In this paper, a multiple-ring-modulated junction termination extension (MRM-JTE) technology for large-area silicon carbide PiN rectifier rated at 4500 V is proposed and experimentally investigated using a standard two-zone JTE (TZ-JTE) process without extra process steps or masks. Multiple modulation rings embedded inside JTE region, which is similar to varied lateral doping technology widely used in silicon devices, form a gradual decrease of effective charges in the termination region. MRM combines the advantages of two termination techniques, namely, ring-assisted JTE and space-modulated JTE, to enlarge the optimum JTE-dose window with high reverse blocking voltage in comparison with conventional TZ-JTE. A breakdown voltage of 4940 V at a leakage current of $1~\mu \text{A}$ is achieved from fabricated MRM-JTE rectifiers with a 36- $\mu \text{m}$ -thick N− epilayer doped to ${1.8} \times {10}^{{15}}$ cm−3, which is 92% of the ideal parallel-plane value. A forward current of 50 A has been measured at a forward voltage drop of 3.9 V for devices with an active anode area of 9.2 mm2, corresponding to low differential on-resistance of 1.8 $\text{m}\Omega \cdot \text {cm}^{ {2}}$ . The simulation and experimental results show that the proposed device exhibits approximately 2 times JTE dose tolerance window improvement with respect to the breakdown voltage of 4500 V.