Different Levels Of Parallelism Research Articles

Adaptive fail-safe topology optimization using a hierarchical parallelization scheme

This work presents an efficient, flexible, and scalable strategy to implement density-based topology optimization formulation for fail-safe structural design. Such optimized designs can operate after faults modeled as loss of stiffness. However, the need for assessing the physical behavior in all the fault cases can make this problem unfeasible computationally. We combine many ingredients to exploit the different levels of parallelism of the formulation to deal successfully with this problem. We use a non-overlapping domain decomposition method to solve the failure cases using multi-core computing with distributed memory computation. These subdomains use adaptive mesh refinement (AMR) techniques to focus computing efforts on the regions of interest. A key point to evaluate the fault cases is the organization of the computing threads, especially in clusters of computers. We group the computing threads by physical computing nodes to reduce the inter-node communications, maximizing intra-node communications to mitigate bandwidth problems. Another ingredient of paramount importance is the use of computing buffers to adapt the evaluation of the fault cases to the computing resources. We test the scalability of the computational framework using a large cluster of computers.

Optimization of FPGA-based CNN accelerators using metaheuristics

In recent years, convolutional neural networks (CNNs) have demonstrated their ability to solve problems in many fields and with accuracy that was not possible before. However, this comes with extensive computational requirements, which made general CPUs unable to deliver the desired real-time performance. At the same time, FPGAs have seen a surge in interest for accelerating CNN inference. This is due to their ability to create custom designs with different levels of parallelism. Furthermore, FPGAs provide better performance per watt compared to GPUs. The current trend in FPGA-based CNN accelerators is to implement multiple convolutional layer processors (CLPs), each of which is tailored for a subset of layers. However, the growing complexity of CNN architectures makes optimizing the resources available on the target FPGA device to deliver optimal performance more challenging. In this paper, we present a CNN accelerator and an accompanying automated design methodology that employs metaheuristics for partitioning available FPGA resources to design a Multi-CLP accelerator. Specifically, the proposed design tool adopts simulated annealing (SA) and tabu search (TS) algorithms to find the number of CLPs required and their respective configurations to achieve optimal performance on a given target FPGA device. Here, the focus is on the key specifications and hardware resources, including digital signal processors, block RAMs, and off-chip memory bandwidth. Experimental results and comparisons using four well-known benchmark CNNs are presented demonstrating that the proposed acceleration framework is both encouraging and promising. The SA-/TS-based Multi-CLP achieves 1.31x - 2.37x higher throughput than the state-of-the-art Single-/Multi-CLP approaches in accelerating AlexNet, SqueezeNet 1.1, VGGNet, and GoogLeNet architectures on the Xilinx VC707 and VC709 FPGA boards.

Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs.

Due to the huge success and rapid development of convolutional neural networks (CNNs), there is a growing demand for hardware accelerators that accommodate a variety of CNNs to improve their inference latency and energy efficiency, in order to enable their deployment in real-time applications. Among popular platforms, field-programmable gate arrays (FPGAs) have been widely adopted for CNN acceleration because of their capability to provide superior energy efficiency and low-latency processing, while supporting high reconfigurability, making them favorable for accelerating rapidly evolving CNN algorithms. This article introduces a highly customized streaming hardware architecture that focuses on improving the compute efficiency for streaming applications by providing full-stack acceleration of CNNs on FPGAs. The proposed accelerator maps most computational functions, that is, convolutional and deconvolutional layers into a singular unified module, and implements the residual and concatenative connections between the functions with high efficiency, to support the inference of mainstream CNNs with different topologies. This architecture is further optimized through exploiting different levels of parallelism, layer fusion, and fully leveraging digital signal processing blocks (DSPs). The proposed accelerator has been implemented on Intel's Arria 10 GX1150 hardware and evaluated with a wide range of benchmark models. The results demonstrate a high performance of over 1.3 TOP/s of throughput, up to 97% of compute [multiply-accumulate (MAC)] efficiency, which outperforms the state-of-the-art FPGA accelerators.

Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC

The emergent technology of Multi-Processor System-on-Chip (MPSoC), which combines heterogeneous computing with the high performance of Field Programmable Gate Arrays (FPGAs) is a very interesting platform for a huge number of applications ranging from medical imaging and augmented reality to high-performance computing in space. In this paper, we focus on the Xilinx Zynq UltraScale+ EG Heterogeneous MPSoC, which is composed of four different processing elements (PE): a dual-core Cortex-R5, a quad-core ARM Cortex-A53, a graphics processing unit (GPU) and a high end FPGA. Proper use of the heterogeneity and the different levels of parallelism of this platform becomes a challenging task. This paper evaluates this platform and each of its PEs to carry out fundamental operations in terms of computational performance. To this end, we evaluate image-based applications and a matrix multiplication kernel. On former, the image-based applications leverage the heterogeneity of the MPSoc and strategically distributes its tasks among both kinds of CPU cores and the FPGA. On the latter, we analyze separately each PE using different matrix multiplication benchmarks in order to assess and compare their performance in terms of MFlops. This kind of operations are being carried out for example in a large number of space-related applications where the MPSoCs are currently gaining momentum. Results stand out the fact that different PEs can collaborate efficiently with the aim of accelerating the computational-demanding tasks of an application. Another important aspect to highlight is that leveraging the parallel OpenBLAS library we achieve up to 12 GFlops with the four Cortex-A53 cores of the platform, which is a considerable performance for this kind of devices.

Heterogeneous CPU/GPU co-execution of CFD simulations on the POWER9 architecture: Application to airplane aerodynamics

High fidelity Computational Fluid Dynamics simulations are generally associated with large computing requirements, which are progressively acute with each new generation of supercomputers. However, significant research efforts are required to unlock the computing power of leading-edge systems, currently referred to as pre-Exascale systems, based on increasingly complex architectures. In this paper, we present the approach implemented in the computational mechanics code Alya. We describe in detail the parallelization strategy implemented to fully exploit the different levels of parallelism, together with a novel co-execution method for the efficient utilization of heterogeneous CPU/GPU architectures. The latter is based on a multi-code co-execution approach with a dynamic load balancing mechanism. The assessment of the performance of all the proposed strategies has been carried out for airplane simulations on the POWER9 architecture accelerated with NVIDIA Volta V100 GPUs.

Memphis: a framework for heterogeneous many-core SoCs generation and validation

This work presents Memphis, which comprises a flexible EDA framework and a many-core model for heterogeneous SoCs. The framework, together with the many-core model supports the integration of processors, network interfaces, routers, and peripherals. A set of tools enable a decoupled generation and compilation of the hardware, operating systems, and applications. The hardware model is cycle-accurate, with a SystemC model to speed up simulation time and a VHDL model enabling prototyping in FPGAs devices. The framework provides a rich set of graphical debugging tools enabling an easy and intuitive understanding of computation and communication events happening at runtime. The coupled integration of the platform model to the EDA framework makes Memphis well suited to be employed in research and teaching. As case studies, we provide a set of evaluations addressing the many-core generation, simulation, and debugging. Different applications sets were employed, enabling to characterize the computation and communication performance of the many-core, as well as, evaluate an AES encryption application performance according to different levels of parallelism.

HYPERDOCK: Improving virtual screening through parallel hyperheuristics

Virtual screening (VS) methods aid clinical research by predicting the interaction of ligands with pharmacological targets. The computational requirements of VS, along with the size of the databases, propitiate the use of high-performance computing. METADOCK is a tool for the application of metaheuristics to VS in heterogeneous clusters of computers based on central processing unit (CPU) and graphics processing unit (GPU). HYPERDOCK represents a step forward; the exploration for satisfactory metaheuristics is systematically approached by means of hyperheuristics working on top of the metaheuristic schema of METADOCK. Multiple metaheuristics are explored, so the process is computationally demanding. HYPERDOCK exploits the parallelism of METADOCK and includes parallelism at its own level. The different levels of parallelism can be used to exploit the parallelism offered by computational systems composed of multicore CPU + multi-GPUs. The efficient exploitation of these systems enables HYPERDOCK to improve ligand–receptor binding.

Performance Analysis of High Throughput MAP Decoder for Turbo Codes and Self Concatenated Convolutional Codes

The effect of parallelism on Bit Error Rate (BER) performance of Turbo Code (TC) and Self Concatenated Convolutional Code (SECCC) with different levels of parallelism and frame sizes is investigated. Next Iteration Initialization (NII) method is employed for mitigating the BER degradation resulting from increased parallelism. In order to analyze and compare the architectural performance of both schemes, this paper presents the Very High Speed Integrated Circuit Hardware Description Language (VHDL) design of Maximum Aposteriori Probability (MAP) decoder for TC and SECCC, both employing the same constituent code. The simulation results show that for BER of 10−4, without parallelism, TC is 0.4 dB superior to SECCC, whereas, with parallelism of 64, the difference in performance between both schemes reduces to 0.25 dB. It is found that SECCC outperforms TC for frame sizes less than or equal to 2048 bits, when invoking a parallelism of 16, 32 and 64. The BER performance of both schemes shows that SECCC outperforms TC at parallelism of 256 by 0.3 dB at BER of 10−4. Hence, for high throughput architectures employing higher parallelism (beyond 64 and 128) without significant degradation in BER performance, SECCC performs better than TC. The synthesis results of VHDL design of the MAP decoder obtained using Xilinx ISE verify that both schemes have equal clock frequency and resource consumption. It is demonstrated that the MAP decoder achieves the clock frequency of 86.3 MHz which is capable of producing a throughput of 691 Mbps using parallelism of 64.

A tailored fast multipole boundary element method for viscous layer mesh generation

In this study, the fast multipole boundary element method (BEM) is tailored to solve Laplacian equations, aimed at providing smoothed marching directions for the generation of boundary layer elements and overcoming the performance bottleneck in applying classic BEM in this process. A set of speeding-up techniques are thus developed to enable the development of a fast enough viscous mesh generator. The first technique exploits different levels of parallelism within the FMM to fuel the efficient execution of the method on vastly available multi-core computers. The second technique reschedules the marching-direction computing procedure such that overlapped computations are treated only once. The third technique is built on the detailed experimental studies on two parameters of the FMM such that a good trade-off could be achieved between computing efficiency and accuracy. Applying the above techniques as a whole, the developed mesh generator could now treat real configurations at a comparable speed as that of state-of-the-art commercial tools but provide elements with much higher quality. This result convinces us, if conquering the bottleneck in terms of computing time, the BEM is extremely useful for the development of a wide range of meshing techniques.

Parameter tuning evolutionary algorithms for runtime versus cost trade-off in a cloud computing environment

The runtime of an evolutionary algorithm can be reduced by increasing the number of parallel evaluations. However, increasing the number of parallel evaluations can also result in wasted computational effort since there is a greater probability of creating solutions that do not contribute to convergence towards the global optimum. A trade-off, therefore, arises between the runtime and computational effort for different levels of parallelization of an evolutionary algorithm. When the computational effort is translated into cost, the trade-off can be restated as runtime versus cost. This trade-off is particularly relevant for cloud computing environments where the computing resources can be exactly matched to the level of parallelization of the algorithm, and the cost is proportional to the runtime and how many instances that are used. This paper empirically investigates this trade-off for two different evolutionary algorithms, NSGA-II and differential evolution (DE) when applied to a multi-objective discrete-event simulation (DES) problem. Both generational and steady-state asynchronous versions of both algorithms are included. The approach is to perform parameter tuning on a simplified version of the DES model. A subset of the best configurations from each tuning experiment is then evaluated on a cloud computing platform. The results indicate that, for the included DES problem, the steady-state asynchronous version of each algorithm provides a better runtime versus cost trade-off than the generational versions and that DE outperforms NSGA-II.

Hybrid multi-core CPU and GPU-based B&B approaches for the blocking job shop scheduling problem

The Branch and Bound algorithm (B&B) is a well known method for solving optimally Combinatorial Optimization Problems. This method is based on intelligent enumeration of all feasible solutions which reduce considerably the search space. Nevertheless, it remains inefficient when using the sequential approach to deal with large problem instances due to its huge resolutions time. However, the execution time can be reduced considerably by using parallel computing architectures. With the huge evolution of the multi-cores CPUs and GPUs, it is quite hard to design schemes that efficiently exploit the different hardware architectures simultaneously. As a result, most of the existing works focus on exploiting one hardware architecture at a time. In this paper, we propose five parallel approaches to accelerate the B&B execution time using Multi and Many-core systems. Our goal is to solve optimally the Blocking Job Shop Scheduling problem (BJSS) which is one of the hardest scheduling problem. The first proposed approach is a multi-search parallelization based on master/worker paradigm, exploiting the multi-Core CPU-processors. The second and the third approaches represent a GPU-based parallelization schemes having different level of parallelism and GPU occupancy. The fourth and fifth approaches represent a hybridization between the Multi-core approach and the GPU-based parallelization approaches. The goal of this hybridization is to benefit from the power of both the CPU-cores and the GPU at the same time. This hybridization is based on concurrent kernels execution provided by Nvidia Multi process Service (MPS) that allows multiple host processes (Master and workers) to use simultaneously the GPU to launch their kernels in order to accelerate the bounding of one or several nodes at a time. Experiments using the well known Taillard instances confirm the efficiency of our proposals and show a relative speedup of 160x as compared to an optimized sequential B&B algorithm.

Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays

Today’s MPSoCs (multiprocessor systems-on-chip) have brought up massively parallel processor array accelerators that may achieve a high computational efficiency by exploiting multiple levels of parallelism and different memory hierarchies. Such parallel processor arrays are perfect targets, particularly for the acceleration of nested loop programs due to their regular and massively parallel nature. However, existing loop parallelization techniques are often unable to exploit multiple levels of parallelism and are either I/O or memory bounded. Furthermore, if the number of available processing elements becomes only known at runtime—as in adaptive systems—static approaches fail. In this article, we solve some of these problems by proposing a hybrid compile/runtime multi-level symbolic parallelization technique that is able to: (a) exploit multiple levels of parallelism as well as (b) different memory hierarchies, and (c) to match the I/O or memory capabilities of the target architecture for scenarios where the number of available processing elements is only known at runtime. Our proposed technique consists of two compile-time transformations: (a) symbolic hierarchical tiling followed by (b) symbolic multi-level scheduling. The tiling levels scheduled in parallel exploit different levels of parallelism, whereas the sequential one, different memory hierarchies. Furthermore, by tuning the size of the tiles on the individual levels, a tradeoff between the necessary I/O-bandwidth and memory is possible, which facilitates obeying resource constraints. The resulting schedules are symbolic with respect to the problem size and tile sizes. Thus, the number of processing elements to map onto does not need to be known at compile time. At runtime, when the number of available processors becomes known, a simple prologue chooses a feasible schedule with respect to I/O and memory constraints that is latency-optimal for the chosen tile size. In summary, our approach determines the set of feasible, latency-optimal symbolic loop schedule candidates at compile time, from which one is dynamically selected at runtime. This approach exploits multiple levels of parallelism, is independent of the problem size of the loop nest, and thereby avoids any expensive re-compilation at runtime. This is particularly important for low cost and memory-scarce embedded MPSoC platforms that may not afford to host a just-in-time compiler.

Orchestrating parallel detection of strongly connected components on GPUs

Abstract Detecting strongly connected components (SCC) is a practical graph analytics algorithm widely used in many application domains. To accelerate SCC detection, parallel algorithms have been proposed and implemented on GPUs. However, existing GPU implementations show unstable performance for various graphs, especially for real-world graphs, as these implementations do not have a clear understanding of the graph properties. In this paper, we analyze that graphs in SCC detection usually exhibit (1) skewed component sizes (the static property) and (2) dynamically changed graph structure (the dynamic property). To deal with these irregular graph properties, we propose a hybrid method that divides the algorithm into two phases and exploits different levels of parallelism for different-sized components. We also customize the graph traversal strategies for each phase to handle the dynamically changed graph structure. Our method is carefully implemented to take advantage of the GPU hardware. Evaluation with diverse synthetic and real-world graphs shows that our method substantially improves existing GPU implementations, both performance-wise and applicability-wise. It also achieves an average speedup of 5.6 × and 1.5 × over the sequential and OpenMP implementations on the CPU respectively.

Parallelism in Karelian Laments

Parallelism in Karelian Laments Eila Stepanova (bio) Introduction Karelian lament poetry integrates a variety of forms of parallelism—different types of what Roman Jakobson (1981 [1966]:98) described as "recurrent returns"—that are both organizing principles for the poetic discourse and also rhetorical resources that a lamenter can draw on and manipulate in performance. Parallelism operates at the phonic level of sounds, both recurrent sounds in alliteration and recurrent melodic structures. It works in different ways at the level of individual words and formulaic expressions within a phrase. Parallelism is also prominent at the level of larger structural and thematic units. The types of parallelism in Karelian laments work complementarily with one another, and in several respects may also differ from their uses in other traditions. The integrated combination of all these types of parallelism produces Karelian lament as a distinctive form of verbal art. In this opening section of this essay, I introduce the Karelian lament tradition and features of lament performance and poetics. The second section offers an overview of the different types of parallelism at work in Karelian laments. This survey begins with the phonic parallelism of alliteration and parallelism at the level of words and formulae, continues with semantic parallelism of larger units in composition, and finally considers parallelism between the language of laments and the environment where laments are performed. The third section discusses the rhetorical functions of parallelism in laments. Forms of semantic parallelism are shown to be potentially meaningful in themselves. The potential for semantic parallelism between larger units of expression is shown to allow flexibility that makes it a resource for organizing extended sequences of lament poetry. The fourth section turns to the question of how parallelism as a structuring principle of lament can penetrate into a lamenter's way of speaking about laments so that the metadiscourse becomes organized on the same principle. The conclusion considers how all the different levels of parallelism and their flexibility make Karelian lament a dynamic resource for personal expression. Karelians and Karelia Karelians belong to a Finnic linguistic-cultural group with a distinctive language, culture, and ethnic identity. They are historically associated with the transnational territory of Karelia, situated on both sides of today's Finnish-Russian border, which extends from the Gulf of Finland to the White Sea (see Fig. 1). Before the 1930s approximately, the majority population was Karelian. However, the territories of Karelia were greatly disrupted through political conflicts and evacuation, especially during World War II. Today the large area of Karelia is populated by multiple ethnic groups, which include Finns, Russians, Ukrainians, and Karelians. Although Karelian and Russian languages and cultures were markedly different from one another, Karelians in Russia have now been largely assimilated into Russian culture. Karelian language and culture were relatively close to that of Finns; in Finland modernization and mobility have led to a significant degree of assimilation of both those previously residing within today's national borders as well as those who were evacuated to Finland during World War II. Currently, Karelians are a minority in the Republic of Karelia of the Russian Federation as well as in Finland. Among Finnic languages, Karelian is closely related to Finnish, Ižorian, and Vepsian, and more distantly to Estonian, Votic, and Seto. Degrees of similarity in culture and traditions can also be viewed along these lines. At the same time, there is a division between eastern and western Finnic areas. The Finnic cultural areas became divided between East and West, with Russian influence and the Orthodox Church dominant among Karelians, Ižorians, Votes, and Setos, while the Scandinavian influence, the Catholic and later the Lutheran Church were dominant among Finns and Estonians. Click for larger view View full resolution Fig 1. Finnic linguistic-cultural areas, copyright belongs to author. Karelian Lament Poetry Laments—also called dirges, wailing, weeping, or elegies—have been known all over the world and are still found in some contemporary cultures (see Wilce 2009). In most cultures, laments are performed by women, although men also perform them in some exceptional circumstances.1 Scholars generally agree that laments belong to the primordial varieties of folklore, with roots in the cult of the dead (Honko 1974...

Parallel Branch-and-Bound in multi-core multi-CPU multi-GPU heterogeneous environments

We investigate the design of parallel B&B in large scale heterogeneous compute environments where processing units can be composed of a mixture of multiple shared memory cores, multiple distributed CPUs and multiple GPUs devices. We describe two approaches addressing the critical issue of how to map B&B workload with the different levels of parallelism exposed by the target compute platform. We also contribute a throughout large scale experimental study which allows us to derive a comprehensive and fair analysis of the proposed approaches under different system configurations using up to 16 GPUs and up to 512 distributed cores. Our results shed more light on the main challenges one has to face when tackling B&B algorithms while describing efficient techniques to address them. In particular, we are able to obtain linear speed-ups at moderate scales where adaptive load balancing among the heterogeneous compute resources is shown to have a significant impact on performance. At the largest scales, intra-node parallelism and hybrid decentralized load balancing is shown to have a crucial importance in order to alleviate locking issues among shared memory threads and to scale the distributed resources while optimizing communication costs and minimizing idle times.

Fast Edge Detection Architecture using Different Levels of Parallelism on a FPGA

Implementing edge detection techniques on a FPGA has recently become more popular since it benefits high speed which is desired for real-time applications. This work presents a fast FPGAbased architecture for first order derivative edge detection methods. Fast pipeline-based architectures are presented which are able to perform edge detection using different levels of parallelism to accelerate the process. This acceleration includes applying parallelism over convolution masks, edge detection modules and image intensity values. Two different edge detection architectures are proposed called one-way and two-way parallel methods. The architectures are implemented using Verilog HDL for a typical image and we synthesized them for Cyclone IV FPGA. Experimental results show the speed-up near to 460 and 920 for one-way and two-way parallel architectures.

Application-specific coarse-grained reconfigurable array: architecture and design methodology

Coarse-grained reconfigurable arrays (CGRAs) have shown potential for application in embedded systems in recent years. Numerous reconfigurable processing elements (PEs) in CGRAs provide flexibility while maintaining high performance by exploring different levels of parallelism. However, a difference remains between the CGRA and the application-specific integrated circuit (ASIC). Some application domains, such as software-defined radios (SDRs), require flexibility with performance demand increases. More effective CGRA architectures are expected to be developed. Customisation of a CGRA according to its application can improve performance and efficiency. This study proposes an application-specific CGRA architecture template composed of generic PEs (GPEs) and special PEs (SPEs). The hardware of the SPE can be customised to accelerate specific computational patterns. An automatic design methodology that includes pattern identification and application-specific function unit generation is also presented. A mapping algorithm based on ant colony optimisation is provided. Experimental results on the SDR target domain show that compared with other ordinary and application-specific reconfigurable architectures, the CGRA generated by the proposed method performs more efficiently for given applications.

Algorithm 944

We present Talbot Suite, a C parallel software collection for the numerical inversion of Laplace Transforms, based on Talbot's method . It is designed to fit both single and multiple Laplace inversion problems, which arise in several application and research fields. In our software, we achieve high accuracy and efficiency, making full use of modern architectures and introducing two different levels of parallelism: coarse and fine grained parallelism. They offer a reasonable tradeoff between accuracy, the main aspect for a few inversions, and efficiency, the main aspect for multiple inversions. To take into account modern high-performance computing architectures, Talbot Suite provides different software versions: an OpenMP-based version for shared memory machines and a MPI-based version for distributed memory machines. Moreover, oriented to hybrid architectures, a combined MPI/OpenMP-based implementation is provided too. We describe our parallel algorithms and the software organization. We also report some performance results. Our software includes sample programs to call the Talbot Suite functions from C and from MATLAB.

MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder

Using multiprocessor technology is an interesting solution for reducing the processing time of complex video encoders such as H.264/Advanced Video Coding (AVC). This paper details different levels of parallelism presented in related works for H.264/AVC encoder. An efficient Macro Blocks Line level parallelism for the intra prediction encoding chain of H.264/AVC for High Definition (HD) video is proposed. It is implemented on MPSoC architecture using an open and free platform for virtual prototyping named SoCLib. Comparing to related works, the proposed partitioning meets strongly the size of required memory constraint and provides an interesting speed-up. The proposed architecture is based on three processors and ensures a reduced circuit area. Experimental results reveal a run time saving of about 59.8% in terms of processing speed, compared to a classical execution based on a single CPU, without affecting the quality of the reconstructed video. Using multiprocessor technology is an interesting solution for reducing the processing time of complex video encoders such as H.264/Advanced Video Coding (AVC). This paper details different levels of parallelism presented in related works for H.264/AVC encoder. An efficient Macro Blocks Line level parallelism for the intra prediction encoding chain of H.264/AVC for High Definition (HD) video is proposed. It is implemented on MPSoC architecture using an open and free platform for virtual prototyping named SoCLib. Comparing to related works, the proposed partitioning meets strongly the size of required memory constraint and provides an interesting speed-up. The proposed architecture is based on three processors and ensures a reduced circuit area. Experimental results reveal a run time saving of about 59.8% in terms of processing speed, compared to a classical execution based on a single CPU, without affecting the quality of the reconstructed video.

Data Centric Framework for Large-scale High-performance Parallel Computation

Supercomputer architectures are being upgraded using different level of parallelism to improve computing performance. This makes it difficult for scientists to develop high performance code in a short time. From the viewpoint of productivity and software life cycle, a concise yet effective infrastructure is required to achieve parallel processing. In this paper, we propose a usable building block framework to build parallel applications on large-scale Cartesian data structures. The proposed framework is designed such that each process in a simulation cycle can easily access the generated data files with usable functions. This framework enables us to describe parallel applications with fewer lines of source code, and hence, it contributes to the productivity of the software. Further, this framework was considered for improving performance, and it was confirmed that the developed flow simulator based on this framework demonstrated considerably excellent weak scaling performance on the K computer.