Deterministic Test Research Articles

Improving generalization capability of deep learning-based nuclei instance segmentation by non-deterministic train time and deterministic test time stain normalization

With the advent of digital pathology and microscopic systems that can scan and save whole slide histological images automatically, there is a growing trend to use computerized methods to analyze acquired images. Among different histopathological image analysis tasks, nuclei instance segmentation plays a fundamental role in a wide range of clinical and research applications. While many semi- and fully-automatic computerized methods have been proposed for nuclei instance segmentation, deep learning (DL)-based approaches have been shown to deliver the best performances. However, the performance of such approaches usually degrades when tested on unseen datasets.In this work, we propose a novel method to improve the generalization capability of a DL-based automatic segmentation approach. Besides utilizing one of the state-of-the-art DL-based models as a baseline, our method incorporates non-deterministic train time and deterministic test time stain normalization, and ensembling to boost the segmentation performance. We trained the model with one single training set and evaluated its segmentation performance on seven test datasets. Our results show that the proposed method provides up to 4.9%, 5.4%, and 5.9% better average performance in segmenting nuclei based on Dice score, aggregated Jaccard index, and panoptic quality score, respectively, compared to the baseline segmentation model.

A solution method for stochastic multilevel programming problems. A systematic sampling evolutionary approach

Stochastic multilevel programming is a mathematical programming problem with some given number of hierarchical levels of decentralized decision makers and having some kind of randomness properties in the problem definition. The introduction of some randomness property in its hierarchical structure makes stochastic multilevel problems computationally challenging and expensive. In this article, a systematic sampling evolutionary method is adapted to solve the problem. The solution procedure is based on realization of the random variables and systematic partitioning of each hierarchical level’s decision space for searching an optimal reaction. The search goes sequentially upwards starting from the bottom up through the top hierarchical level problem. The existence of solution and convergence of the solution procedure is shown. The solution procedure is implemented and tested on some selected deterministic test problems from literature. Moreover, the proposed algorithm can be used to solve stochastic multilevel programming problems with additional complexity in their problem definition.

X-Masking for Deterministic In-System Tests

Deterministic in-system tests begin to play an essential role in safety-critical applications, in large data centers, or in monitoring silicon aging, to name just a few. All of these ecosystems require periodic, high-quality tests to assure required test coverage and short test application, especially in designs that must test themselves during system operations. In order for deterministic tests to be in-system applicable, they should compact multi-million-bit test responses with unknown (X) values to small signatures. This, in turn, allows for a much faster input-only streaming and a simultaneous reduction of the on-chip-stored test data volume, a system memory, and test time. Typically, the unknown states, whose sources vary from uninitialized memories to unpredictable last-minute timing violations, render signatures unusable. Hence, test response compaction requires some form of protection. This paper presents a user-tunable X-masking scheme. It works synergistically with on-chip test compression logic by employing encoded test data to completely filter out unknown values that otherwise might reach a test response compactor such as a MISR or test result sticky-bits used by the on-chip compare framework. It makes the proposed scheme a very versatile of its kind. Experimental results obtained for several industrial cores show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on various test-related statistics.

Storage-Based Logic Built-In Self-Test With Cyclic Tests

Logic built-in self-test (LBIST) eliminates the need for external test data, and thus facilitates in-field testing. Instead of pseudo-random tests that are typically produced by on-chip test generation logic, storage-based LBIST uses deterministic test data entries, which are stored on-chip, for applying tests that are closer to deterministic tests. This article describes a storage-based LBIST approach that uses a unique type of scan-based tests referred to as cyclic tests. Cyclic tests have cyclic scan enable and scan in sequences, with a higher proportion of functional capture cycles compared with conventional scan-based tests. This results in more clock cycles where fault effects can be captured in the flip-flops. The improved fault detection capabilities this provides helps balance the number of applied tests and the storage requirements. Experimental results for benchmark circuits demonstrate the effectiveness of cyclic tests.

A New Static Compaction of Deterministic Test Sets

Test set compaction is one of the key steps of the postproduction test known to bring down test pattern counts. This, in turn, allows one to reduce the corresponding test data volume, test application time, and hence the cost of testing. This article presents a method that strives to reduce the number of automatic test pattern generation (ATPG)-produced deterministic test patterns to deliver compact test sets. In principle, the new scheme works with a meaningful representation of test patterns by using external and internal necessary assignments (NAs) to determine small groups of potentially compatible faults. These faults are subsequently retargeted by the robust satisfiability (SAT)-based ATPG that produces a single test pattern for the entire group, thus making the resultant test set smaller in size. Experimental results obtained for 12 large industrial cores and stuck-at faults confirm superiority of the proposed scheme over the state-of-the-art test set compaction techniques and are reported herein.

A Test Point Selection Method Based on Fault Response Matrices Framework

This paper presents a novel method for test point selection based on fault response matrices framework. The main purpose of this method is to minimize the set of test points by constructing a fault response matrices framework, to resolve fault effects vanishing and fault detection degradation, and to achieve fewer test point set and higher fault coverage. According to the analysis of the fault response matrices and their derived matrices, the efficiency of the response of each node on the fault is ranked and a new propagation cone for undetectable faults is defined to narrow candidate test point set. We propose a custom testability measure to evaluate the impact of candidate test points on design, and obtain an optimal configuration of the most efficient test points accurately and rapidly. This methodology fully considers the correlation among test points, faults, and test vectors across internal signals resolving timing constraints to increase faults coverage. It can narrow the hard-to-test areas of random test patterns, and reduce the test vector set volume of deterministic test patterns. Our experimental results demonstrate the superiority of the proposed method: higher test coverage, minimum test time, fewer deterministic test patterns, and smaller hardware overhead.

Model Based System Engineering (MBSE) and design assurance process in the context of mitigation of design errors during the development of highly integrated and complex aerospace systems.

Over the years, aircraft and spacecraft designs incorporated highly integrated and/or complex systems that can manage complex scenarios during its operation. In addition to the inherent complexity and/or high level of integration of those systems, the development process applied to aerospace programs is also challenged by other factors: program schedule, budget, multidisciplinary teams, new industry emerging technologies, large number of different processes and procedures that guide the activities along the development life cycle, and others. Given the fact many tasks executed during the development of such systems require human interaction, that yields the introduction of design errors that can contribute to the occurrence of non-desired system behaviors during operation phase. It is already recognized by the civil aviation industry that it is unfeasible to have a deterministic test set to demonstrate that such systems are completely free of such design errors. In that context, a huge effort is applied by the industry, by using qualitative methods to mitigate the occurrence of design errors during the development phases. This paper discusses how MBSE methodology applied together with a design assurance process could prevent such design errors, and presents an analysis showing how some events in aerospace industry where a design error was one of the contributing factors could be avoided.

A Hybrid Test Scheme for Automotive IC in Multisite Testing

This article proposes a hybrid test scheme based on interleaved test applications to increase the efficiency of multisite testing of integrated circuits (ICs) by solving problems related to test coverage, which is an important feature in automotive IC, and test costs, including the number of test pins and the volume of test data. To solve the problems, a hybrid test scheme that combines the merits of broadcast-based scan compression and built-in self-test (BIST) is proposed. The proposed scheme not only generates deterministic test patterns, similar to scan compression, but also requires fewer test pins, similar to BIST, thereby increasing the efficiency of multisite testing. With appropriately designed linear-feedback shift registers (LFSRs) and seeds periodically inserted through the reduced test pins, the test application process combines deterministic testing and random testing. The random testing stage can compensate the seed-insertion time for the subsequent deterministic testing stage and reduce the number of required deterministic patterns by detecting easy-to-detect faults. For further reduction of the volume of test data and hardware overhead, some compatible scan chains (SCs) are grouped and receive test data from an LFSR. The experimental results show that the proposed method increases the efficiency of multisite testing with a reduced pin count.

Quantifying Efforts to Mitigate Interference between an Unmanned Surface Vessel and Starfish 990F for the Identification of Underwater Features in the Littoral Zone

Effective testing of new sensing technologies requires realistic yet deterministic test ranges. The advancements in customizable, adaptive unmanned surface vessels (USV) have contributed to the increasing presence of USVs completing maritime site characterizations of test ranges using commercial off-the-shelf (COTS) sensors such as the Tritech Starfish 990F side-scan sonar. This paper aims to present recommendations for the electromechanical integration of a COTS sonar system onto a capable USV through passive techniques such that underwater objects within the littoral zone of Sand Island, Hawaii, are characterized. Results demonstrated a 49% improvement in the sonar images. Therefore, designers are recommended to fully isolate the sensing system from the USV, physically separate the sonar and USV components, and to establish a baseline performance for the system prior to operation.

Storage-Based Logic Built-in Self-Test With Multicycle Tests

Storing deterministic test data on-chip allows logic built-in self-test (LBIST) to produce a special type of random test that consists of random combinations of deterministic test data. Such tests can achieve a higher fault coverage than random tests whose bits are determined randomly. A bottleneck of this approach is the volume of test data that needs to be stored. This article observes that the use of multicycle tests can address this bottleneck by reducing the number of tests needed for detecting target faults and, thus, the volume of test data needed for producing them. A software procedure is described to support this solution. Experimental results for benchmark circuits demonstrate the effectiveness of multicycle tests in this context.

Upscaled models for time-varying solute transport: Transient spatial-Markov dynamics

Correlated velocity models (CVMs) have proven themselves to be effective tools for describing a wide range of solute transport behaviors in heterogeneous porous media. In particular, spatial Markov models (SMMs) are a class of CVMs where subsequent Lagrangian velocities along transport trajectories depend only on the current velocity, and not on past history. Such models provide a powerful tool for modeling transport in terms of a limited number of flow properties, such as the Eulerian point distribution of (flow) velocities, tortuosity, and the spatial scale of persistence of velocities. However, to date, all SMM modeling frameworks and applications have assumed that the underlying flow is steady-state. In this work, we extend SMMs to the case of time-varying flows. We propose, compare, and validate alternative numerical implementations, and we determine conditions for validity and efficiency based on standard physical quantities used to describe flow and transport at the Darcy scale. The models require additional information relative to a steady-state velocity SMM and we discuss the conditions under which this extra burden is warranted. We also provide clear, deterministic tests for the validity of the transient SMM, termed the “slow variation” and “fast propagation” criteria, which offer clear guidance on when transient, upscaled models are reasonable to employ. Our work forms the basis of a new framework allowing for the application of efficient upscaled models of transport to realistic transient flow conditions.

Evaluation of a Hardware-in-the-loop Test Setup Using Mechanical Measurements with a DFIG Wind Turbine Nacelle

The impact of system test benches on the development and validation of wind energy converters is significantly increasing, and that is due to the higher availability as well as the provided powerful actuator and emulation systems. However, the question remains to be answered about how consistent measurements in the laboratory are. Especially in the case where no field measurements are available for prototypes. The challenge in this regard is the unknown accuracy of simulations and the lack of an experimentally calibrated torque measurement in the hardware-in-the-loop (HiL) setup. The presented paper handles this topic and presents an evaluation method to elaborate measurement consistency independent from field tests. A transparent and comprehensive comparison is provided, taking advantage of the deterministic test environment enabled by the HiL system and the dedicated designed torque measurement adapter. Provided results demonstrate consistent measures obtained from the real-time simulation, HiL control system, and the electrical and mechanical measurements, where a low deviation of up to 2 % is partly observed.

Adaptive Real-Time Characterisation of Composite Precursors in Manufacturing

This paper explores the application of a novel adaptive consolidation sensor framework for the characterisation of composite precursors. The designed framework develops material-driven test programmes in real-time and defines robust material models for the studied composite precursor. The proposed approach allows to remove any subjective judgement about the material behaviour and to reduce human involvement at the experimentation stage. The proposed framework along with the developed data transfer/acquisition hardware setup was put to the test within several characterisation exercises. Two different material systems were tested. The output of the proposed testing method—model and properties for the tested materials—is compared with the results of the conventional deterministic characterisation tests.

Pyrometry-based closed-loop control of the melt pool temperature in Laser Metal Deposition with coaxial wire feeding

Laser metal deposition with coaxial wire feeding is a directed energy deposition process that enables near-net-shape and direction-independent additive manufacturing of metal parts. However, the high sensitivity of the process to disturbances poses a major challenge, as this frequently leads to defective components and rejects. To counteract this, a pyrometer was coaxially coupled into the beam path of the laser processing head to accurately determine the melt pool temperature without limiting accessibility. Applying deterministic test signals, a system model describing the dynamic relationship between the temperature and the laser power was identified. Based on this model, a closed-loop process control was designed. The control system was validated by introducing various disturbances, for which the reference temperature could be tracked with good approximation. The designed temperature control results in reduced effort for tuning the deposition process as well as a lower probability of defects, which saves manufacturing time and cost.

Synchronized Multi-Rate Test Pattern Generation Using Hybrid Twisted Ring Counter and LFSR for BIST Application

This work presents a new approach for built-in test pattern generation (BIST) based on the variable rate clock-driven linear feedback shift register (LFSR) and twisted-ring counters (TRCs). The proposed technique operates on different operating clocks for generating deterministic test pattern sequence for the circuit under test (CUT). The test vectors generated by LFSR are transformed and reproduced with TRC results. The TRC design constitutes of only flip-flops, which be used as a potential alternative to improved seed storage and complex multi polynomial configurations in LFSR.Moreover, the control logic is simplified with synchronized multi-rate clock generation and can be easily extended for any test cubes among multiple CUTs. The randomness characteristics of LFSR are retained with improved memory efficiency and considerable complexity reduction. Experimental results validate the proposed test pattern generator (TPG) over existing well-known LFSRs models, and its randomness is proved with ISCAS benchmark circuits.

The determination of redundant test patterns based on binary matrix symmetry properties

The object of research are digital circuit control tests. The model of a digital circuit is of a grey-box type. Test patterns (impacts) are combinations of logical zeros and ones, applied to circuit inputs. A binary matrix is the response of a digital circuit to input impacts. The examined faults are of «bridging faults» and «stuck-at faults» types. We distinguish the structural units of a test, as well as transformations, maintaining its structure. The measure of binary matrix symmetry is defined. Based on the measure obtained, the criteria are introduced, which help to calculate the utility of another test impact upon a digital circuit. To investigate the criteria, both pseudo-random and deterministic test sequences have been used. Among others, we have observed such algorithmic sequences as a sliding-ONE test, a logarithmic test, a galloping test pattern and a checkerboard test. The proposed approach gives the possibility to identify and exclude the impacts, not carrying useful information, from a test of combinational circuit control. The developed criteria can also be applied to construct memory tests. The analysis of experimental data allows us to make a conclusion about the advisability of using the proposed mathematical apparatus in the theory and practice of digital device testing, as well as in processes of test development.

LOW COST IC TESTER USING PSEUDO-RANDOM APPROACH

Lowcost IC testing is now a burning issue in semiconductor technology. Conventional IC tester, ATE (automatic test equipment), cannot cope with the today’s continuously increasing complexities in IC technology. Deterministic algorithm, which is an idea of 1960’s, is adopted in the ATE. Recently pseudo random testing approach has been emerged as an economically viable alternative to the expensive deterministic testing. This paper introduces a SOC implementing pseudo-random test technique for lowcost IC testing with reliable performance. It is capable of testing combinational circuits as well as sequential circuits with scan-path facilities efficiently. It can also be used for testing PCB interconnection faults.

Storage-Based Built-In Self-Test for Gate-Exhaustive Faults

Built-in self-test (BIST) approaches are suitable for in-field testing since they do not require a tester for storage and application of test data. They also reduce the security vulnerabilities associated with loading and unloading of external test data into scan chains. As technologies evolve, in-field testing needs to address more complex defect and aging mechanisms that require specific deterministic tests. This can be addressed by BIST approaches that store test data on-chip and use the data for on-chip generation of both random and deterministic tests. In this case, there is a tradeoff between the amount of stored test data and the comprehensiveness of the test set that can be applied. This article explores this tradeoff in a specific context that has the following main features: 1) the initial stored test data is based on a stuck-at test set; 2) the target faults are single-cycle gate-exhaustive faults; and 3) the stored test data is enhanced gradually by test data based on a gate-exhaustive test set to increase the coverage of gate-exhaustive faults.

Generating Continuous Deterministic Band-Limited Test Signals With Nearly Laplace Distribution

Generating Continuous Deterministic Band-Limited Test Signals With Nearly Laplace Distribution

Development of the Energy Method and Study of Algorithms for Predicting the Takeoff Trajectory of Aircraft

The article is devoted to the development and research of the method of predicting the events on the trajectory of takeoff, climb and overcome highrise obstacles on the course. The prediction method is based on the energy approach to flight control, created by us in previous works. The mathematical formulation of the method is the energy balance equation describing the mutual influence of all acting forces in the aircraft-engine-environment" system. In this article, the equation is extended to ground modes of movement along the runway. For this, a term is added to the equation that takes into account the action of braking forces from the chassis. The balance equation allows us to directly obtain an algorithm for calculating the length of the forward trajectory required for the accumulation of the required amount of terminal energy. Takeoff trajectory includes ground and air segments. Therefore, the possibility of overcoming the obstacle is fixed by the algorithm at the point of a possible decision to takeoff, taking into account the next air segment. This point is reached before the decision-making airspeed prescribed by the flight manual is reached. This advance warning of the possibility of takeoff improves situational awareness of the pilot, which reduces stress and reduces the risk of erroneous actions. A computer stand was developed for the research. Single launches and series of statistical tests are possible. Takeoff scenarios are generated in the stand operator window, as well as initial runway conditions, atmospheric disturbances, aircraft configuration, and obstacle coordinates are specified. The parameters of random errors in the takeoff weight and centering are assigned, as well as the noise of longitudinal overload measurements are set. A large volume of deterministic and statistical tests of algorithms for predicting events on the takeoff trajectory was performed at the stand. Using the statistical analysis module, the characteristics of the range prediction errors to the take-off decision point and the nose wheel separation point were calculated. Probability densities and histograms of error distribution over five characteristic zones of deviations from the mean are constructed. The confidence intervals for calculating the mathematical expectation are obtained. A prototype of an electronic indicator of the takeoff trajectory with marks of predictive characteristic coordinates has been developed.