Destination Tag Research Articles

Network Status Aware Routing in 3D-CGIN

3D-CGIN is a CGIN providing at least 3 disjoint paths between any communicating pair. It uses alternate source for every sender to ensure availability of 3 disjoint paths. 3D-CGIN is compatible with distance tag routing and destination tag routing schemes. These methods prove quite useful in 3D-CGIN. In the presence of faults, the new path is searched from source to destination. In order to tolerate faults, extra processing is required for selection of new path and diverting/resending the packets on that new path. Generally, the extra processing causes increase in processing time or hop count. To gain the advantage of multiple disjoint paths, we must carefully design the routing scheme, such that, it can minimize extra processing while tolerating the faults. We feel that, use of timely updated network status will certainly help in improving the routing. In 3D-CGIN, we introduce such network status aware strategies. This paper introduces two such schemes, which use pre-computing of routing tags. These methods use the network status to avoid paths with faulty nodes. The paper first discusses the routing in Destination Tag and rerouting. The network 3D-CGIN can tolerate a maximum of 6 faults in worst case, due to the additional link at initial stage. In this paper, we emphasis on various routing strategies those can be used with 3D-CGIN architecture to improve the routing.

A Two-Step Process Gets mRNA Loaded and Ready to Go

​ProteinsProteins are the workhorses of the cell, but to get the most work out of them, they need to be in the right place. In neurons, for example, proteins needed at axons differ from those needed at dendrites, while in budding yeast cells, the daughter cell needs proteins the mother cell does not. In each case, one strategy for making sure a protein gets where it belongs is to shuttle its messenger RNA to the right spot before translating it. In vitro reconstitution experiments with an mRNA-transport complex from yeast identify a quality control step for the incorporation of correct transcripts ... The destination for such an mRNA is encoded in a set of so-called “zipcode” elements, which loop out of the RNA string to link up with RNA-binding proteins. In yeast, these proteins join up with a myosin motor that taxis the complex to the encoded location. While this general picture has become clear in the past several years, details of the transport complex itself have remained murky. In this issue of PLoS Biology, Marisa Muller, Dierk Niessing, and colleagues show that the complex forms in stages, with the final protein added only in the cytoplasm, an event crucial to ensuring the transport complex doesn't pick up passengers who weren't meant to travel. The authors began by showing that a known zipcode element binding protein, called She2p, bound in a similar way to RNAs without the elements as to those with them, suggesting that the job of keeping non-transported RNAs out of the transport complex fell to another protein. Tests of another known complex protein, called Puf6p, were negative, leading the authors to look elsewhere. One candidate was She3p, known to link the complex to the myosin motor. They found that She3p co-purified with She2p, indicating they linked together, and that together they bound tightly to zipcode-containing mRNAs, but not to other RNAs without the address sequences. She3p also interacted with RNAs by itself, albeit weakly, which was a surprise, since its sequence bore no resemblance to other RNA-binding proteins. When She2p was mutated to prevent its linkage to RNA, the ability of the RNA–protein complex to reach its destination was impaired. She2p binds to its target RNAs in the nucleus, but She3p was thought to be a cytoplasmic protein. To test that belief, they examined its distribution in a cell with a temperature-sensitive defect in nuclear export, and saw that even at high temperatures, when nuclear export was shut down, She3p was found only in the cytoplasm, indicating that it, unlike She2p, waits for the nascent transport complex to enter the cytoplasm before it binds on. Based on their results, the authors propose a two-step model of transport complex formation. Within the nucleus, She2p binds to the mRNA as it is transcribed, and then shuttles it to the cytoplasm. She2p binds loosely and promiscuously, though, catching up mRNAs both with and without zipcodes. Once in the cytoplasm, She3p joins on, tightening the grip on mRNAs that contain zipcodes while booting out those without them. With the myosin motor attached to She3p, the complex motors off to its destination elsewhere in the cell. The results in this study indicate that quality control in mRNA transport relies on a reciprocal action: the complex proteins together ensure that only those mRNAs with a destination tag are incorporated into the transport complex, and the mRNA, by binding to each of the proteins in the complex, ensures that all are on board before the journey starts. These findings are an important step forward to understand how mRNAs are transported to their chosen destination in yeast, and opens up the possibility that a similar strategy is followed in other organisms. Muller M, Gerhard Heym R, Mayer A, Kramer K, Schmid M, et al. (2011) A Cytoplasmic Complex Mediates Specific mRNA Recognition and Localization in Yeast. doi:10.1371/journal.pbio.1000611

Design schemes of dynamic rerouting networks with destination tag routing for tolerating faults and preventing collisions

In fault-tolerant multistage interconnection design, the method of providing disjoint paths can tolerate faults, but it is complicated and hard to choose a collision-free path in disjoint paths networks. A network with disjoint paths can concurrently send more identical packets from the source node to increase the arrival ratio or backtrack a packet to the source and take the other disjoint path, but these two methods might increase the collision ratio. In contrast, a dynamic rerouting method finds an alternative path that tolerates faults or prevents collisions. In this paper, we present methods of designing dynamic rerouting networks. This paper presents (1) three design schemes of dynamic rerouting networks to tolerate faults and prevent collisions; (2) design schemes that enable a dynamic rerouting network to use destination tag routing to save hardware cost in switches for computing rerouting tags; (3) a method to prevent a packet from re-encountering the faulty element again after rerouting to reduce the number of rerouting hops and improve the arrival ratio; and (4) simulation results of related dynamic rerouting networks to realize the factors which influence the arrival ratio including the fault tolerant capability and the number of rerouting hops. According to our proposed design schemes and according to our analysis and simulation results, a designer can choose an applicable dynamic rerouting network by using cost-efficient considerations.

Fault-tolerant gamma interconnection network without backtracking

A no-backtracking gamma interconnection network (NBGIN) is a modified gamma interconnection network (GIN) that can tolerate one switch or link fault without backward packet transmission. Basically, this can be achieved by providing two alternative paths at all intermediate nodes during the progression of routing through carefully designed algorithm. In this work, a destination tag routing named as NB function is designed. With this NB function, a packet can find an alternate path as soon as it encounters a switch or link fault in NBGIN. The major advantage of NBGIN over gamma-induced networks is that there is no rerouting penalty under a fault. In addition, NBGIN processes the characteristics of one-fault tolerance, destination tag routing, and dynamic rerouting. Furthermore, the routing and rerouting path can be simply determined by the destination tag only instead of being computed with the routing tag.

Fault-tolerant gamma interconnection networks by chaining

The authors propose two single-fault-tolerant gamma interconnection networks. The first is a partially chained gamma interconnection network (PCGIN) with two disjoint paths between any source-destination pair. A PCGIN has the characteristics of one fault tolerance and destination tag routing, but backtracking may be necessary when a fault occurs. To eliminate the backtracking penalties of a PCGIN, a fully chained gamma interconnection network (FCGIN); that can at least tolerate one link or switch fault at each stage without backtracking, is also proposed FCGIN has the advantages of destination tag routing, lower hardware costs than a PCGIN, low fault penalty, and strong reroutability.

A high-performance ATM switch based on modified shuffle-exchange network

This paper presents an output buffering ATM switch, called modified shuffle-exchange network (MSN) that is obtained by inserting a connection pattern just after every other shuffle-exchange stage. The purpose of modifying a shuffle-exchange network by inserting a connection pattern is to reduce significantly the number of its internal conflicts. Each link of every other stage of MSN has a filter to route successful packets to their destinations. Instead of employing the traditional destination tag routing scheme on MSN, we developed a fast destination tag routing scheme, called FDR, for MSN. In the traditional destination tag routing scheme, the routing tag of a packet is made equal to its destination address. In FDR, however, the routing tag of a packet is determined by its destination address as well as source address. FDR often requires less than log 2 N stages to route a packet from its source to destination, which leads the traffic load to be reduced at the successive stages of the network. An analytical model is presented to analyze the performance of MSN under uniform traffic. Under a variety of traffic models, including uniform, hot-spot, ATM bursty, and output concentration, extensive simulations are run to examine and compare the performance of MSN with two existing similar networks. The simulation results show that MSN with FDR improves the packet loss probability substantially.

Adaptive message routing in a class of fault-tolerant multistage interconnection networks

Multistage interconnection networks (MINs) are often used to provide interconnections in multiprocessor systems. A unique path MIN usually has lower hardware complexity and simple control algorithm, but it lacks fault-tolerance. This paper proposes a class of multipath MINs, which are obtained by adding auxiliary links at the final stage in quad tree networks so that they can provide more paths between each source-destination pair, and presents their routing algorithm which is both destination tag based and adaptive. Starting with the routing tag for the minimum path between a given source-destination pair, the routing algorithm uses a set of rules to select switches and modify routing tag. In addition to trying the auxiliary link when both of the output links are unavailable, the second output link is tried before the auxiliary link when the first output link is unavailable. This feature distinguishes the proposed routing algorithm from the one for quad tree networks and makes better use of all the possible paths between the given source-destination pair. At the end of this paper, an index of performance called capacity is introduced to compare different kinds of MINs. Comparison shows that the proposed MINs have better capacity than quad tree networks.

A kind of Multistage Interconnection Networks with multiple paths

Multistage Interconnection Networks (MINs) are often used to provide interconnections in multiprocessor systems. A unique path MIN usually has lower hardware complexity and a simple control algorithm, but it lacks fault tolerance. This paper proposes a kind of multipath MINs, which are obtained by adding auxiliary links at the final stage in Quad Tree (QT) networks so that they can provide more paths between each source-destination pair, and presents their routing algorithm which is both destination tag based and adaptive. Starting with the routing tag for the minimum path between a given source-destination pair, the routing algorithm uses a set of rules to select switches and modify routing tag. In addition to trying the auxiliary link whenlink 0 andlink 1 are unavailable,link 1 will be tried whenlink 0 is unavailable. This feature distinguishing the proposed routing algorithm from that for QT networks makes better use of all the possible paths between the given source-destination pair. In the end, this paper introduces a performance index, which is calledcapacity, to compare different kinds of MINs. Comparison shows that the proposed MINs have bettercapacity than QT networks.

Sliding Banyan network

The sliding Banyan network is described and evaluated. The novel three-dimensional (3-D) multistage network topology employs a macro-lenslet array in a retroreflective configuration to effect the required shuffle link patterns across a single two-dimensional (2-D) multichip array of pixels. An electronic deflection routing scheme, based on simple destination tag self-routing, is employed within the smart pixels, Internal packet blocking is efficiently avoided because deflected packets are routed through individualized banyan networks that have slid in the time dimension to accommodate each packet's routing needs. Simulations show that this self-routing approach reduces the number of stages, and hence the number of switching and interconnection resources necessary to achieve a specified blocking probability. Experimental focusing and registration results, using arrays of vertical cavity surface emitting lasers, show that conventional optical imaging technology is suitable for this architecture. The results indicate that the sliding banyan approach will overcome the current performance constraints of conventional metallic interconnections and be scalable to ATM switching applications with aggregate throughputs in the Tb/s regime.

CGIN: a fault tolerant modified Gamma interconnection network

To improve the terminal reliability of the Gamma interconnection network (GIN), we consider altering its connecting patterns between stages to attain multiple disjoint paths between any source and destination pair. The new modified GIN, referred to as a CGIN with connecting patterns between stages exhibiting a cyclic feature, is able to tolerate any arbitrary single fault and to lift up terminal reliability accordingly. If several rows of switching elements are fabricated in one chip using the VLSI technology, a CGIN could lead to reduced cost because the pin count per chip decreases and the layout area taken by connections shrinks. To make routing and rerouting in the CGIN more efficient and simpler to implement, destination tag routing and rerouting is also provided.

Destination tag routing techniques based on a state model for the IADM network

A 'state model' is proposed for solving the problem of routing and rerouting messages in the inverse augmented data manipulator (IADM) network. Necessary and sufficient conditions the reroutability of messages are established using this model, and destination tag schemes are derived. These schemes are simpler, more efficient, and require less complex hardware than previously proposed routing schemes. Two destination tag schemes are proposed. A universal rerouting algorithm is constructed based on one of the schemes. It finds a blockage-free path for any combination of multiple blockages if there exists such a path, and indicates the absence of such a path if there exists none. In addition, the state model is used to derive constructively a lower bound on the number of subgraphs which are isomorphic to the indirect binary n-cube network in the IADM network. This knowledge can be used to characterize properties of the IADM networks and for permutation routing in the IADM networks. >

On self-routing in Benes and shuffle-exchange networks

The authors present self-routing algorithms for realizing the class of linear permutations in various multistage networks such as Benes and 2n-stage shuffle-exchange. Linear permutations are useful in providing fast access of data arrays. In the first half of the network, switches are set by comparing the destination tags at their inputs, and, in the second half, switches are set using the Omega self-routing algorithm. It is shown that the comparison operations can be implemented in bit-serial networks without loss of time. In contrast, with the well-known Benes network self-routing algorithm of D. Nassimi and S. Sahni (1981), switches are set by giving priority to the destination tag at the upper input to them. The algorithms presented are useful in providing fast access of various data patterns using interconnection networks cheaper than crossbars. >

Indirect star-type networks for large multiprocessor systems

The authors propose three indirect star-type networks, the indirect star networks I and II and the star-delta network, and investigate their properties. An indirect star-type network is obtained by unfolding the star graph. The star-delta network is obtained through an unfolding scheme based on the recursive property of the star graph, and has n-1 switching stages. The star-delta network has the advantage of being controlled by the destination tag routing scheme. The indirect star-type networks are to the star graph as the indirect cube-type networks are to the n-cube. The authors analyze the performance of the indirect star-type networks under uniform traffic to investigate their potential as an alternative to the indirect cube-type networks for the future high-performance large multiprocessor systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The n-omega: An omega-like topology for distributed-memory multiprocessors

A new processor interconnection topology, the n-omega, is proposed in this paper. The n-omega has a fixed degree of 8 and is shown to have a diameter smaller than log 2 P, where P is the number of processors in the network. An elegant routing mechanism which is a simple extension to the destination tag control of the omega network is presented. The n-omega possesses good fault-tolerant properties and is amenable to easy partitioning. The proposed topology is compared against some existing distributed-memory multiprocessor networks.

The n-omega: An omega-like topology for distributed-memory multiprocessors

A new processor interconnection topology, the n-omega, is proposed in this paper. The n-omega has a fixed degree of 8 and is shown to have a diameter smaller than log2P, where P is the number of processors in the network. An elegant routing mechanism which is a simple extension to the destination tag control of the omega network is presented. The n-omega possesses good fault-tolerant properties and is amenable to easy partitioning. The proposed topology is compared against some existing distributed-memory multiprocessor networks.

The B-network: a multistage interconnection network with backward links

A multistage interconnection network (MIN) for multiprocessor systems is proposed. The proposed MIN, called the B-network, uses backward links to provide backward paths for the requests blocked at switches or memory due to contentions. The gamma network is known to contain a cube network (specifically, the inverse omega network) as a substructure. The B-network is obtained from the gamma network by preserving the cube structure but reversing the direction of all other links. These backward links are used as alternate paths for requests blocked due to path or memory contentions. The B-network can be controlled by the simple destination tag control algorithm; packets navigating through the B-network, using both regular forward links and backward links, can reach their destinations under the destination tag control. The performance of the B-network is analyzed under the uniform traffic model and compared to various networks of interest. It is shown that the B-network surpasses the performance of the gamma network, the crossbar switch, and single-buffered MINs based on (2*2) switches, while having the same hardware complexity as the gamma network.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Destination tag routing techniques based on a state model for the LADM network

A “state model” is proposed for solving the problem of routing and rerouting messages in the Inverse Augmented Data Manipulator (IADM) network. Using this model, necessary and sufficient conditions for the reroutability of messages are established, and then destination tag schemes are derived. These schemes are simpler, more efficient and require less complex hardware than previously proposed routing schemes. Two destination tag schemes are proposed. For one of the schemes, rerouting is totally transparent to the sender of the message and any blocked link of a given type can be avoided. Compared with previous works that deal with the same type of blockage, the timexspace complexity is reduced from Ο(logN) to Ο(1). For the other scheme, rerouting is possible for any type of link blockage. A universal rerouting algorithm is constructed based on the second scheme, which finds a blockage-free path for any combination of multiple blockages if there exists such a path, and indicates absence of such a path if there exists none. In addition, the state model is used to derive constructively a lower bound on the number of subgraphs which are isomorphic to the Indirect Binary n-Cube network in the IADM network. This knowledge can be used to characterize properties of the IADM networks and for permutation routing in the IADM networks.

The Kappa network with fault-tolerant destination tag algorithm

The design of the Gamma network is analyzed in terms of block structure. The analysis reveals the asymmetry of its duplicate links, and an alternate design in the form of the Kappa network is proposed. Its novel feature is the symmetry of duplicate links at the block level. This symmetry results in a simple control algorithm and enhanced fault tolerance. The relationship between the Kappa network and other existing fault-tolerant networks is briefly discussed. >

On the augmented data manipulator network in SIMD environments

Formulas for the number of the augmented-data-manipulator (ADM)-passable permutations were given previously as cross-recurrence relations for the cardinalities of three specific subsets of such permutations. More concise, transparent recurrence formulas are derived utilizing a novel and conceptually simple model of the ADM. As a byproduct, a global control algorithm for the inverse ADM (IADM) is obtained that can set paths for all the IADM-passable permutations. This algorithm can be adapted for the ADM. Also included are two local control algorithms for the IADM/ADM: the signed bit difference tag control and the destination tag control. >

A multipath network with cross links

A fault-tolerant multistage interconnection network, called the H-network, and a fault-tolerant control algorithm for this network are introduced. The novel feature of this network lies in its design, which has connections not only between switching elements of successive stages but also between switching elements of the same stage. The control algorithm is a simple modification of the destination tag algorithm, but it provides for fault tolerance and is dynamic in nature. It is shown that this design technique is effective in reducing hardware, improving fault tolerance, and giving better performance than other fault-tolerant networks with comparable hardware cost.