Desired Circuit Performance Research Articles

Performance-constrained analogue layout retargeting and optimisation with geometric programming

Layout parasitic has crucial influence on the performance of analogue integrated circuits. The paper presents a performance-constrained analogue layout retargeting and optimisation scheme. Geometric programming (GP), is a kind of nonlinear optimisation problem, is used in the method, which can be transferred or fitted into a convex optimisation problem based on mathematical analyses. Then, a global optimum solution can be achieved. To achieve the desired circuit performance, performance sensitivities based on layout parasitic are carried out in the analogue layout optimisation. In addition, a central difference method is applied to control parasitic-related layout geometries by constructing a set of performance constraints subject to maximum performance deviation. At last, a two-stage Miller-compensated operational amplifier and a single-ended folded cascode operational amplifier are simulated with the proposed scheme. The automatically generated target layouts can satisfy performance constraints to ensure the desired specifications. The experimental results show that the scheme can achieve effective retargeting of analogue circuit with less layout area and better circuit performance.

Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach

Layout parasitics can significantly affect the performance of analog integrated circuits (ICs). In this paper, a systematic method of optimizing an existing analog layout considering parasitics is presented for technology migration and performance retargeting. This method represents the locations of layout rectangle edges as variables and extracts circuit and layout integrity such as device symmetry, matching, and design rules as constraints. To ensure the desired circuit performance, bounds of layout parasitics are determined first. These bounds are used to constrain the layout geometries while retargeting existing high-quality layouts across technologies and specification sets. The problem is then solved by a graph-based algorithm combined with nonlinear optimization. The proposed method has been implemented in a parasitic-aware automatic layout optimization and retargeting tool (intellectual property reuse-based analog IC layout). Its efficiency and effectiveness are demonstrated by successfully retargeting operational amplifiers within 1 min of CPU time.

Miniaturized microwave passive filter incorporating multilayer synthetic quasi-TEM transmission line

This paper presents a novel approach to miniaturizing a transmission-line (TL)-based bandpass filter (BPF). The BPF is miniaturized by incorporating multilayer stacked synthetic quasi-TEM TLs made of complementary conducting strip (CCS) metal surfaces. The stacked CCS TLs are separated by a meshed ground plane, whose coupling effect was experimentally shown negligibly to affect desired circuit performance. A brief description of the symmetric third-order TL filter synthesis procedure is reported to map such an idealized BPF to the prototype made of the stacked synthetic CCS TLs. Excellent agreement is obtained by comparing the experimental and theoretical filter frequency responses showing a 2.46-dB insertion loss, a -16.8-dB return loss with under 5% offset of low-side out-band transmission zeros, and a 2% offset of center frequency. A quick estimate of the proposed miniaturized filter design based on synthetic quasi-TEM lines shows that the particular filter prototype approaches the process limit.

Cost-effective applications of power factor correction for nonlinear loads

The objective of this paper is to propose a new approach for designing passive LC compensators by using the penalty function method as an optimization tool. The performance of the cost-effective passive LC compensator for a constant load depends on the appropriate inductor and capacitor selection. Several design methods are reviewed and a novel design methodology is proposed in this paper. By using the proposed method, the designer can quickly find appropriate parameter values to meet the desired circuit performance. Simulated results show that an appropriate combination of the inductor and capacitor selected by the proposed method can meet the desired power-quality requirement. Different cases of design examples are shown in this paper to verify the performance of the proposed design methodology.

Passive filter design using genetic algorithms

The objective of this paper is to propose a new approach for designing a passive LC filter of the full-bridge rectifier by using genetic algorithms (GAs). The performance of the cost-effective passive LC filter for a constant load depends on the appropriate inductor and capacitor selection. Several design methods are reviewed and a novel design methodology using GAs is proposed in this paper. By using the proposed GA program, designer can quickly find appropriate parameter values to meet the desired circuit performance. Experimental results show that an appropriate combination of the inductor and capacitor selected by the proposed GA program can meet the desired power quality requirement. Different cases of design examples are shown in this paper to verify the performance of the proposed design methodology.

Assignment of carry variables in iterative networks

Both sequential circuits (Fig. 1) and iterative circuits (Figs. 2 and 3) are usually designed by first forming a stable table (flow table) describing the desired circuit performance.1?3 In this table the various combinations of signals on the feedback or carry leads (corresponding to the internal states of the circuits) are represented by decimal numbers. It is necessary to assign specific combinations of binary signals to these (decimal) states before the actual circuit design can be carried out. This corresponds to the transition from a state table, such as Table I-A to an output table, such as Table I-B. For a given table, different assignments will usually lead to different circuits which can vary significantly in cost. The problem of minimizing the cost of the equipment can be even more important for iterative circuits since each ?cell? occurs many times in the final circuit. The number of different assignments is so large that it is not feasible to try all different assignments for circuits having more than two internal variables.4 This particular problem of discovering assignments which correspond to economical circuits is still unsolved.