Power Amplifier Design Research Articles

Design of multi-octave power amplifier based on feedback structure of butterworth filter

Design of multi-octave power amplifier based on feedback structure of butterworth filter

Thermal design of a solid-state power amplifier at Q-band

Abstract It is very difficult to cool a new solid-state power amplifier at Q-band, which is composed of some high-power monolithic millimeter-wave integrated circuit chips. Cu/Diamond carriers are used as the heat sinks of the chips, and two layers of heat pipes are sealed in the chassis to reduce the thermal resistance of the amplifier. The thermal design scheme is proved useful by simulating Flotherm and the temperature data from the infrared imager. The study provides an available way for the thermal design of a solid-state power amplifier.

An active two-stage class-J power amplifier design for smart grid’s 5G wireless networks

<span>The wireless communication networks in the smart grid’s advanced metering infrastructure (AMI) applications need 5G technology to support large data transmission efficiently. As the 5G wireless communication network’s overall bandwidth (BW) and efficiency depend on its power amplifier (PA), in this work, a two-stage class-J power amplifier’s design methodology that operates at 3.5 GHz centre frequency by utilizing the CGH40010F model gallium nitride (GaN) transistor is presented. The proposed design methodology involves proper designing of input, output, and interstage matching networks to achieve class-J operation with improved power gain over desired BW using the advanced design system (ADS) electronic design automation (EDA) tool and estimating its integration feasibility through active element-based design approach using the Mentor Graphics EDA tool. The proposed PA provides 54% drain efficiency (D.E), 53% power added efficiency (PAE) with a small signal gain of 27 dB at 3.5 GHz and 41 dBm power output with 21 dB of improved power gain across a BW of around 400 MHz using 28 V power supply into 50 Ω load. By replacing the two-stage PA's passive elements with active elements, its layout size is estimated to be (15.5×29.2) μm2 . The results of the proposed PA exhibit its integration feasibility and suitability for the smart grid’s 5G wireless networks.</span>

Design of an ultra-wideband high-efficiency power amplifier based on multi-paths impedance matching structure

Design of an ultra-wideband high-efficiency power amplifier based on multi-paths impedance matching structure

Doherty Power Amplifier Design via Differential Combining

This paper introduces a novel differential combiner designed to effectively address parasitic capacitances of transistors used in power amplifier (PA) designs with precise compensation at a specified frequency. The combiner consists of a λ/4 transmission line with an integrated capacitor of value 2COUT at its midpoint, which ensures accurate cancellation of parasitic effects. This design connects the drain pins of two transistors, which are considered identical in this configuration. By eliminating the need for complex parasitic compensation techniques, this method significantly simplifies the design process of Doherty Power Amplifiers (DPAs). Extensive simulations validate the effectiveness of this approach, highlighting its potential as a versatile and straightforward solution for next-generation communication systems.

A study on GaN-based high-efficiency class E power amplifier circuits at medium-low frequencies

Abstract In this paper, a high-power amplifier is designed to address the challenges of low transmission power and poor efficiency in wireless energy transmission technology at low frequencies. The design is based on a class E power amplifier circuit. The theoretical analysis is conducted to determine transistor selection and the static DC operating point. Load traction technology is employed to match the load impedance of the power amplifier, ensuring highly efficient and unified power additional efficiency, and output power. To enhance system stability and feedback compensation, gate series resistance and parallel capacitors are incorporated. Simulation results demonstrate that the designed power amplifier achieves an output power of 48 dBm with a power additive efficiency (PAE) of 85%. Furthermore, the third-order intermodulation component reaches 70 dBm, indicating concentrated output energy and high linearity in the amplifier system. Experimental results validate the consistency between theoretical analysis and model simulation, confirming the stability of the designed power amplifier circuit, and successfully achieving energy-efficient, high-power transmission.

Design of highly efficient filtering power amplifier with a wideband response for sub-6 GHz 5G applications

This paper presents the design of a filtering power amplifier (PA) with extra-high power-efficiency and wide bandwidth. To accomplish this, a novel approach is adopted by utilizing a wideband bandpass filter (BPF) as the output matching network (OMN) for the PA. The BPF compromises two paths, where each path consisting of two identical coupled lines that are interconnected to form a ring structure. The suggested configuration eliminates the need for a conventional OMN by integrating the input port of the filter with the drain node of the transistor, resulting in reduced size and losses and improved amplifier performance. The filter concept is illustrated using coupling matrix synthesis. A proof-of-concept filtering PA has been designed using a commercially available 10 W GaN HEMT. This amplifier was designed to operate in the frequency range of 3.0–5.0 GHz, yielding a fractional bandwidth of 50 %. According to achieved results, the drain efficiency and output power are 43.8–70.5 % and 40.2–41.8 dBm, respectively. As a result, the suggested filtering PA demonstrates significant performance in terms of filter bandwidth response and power amplification. Additionally, the proposed filtering PA has a broad operational bandwidth of 3.0–5.0 GHz, which covers the 5G New Radio (NR) n77 (3.3–4.2 GHz), n78 (3.3–3.8 GHz), and n79 (4.4–5.0 GHz) frequency bands.

Design of Doherty power amplifier with power back-off extension based on harmonic tuning and output combining network optimization

This paper proposes a Doherty power amplifier (DPA) design method based on harmonic tuning and output combining network (OCN) optimization to extend the power back-off (PBO) range. Firstly, based on the optimal harmonic load impedance, a harmonic tuning optimization method is used to design the harmonic tuning network of the amplifiers, effectively improving the efficiency at saturation and PBO. Secondly, the fundamental output matching network and the post-matching network are considered as an OCN. The S-parameters of the OCN are calculated and utilized in the DPA design. To further expand the PBO range, the carrier load impedance at PBO is determined by considering the relationship between PBO range and reflection coefficient. Finally, a multi-objective evolutionary algorithm combined with the theory of solution set is used to optimize the OCN design, simplifying the design process of the output matching network. For verification, a high-efficiency DPA operating at 1.68 GHz with a large PBO range of 9.5 dB is designed and measured. Results indicate that the proposed DPA achieves a saturated output power greater than 44 dBm, with a peak efficiency of up to 75.2%. The efficiencies are 68.5% and 61.0% at 6 and 9.5 dB back-off powers, respectively.

An enhanced broadband class-J mode power amplifier for 5G smart meter applications.

Background: With the tremendous increase in the usage of smart meters for industrial/ household purposes, their implementation is considered a crucial challenge in the Internet of Things (IoT) world, leading to a demand for emerging 5G technology. In addition, a large amount of data has to be communicated by smart meters efficiently, which needs a significant enhancement in bandwidth. The power amplifier (PA) plays a major role in deciding the efficiency and bandwidth of the entire communication system. Among the various modes of PAs, a newly developed Class-J mode PA has been proven to achieve high efficiency over a wide bandwidth by maintaining linearity. Methods: This paper proposes a Class-J mode PA design methodology using a CGH40010F-GaN device that operates at a 3.5 GHz frequency to meet the requirements of 5G wireless communication technology for the replacement of existing 4G/LTE technology used for advanced metering infrastructure (AMI) in smart grids. This research's main objective is to design the proper matching networks (M.Ns) to achieve Class-J mode operation that satisfies the bandwidth requirements of 5G smart grid applications. With the target impedances obtained using the load-pull simulation, lumped element matching networks are analyzed and designed in 3 ways using the ADS EDA tool. Results: The simulation results reveal that the proposed Class-J PA provides a maximum drain efficiency (D.E) of 82%, power added efficiency (PAE) of 67% with 13 dB small-signal gain at 3.5 GHz, and output power of 40 dBm (41.4 dBm peak) with a power gain of approximately 7 dB over a bandwidth of approximately 400 MHz with a 28 V power supply into a 50 Ω load. Conclusion: The efficiency and bandwidth of the proposed Class-J PA can be enhanced further by fine-tuning the matching network design to make it more suitable for 5G smart meter/grid applications.

A V-Band Wideband Power Amplifier with High Gain in a 130 nm SiGe BiCMOS Process.

This paper introduces a high-gain wideband power amplifier (PA) designed for V-band applications, operating across 52 to 65 GHz. The proposed PA design employs a combination of techniques, including pole-gain distribution, base-capacitive peaking, and the parallel configuration of multiple small-sized transistors. These strategies enable significant bandwidth extension while maintaining high gain, substantial output power, and a compact footprint. A two-stage PA using the combination technique was developed and fabricated in a 130 nm SiGe BiCMOS process. The PA prototype achieved a peak gain of 27.3 dB at 64 GHz, with a 3 dB bandwidth exceeding 13 GHz and a fractional bandwidth greater than 22.2%. It delivered a maximum saturated output power of 19.7 dBm and an output 1 dB compression point of 18 dBm. Moreover, the PA chip occupied a total silicon area of 0.57 mm2, including all testing pads with a compact core size of 0.198 mm2.

A computational analysis of the impact of thin undoped channels in surface-related current collapse of AlGaN/GaN HEMTs

Abstract This study provides an insight into the impact of thin purely undoped GaN channel thickness (t ch) on surface-related trapping effects in AlGaN/GaN high electron mobility transistors. Our TCAD study suggests that in cases where parasitic gate leakage is the driving trapping mechanism that promotes the injection of electrons from the Schottky gate contact into surface states, this effect can be alleviated by reducing t ch of the undoped GaN channel. We show that by decreasing t ch from 130 to 10 nm, devices exhibit a reduction in gate-related current collapse under the specific class-B RF operating bias conditions as a consequence of a substantial decrease in the off-state gate leakage with reducing t ch. Large-signal simulations revealed an increase by 3 W mm−1 and about 12% output power and power-added efficiency due to the decrease of gate-related collapse. This work, for the first time, highlights the role of a proper purely undoped GaN t ch selection to alleviate gate-related surface trapping in the design of GaN-based microwave power amplifiers.

Temperature Characteristics Modeling for GaN PA Based on PSO-ELM.

In order to solve the performance prediction and design optimization of power amplifiers (PAs), the performance parameters of Gallium Nitride high-electron-mobility transistor (GaN HEMT) PAs at different temperatures are modeled based on the particle swarm optimization-extreme learning machine (PSO-ELM) and extreme learning machine (ELM) in this paper. Then, it can be seen that the prediction accuracy of the PSO-ELM model is superior to that of ELM with a minimum mean square error (MSE) of 0.0006, which indicates the PSO-ELM model has a stronger generalization ability when dealing with the nonlinear relationship between temperature and PA performance. Therefore, this investigation can provide vital theoretical support for the performance optimization of PA design.

Design and fabrication of S-band power amplifier for wireless sensor networks

This paper discusses the process of designing and manufacturing a wideband power amplifier operating in the S-band. To amplify a low power and broadband radio frequency signals from 2.1 GHz to 2.5 GHz, the proposed power amplifier uses a diagram of a two-stages amplification with peak offset amplification frequency 2.3 GHz. The power amplifier is designed with a center frequency difference of 2.2 GHz and 2.4 GHz respectively to achieve a bandwidth of 400 MHz. The proposed power amplifier (PA) uses RF transistor SHF-0589 using gallium arsenide heterostructure field-effect transistor (GaAs HFET) technology for high gain and low power consumption. The complete amplifier achieves power gain 21.1 dB inband 2.1-2.5 GHz and achieve maximum power gain of 22.5 dB at the frequency of 2.4 GHz; the output power rise up to 33 dBm; input reflection coefficient (S11) reaches -19.2 dB and output reflection coefficient reaches -17.2 dB. The designed amplifier circuit can be used for wireless sensor networks operating at S-band.

Design of a broadband high-efficiency power amplifier based on a rectangular double transmission line structure

Abstract This paper presents a design methodology for a broadband high-efficiency power amplifier (PA). The large available impedance space of the extended continuous Class-GF mode is employed. A novel output matching network of the PA consisting of a rectangular double transmission line structure is proposed to meet impedance requirements. To validate the effectiveness of this structure, a high-efficiency PA operating in 0.8–3.0 GHz is designed using a CGH40010F GaN transistor. The measured results demonstrate that the drain efficiency falls within the range of 63.2%–71.9%, the output power varies from 40.2 to 42.2 dBm, and the gain ranges from 9.4 to 11.3 dB within the frequency band of 0.8–3 GHz. The realized PA exhibits an extremely competitive relative bandwidth of 115.8%.

Design of dual-band power amplifier based on microstrip coupled-line bandstop filter

This article presents a simple and effective method for designing a dual-band power amplifier (PA). A microstrip coupled-line bandstop filter (BSF) is cascaded with a broadband PA, thus a notched band can be obtained in the wide operating band, realizing a dual-band characteristic of the PA. The simplified real frequency technique (SRFT) is employed to derive a broadband input matching networks covering the requisite frequency band. Appropriate fundamental impedance and second harmonic impedance matching are achieved at the ideal region of the Smith chart. For validation, an experimental prototype is fabricated and tested using a commercial GaN transistor Cree’s CGH40010F. The proposed dual-band PA is operated at 1.95–2.4 GHz and 2.65–3.1 GHz, with 61%–71% measured power-added efficiency (PAE) and 40.5–41.5 dBm of measured output power.

Analysis and design of hybrid Doherty-Outphasing power amplifier

This paper theoretically analyzes the network phase solution space under Doherty, Outphasing, and hybrid modes. A dual-input wideband Doherty-Outphasing power amplifier (DOPA) design method is proposed. This method can ensure that the output back-off (OBO) amount is further increased based on the OBO amount of Doherty power amplifier. To prove the reliability of the proposed method, a hybrid DOPA power amplifier in the band of 1.7–2.4 GHz with an OBO amount of 12 dB is designed. The experimental results also show that the output power of the hybrid DOPA is 48.6–49.5 dBm in the band of 1.7–2.3 GHz, and the saturation efficiency is 57%–63%. The efficiency at 12 dB, 9 dB and 6 dB OBO is 42%–50%, 46%–59% and 50%–63% respectively. The digital pre-distortion correction is carried out at 1.8, 2.1 and 2.3 GHz frequency points, and the adjacent channel power ratio is lower than -47.7 dBc. Simulation and experiment results can verify the effectiveness and correctness of the proposed method. To the best of our knowledge, it is the first time to achieve such a wide bandwidth to the hybrid DOPA with the proposed design method.

Design of a broadband high-efficiency power amplifier based on ring-resonant filter with compensation architecture and a series of continuous modes

Design of a broadband high-efficiency power amplifier based on ring-resonant filter with compensation architecture and a series of continuous modes

A Low Frequency Power Amplifier Design Based on Output CapacitorLess Circuit

This low-frequency power amplifier utilizes the AT89S51 microcontroller as the main control chip. The system can be divided into several modules: power amplification circuit module, pre-amplification module, band-stop filtering module, protection circuit module, volume control module, power supply voltage, AC voltage, and AC current testing module, A/D conversion module, power module, and single-chip microcomputer subsystem control module. We chose class AB audio power amplifiers. To ensure circuit stability and higher fidelity, we selected the TDA2030 integrated chip to build the OCL power amplifier circuit, preventing efficiency from being too low. Through the control of single-chip microcomputer subsystem, it can measure and display output power, the supply power of the DC power source, and overall efficiency. This system utilizes electronic switches connected with band-stop filters, with the band-stop frequency ranging from 40～60Hz.

Physics‐informed neural network assisted automated design of power amplifier by user defined specifications

AbstractThis article presents a model that can automatically produce a power amplifier's (PA) design parameters, that is, transmission lines (TLs) dimension, from a dataset of user‐specified design goals like gain, efficiency, linearity, and scattering (S‐) parameters. Based on the applied boundary conditions, a synthetic dataset is generated with the best range of design parameters (W and L). This dataset is utilized for training the physics‐informed neural network (PINN) model with user‐specified design goals as input and design parameters as target to produce the optimum value of W and L as the resultant output. Furthermore, utilizing the obtained dimensions, design, simulation, fabrication, and measurement of a PA are performed to validate our proposed model. The results of large signal measurements of PA are drain efficiency (DE) of 26.9%, power added efficiency (PAE) of 24.7%, output power (Pout) of 30.98 dBm at an input power of 19 dBm, and gain of 12.41 dB at an operating frequency of 1.625 GHz. It has been observed that the design parameters produced by the model have a significant agreement with the validated output. Also, the statistical error analysis is done by calculating the error metrics between the validated output and the actual output of the PA design.

Broadband dual-input doherty power amplifier design based on a simple adaptive power dividing ratio function

Broadband dual-input doherty power amplifier design based on a simple adaptive power dividing ratio function