Design Of Matching Networks Research Articles

Analysis and design of output matching network for Doherty power amplifiers

In this paper, a method for designing output matching network is proposed. The impedance matching idea is based on the sufficient condition of the ideal transistors. At this condition, the improved terminal load accommodates to the transistor load at the variation of the input power, which simplifies the design process and increases the matching accuracy. For verification, a Doherty power amplifier is designed and measured. The operating frequency is from 1.75 to 1.95 GHz with the saturated output power of 43.5 dBm to 44.2 dBm. The measured peak drain efficiency is 58.8% to 71.7% and the 6 dB back-off drain efficiency is 50.9% to 61.4%.

Harmonic distortion considerations for an integrated WPT-PLC system

AbstractThis paper presents design considerations for an integrated wireless power transfer (WPT) and power line communication (PLC) system (e.g. WPT-PLC). The main goal is to enable wireless charging of mobile electronic products, along with high data rate communication over the shared wireless inductive resonant channel. Starting from a couple of resonant coils, characterized by the S-parameters matrix, the design of an impedance matching network and decoupling filters is carried out to better decouple power and data signals. A pulse-driven class-E power amplifier (PA) and a rectifier are first conceived based on the measured S-parameters and load-pull characterizations. Second, a sine-driven class-E power link, operating at 6.78 MHz, is proposed to reduce the total harmonic distortion of the integrated WPT-PLC system. These design steps aim to ensure high-power efficiency and low harmonic distortion of the class-E PA in order to mildly affect the channel capacity of the PLC. The harmonic interferences of the pulse-driven and sine-driven class-E power links are compared and discussed, together with the electromagnetic compatibility levels, the channel capacity, and the noise disturbances of the PLC channel in order to guarantee an optimized power and data transfer in the integrated WPT-PLC system.

A 1.5 kW Radio-Frequency Tunable Matching Network Based on Phase-Switched Impedance Modulation

Dynamically-tunable impedance matching is a key feature in numerous radio-frequency (RF) applications at high frequencies (10 s of MHz) and power levels (100s–1000 s of Watts and above). This work develops techniques that enable the design of high power tunable matching networks (TMN) that can be tuned orders of magnitude faster than with conventional tunable impedance matching techniques, while realizing the high power levels required for many industrial applications. This is achieved by leveraging an emerging technique – known as phase-switched impedance modulation (PSIM), which involves switching passive elements at the rf operating frequency – that has previously been demonstrated at rf frequencies at up to a few hundred Watts. In this paper, we develop design approaches that enable it to be practically used at up to many kilowatts of power at frequencies in the 10 s of MHz. A detailed analysis of the factors affecting the losses as well as the tradeoffs of a basic PSIM-based element is provided. Furthermore, it is shown how incorporating additional stages to the PSIM-based element, including impedance scaling and / or the addition of series or shunt passive elements, influences the losses and enables the efficient processing of high power levels given the limitations of available switches. A PSIM-based TMN that matches load impedances to 50 $\,\Omega$ and delivers up to 1.5 kW of power at frequencies centered around 13.56 MHz is implemented and tested over a load impedance range suitable for various industrial plasma processes.

A New Design Methodology for Wideband Analog Predistorter With the Characteristics of Frequency-Dependent Gain and Phase Conversions

A novel design method, which can transform the nonlinear circuits design to the impedance matching network (IMN) design, is proposed for wideband analog predistoter (APD) with the characteristics of frequency-dependent gain and phase conversions in this paper. First, the design method for the desired gain and phase conversions is introduced. The ABCD parameters of the IMN can be computed. To simplify the design, the obtained parameters are transformed to the IMN terminal impedance. Then we can only need to design the IMN terminal impedance to obtain the desired transfer characteristics. In the meanwhile, an APD with 4.5 dB gain conversion and 50° phase conversion is designed and simulated to validate the design method for specify gain and phase conversions. The simulated results show good effectiveness of the design method. Second, for wideband application, the complex gain and phase conversions surface design is transformed to the IMN terminal impendence curve versus frequency design. This gives the designers a well-defined strategy for wideband APD design focusing on frequency-dependent phase conversion as well as gain conversion. To validate the proposed method, a wideband APD operating at K-band (17-20 GHz) is designed, fabricated and measured. A linearized 100W K-band TWTA is shown to achieve a noise power ratio (NPR) >20 dB at 3 dB output power back-off, and phase change <; 6.5° among the operating band.

Class-J23 Power Amplifiers

This paper presents the theoretical introduction and experimental validation of the “Class-J2 Mode Power Amplifier,” which provides higher efficiency and output power compared with conventional class-J mode counterpart. This mode of operation is realized by injection of the second-harmonic current to drain node of a class-J power amplifier (PA) to reduce the 45° phase shift between drain current and voltage signals. Similar to class-J PAs, the second-harmonic impedance of class-J2 PAs is purely reactive to simplify the design of the output matching network. The auxiliary second-harmonic injection circuit comprises a transistor biased in class-B mode followed by a class-C biased amplifier to achieve high second-harmonic current conversion efficiency. Theoretical formulations suggest that a 5% improvement in drain efficiency ( $\eta _{D}$ ) as well as a 1.5-dB increase in output power can be achieved for the class-J2 mode in comparison with the typical class-J operation. To check the accuracy of theoretical predictions, a proof-of-concept 1-GHz class-J2 PA with 12.2-dBm output power and 43% PAE is implemented in a 0.18- $\mu \text{m}$ CMOS technology. For better comparison, a 1-GHz class-J PA with the same transistor size and bias condition as the class-J2 PA is also fabricated. The output power and PAE of the reference class-J PA are 11.4 dBm and 40.6%, respectively, which are in agreement with theoretical predictions.

1.25 GHz – 3.3 GHz broadband solid state power amplifier for L and S bands applications

The research of a single stage broadband solid-state power amplifier based on ATF13876 transistor, which operates in the frequency ranging from 1.25 GHz ~3.3 GHz is presented in this paper. To achieve the broadband performance of the operating bandwidth, a multi-section quarter wave impedance transformer and an approximate transformation of previously synthesized lumped elements into transmission lines are adopted. With neatly design of broadband matching networks and biasing circuit, excellent matching performances and unconditionally stability are achieved over the whole operating bandwidth with a maximum gain of 17.2 dB. The large signal simulation shows that the proposed circuit reaches a saturated output power of 18.12 dBm with a maximum PAE of 27.55% and a 1-dB compression point at 5 dBm input power level. Considering the wide frequency coverage, the features of the proposed design compares favorably with the contemporary state-of-the-art.

Investigation of Input–Output Waveform Engineered Continuous Inverse Class F Power Amplifiers

An in-depth analysis of the continuous inverse Class F power amplifier (PA) accounting for nonlinear input and output active device properties is presented. The analyses show possible ways of exploiting input nonlinearity to improve and maintain PA performance in a broadband operation and propose a flexible source second-harmonic design space which reduces the input matching network (MN) design complexities. Such exploitation of input nonlinearity can also alleviate performance degradation due to dynamic knee behavior of a practical field-effect transistor (FET) in continuous inverse Class F PA operation. The analyses are validated with vector load–pull (VLP) measurements and utilized to implement a broadband PA design. High-drain efficiency (DE) over 75% and output power more than 38 dBm are achieved over 0.8–1.4 GHz at constant 3-dB gain compression.

Optimal Planar Electric Dipole Antennas: Searching for antennas reaching the fundamental bounds on selected metrics

Considerable time is often spent optimizing antennas to meet specific design metrics. Rarely, however, are the resulting antenna designs compared to rigorous physical bounds on those metrics. Here we study the performance of optimized planar meander line antennas with respect to such bounds. Results show that these simple structures meet the lower bound on radiation Q-factor (maximizing single resonance fractional bandwidth), but are far from reaching the associated physical bounds on efficiency. The relative performance of other canonical antenna designs is compared in similar ways, and the quantitative results are connected to intuitions from small antenna design, physical bounds, and matching network design.

Optimal Design of Broadband Matching Networks using Cuckoo Search Optimization Algorithm

In this work, a novel evolutionary optimisation algorithm is introduced for the design of broadband matching networks connecting a resistive source generator and a complex inductive load. Impedance matching networks are the key for full transfer of power to the load. They should offer matching over the entire frequency concerned band. A low noise amplifier (LNA) is also optimised to attain the target gain and noise figure specifications over a definite bandwidth, throughout lumped LC elements. Cuckoo search optimisation algorithm (CSOA) is inspired by the life of a bird family, called cuckoo, offers excellent results with simple tuning parameters compared to previous conventional and meta-heuristic optimisation algorithms. It is extremely powerful in solving engineering optimisation problems. Simulation results for broadband impedance matching networks are presented and analysed and the optimised matching network improves well the performances of the circuit.

Theory and Design of Impedance Matching Network Utilizing a Lossy On-Chip Transformer

In this paper, we present a study on a transformer-based impedance matching network. We use a simplified transformer model comprising two magnetically coupled coils, which are driven by a source and terminated by a load. The formulae of the load and the source impedance for conjugate matching of both sides of the transformer are presented, and a figure of merit is proposed for the evaluation of the power transfer efficiency of the transformer under conjugate matching conditions. Analytical expressions are provided for constructing the widely used transformer network consisting of a resistive load and a parallel tuning capacitor. To verify the proposed work, we examined various on-chip transformers implemented in 0.18 μm CMOS technology. Simulation and measurement results for a matching network synthesized using the aforementioned analytical expressions corresponded well with the result of analysis for operating frequencies up to 72% of the self-resonant frequency of the transformer. The presented results confirm that the proposed analytical formulae based on the simplified transformer model are useful for the design and optimization of transformer-based impedance matching networks in the microwave and millimeter-wave regimes.

Optimal design of broadband matching networks using cuckoo search optimisation algorithm

In this work, a novel evolutionary optimisation algorithm is introduced for the design of broadband matching networks connecting a resistive source generator and a complex inductive load. Impedance matching networks are the key for full transfer of power to the load. They should offer matching over the entire frequency concerned band. A low noise amplifier (LNA) is also optimised to attain the target gain and noise figure specifications over a definite bandwidth, throughout lumped LC elements. Cuckoo search optimisation algorithm (CSOA) is inspired by the life of a bird family, called cuckoo, offers excellent results with simple tuning parameters compared to previous conventional and meta-heuristic optimisation algorithms. It is extremely powerful in solving engineering optimisation problems. Simulation results for broadband impedance matching networks are presented and analysed and the optimised matching network improves well the performances of the circuit.

Class-J SiGe &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$X$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Band Power Amplifier Using a Ladder Filter-Based AM–PM Distortion Reduction Technique

In this paper, a class-J power amplifier for operation in the X-band realized in SiGe bipolar technology is presented. The proposed design combines the high efficiency of class-J operation with solutions to mitigate AM-PM distortion down to a level compatible with high spectral efficiency modulation schemes like 64-QAM. The design of a transformer-based output matching network and the trade-off between efficiency and pure class-J operation related to a non-ideal second harmonic termination are discussed. The main sources of AM-PM distortion are identified in the base-emitter and collector-based bipolar junction transistor capacitance variation with power level and solutions that make the design less sensitive to these impairments are proposed. Linear MIM capacitors are used at the power amplifier (PA) core output to realize the proper class-J second harmonic termination, while an input matching network based on a Bessel ladder filter is adopted to make the signal phase at the PA core input less sensitive to base-emitter capacitance variation. A class-J PA previously designed for maximum power-added efficiency (PAE) is used as a reference throughout the paper to highlight the trade-off’s entailed by AM-PM distortion reduction. The designed PA features a peak gain of 15 dB at 10 GHz and 8-to-12 GHz −3 dB bandwidth. The saturated power is 22 dBm with a 33% PAE, while the output $p_{1\,\text {dB}}$ is 19 dBm. The AM-PM distortion at $p_{1\,\text {dB}}$ is 5 degrees.

Highly Linear High-Frequency Low-Noise Amplifier Design at ISM Band

A highly linear high-frequency low-noise amplifier is one of the important components in telecommunication receivers. The purpose of making such amplifiers is to amplify received signal from transmitter (antenna) at an acceptable level. A narrow band highly linear low-noise amplifier was studied and designed in this paper. A BFP720 bipolar transistor from Infineon Company associated with ADS software was used. Low-noise amplifier was initially designed and simulated and its results were obtained. Lumped elements of inductor and capacitor were used in the design of input and output matching network of this circuit, and two amplifier circuits were then designed and some techniques and methods proposed to improve its performance.

Performance-reliability trade-offs in short range RF power amplifier design

In this work, trade-offs between performance and reliability in CMOS RF power amplifiers at the design stage are studied. The impact of transistor sizing, amplifier class and on-chip matching network design are explored for a 130 nm technology and the implications of design decisions in transistor gate oxide reliability are discussed and projected. A strong trade-off is observed between efficiency and reliability, mainly for different on-chip output matching architectures. A comparison between two example designs is performed via SPICE simulations that include reliability models and the effects of aging on the stress conditions of each amplifier.

Equivalent circuit model of a rectangular RF driven hydrogen ion source for impedance matching network design

KAERI is presently developing a rectangular RF driven deuterium ion source for both neutron source and fusion applications. For a model-based design of a reliable impedance matching network for the ion source, we extend an equivalent circuit model of the ion source system by allowing effects of an isolation transformer and a Faraday shield on the system to be reflected in our previous model (Huh et al., 2017 Fusion Eng. Des.121 337). In this paper we use the model to investigate the trends in external electrical characteristics of the ion source system (e.g., voltage and current across and through an RF antenna coil and the impedance matching network circuit components) with RF power of up to 50 kW. The model results provide criteria for the impedance matching network design and data for an assessment of the ion source performance.

Second Harmonic Treatment Technique for Bandwidth Enhancement of GaN HEMT Amplifier With Harmonic Reactive Terminations

Source and load impedance conditions for the second harmonics have a great influence on the efficiency of amplifiers. The bandwidth of high-efficiency operation is limited, since efficiency is drastically degraded due to a slight change in source-side second harmonic impedance from the optimum point. For this reason, to avoid steep efficiency degradation, a source-side second harmonic impedance control is introduced. In addition, a harmonic treatment network, which reduces the influence on matching-network design, is also described here. A fabricated GaN HEMT amplifier has achieved a maximum power-added efficiency (PAE) of 79% with a saturated output power of 48.0 dBm at 2.02 GHz. The amplifier has also achieved a high-efficiency characteristic of more than 70% PAE in the frequency range from 1.68 to 2.12 GHz.

Design Approach for Implementation of Class-J Broadband Power Amplifiers Using Synthesized Band-Pass and Low-Pass Matching Topology

A new synthesis method for the design of broadband impedance matching network has been introduced to match the transistor input. The proposed matching network would be a realistic alternative to those that are frequently designed in low-pass structure. Easy-to-use design equations are given for this filter-based matching network. The required impedance of the stubs and the connecting lines can be directly calculated from the equations. This synthesis method simplifies the implementation of the network in the distributed form as compared with the LC low-pass matching network where equivalences are necessarily required in the rough conversion from lumped-to-distributed elements. The high-efficiency mode of operation is guaranteed by the constructed output low-pass matching network, since the LC low-pass network can provide the prescribed load terminations at fundamental frequencies and at harmonics. A commercially available 10-W GaN HEMT device (CGH40010) was used in this investigation. The proposed broadband power amplifier exhibits band-pass Chebyshev response in S-parameter measurements, and yields good gain flatness (±0.5 dB) and input return loss (>13 dB). Power-added efficiency of 58%-72% has been measured in large-signal measurements. After digital predistortion, the measured adjacent channel leakage power ratio is below -50 dBc at ±5- and ±10-MHz offset, when driven by 5- and 10-MHz WCDMA signals at 7-dB power back off.

Sub‐optimal matching method for dual‐band class‐J power amplifier using real frequency technique

A passive network possessing an input impedance which is positive real in nature poses difficulties with regard to obtaining an optimal impedance for power amplifiers (PAs) with two uncorrelated frequencies. In this context, this study presents a sub-optimal dual-band matching method via real frequency technique. Theoretical analysis is presented for voltage waveform with four independent variables and boundary conditions are given for not lower than zero region. To increase the possibility of acquiring a matching network, a sub-optimal but broad design space is defined according to acceptable performance. It is more practical to match dual-band or broadband PAs because a single fundamental harmonic impedance point could be corresponding to a set of the second harmonics in the new design space, vice versa. Thus, the sub-optimal solution space is bounded from region-to-region between the required fundamental and second harmonic impedances. An enhanced cost function based on driving point function that could better describe harmonic impedance mismatching degree is also proposed for harmonics control. Finally, a dual-band PA is designed to demonstrate the general matching method. The peak efficiency is about 70% and saturated output power is 41 dBm in both bands.

A Novel Design Approach for Highly Efficient Multioctave Bandwidth GaN Power Amplifiers

This letter presents a novel approach to design highly efficient multioctave bandwidth power amplifiers (PAs). The fundamental load impedances are slightly detuned out of their optimum values to reduce the in-band harmonics influence on output power and power-added efficiency. The design of the output matching network includes a 4:1 planar Guanella transformer for wide bandwidth and low complexity. In the frequency band 0.5–2.7 GHz, the PA achieves 9.2 ± 1.2 dB power gain and more than 20-W output power. The drain efficiency varies from 56% to 70% over the bandwidth.

Design of impedance matching circuits for RF energy harvesting systems

This paper presents a systematic design methodology for impedance matching circuits of an RF energy harvester to maximize the harvested energy for a range of input power levels with known distribution. Design of input matching networks for RF rectifier differs from those for traditional RF circuits such as low-noise amplifier because the transistors in the RF rectifiers operate in different regions. In this work, it is shown that the input impedance of the rectifier estimated based on small signal simulation of transistors at the peak of input signal in the rectifier when the transistors are biased with stable DC operating voltage provides the largest harvested energy from a fixed input power. For variable input power levels, a matching network selection strategy is proposed to maximize expected harvested energy given the probability density distribution of input power levels. As an experimental sample, an RF energy harvester circuit is designed to maximize the harvested energy in the 902–928MHz band employing an off-chip impedance matching circuit designed using the proposed methodology. The proposed RF energy harvester exhibits a measured maximum power conversion efficiency (PCE) of 32% at −15dBm (32μW) and delivers an output DC voltage of 3.2V to a 1MΩ load.