Low-power Circuit Design Research Articles

A Novel Design Approach of Low Power Consuming Decoder using Reversible Logic Gates

In current scenario, the reversible logic design is attracting more interest due to its low power consumption. Reversible logic is very important in low-power circuit design. The important reversible gates used for reversible logic synthesis are Feynman Gate, Fredkin gate, toffoli gate, new gate and peres gate etc. Reversible Logic requires non-destruction of information. Therefore the number of inputs must be equal to the number of outputs. (If there were more outputs than inputs, the reverse direction wouldn't be reversible!). This paper presents a compact realization of quantum n-to-2n decoder circuit, where n is the number of input bits. The proposed design of the decoder circuit shows that it is composed of the quantum 2-to-4 decoder circuit. We present a decoder circuit using simple Feynman gate and tofolli gates. Designed circuit performs better than the existing ones, e.g., the proposed decoder circuit improves on the number of gates, delay, area and power. We simulated the circuit using cadence tool in both analog and digital.

Novel Design of Reversible MUX and DEMUX using GDI Techinque

Now a day’s Reversible logic is playing a crucial role in designing of digital circuits and it is used in reducing power consumption in digital design. By regaining the bit loss it reduces the power consumption in digital circuits. Gate diffusion input (GDI) is a technique of low-power digital circuit design. This technique reduces the power consumption, delay, and transistor count by maintaining the complexity very low of logic design. In these paper a novel MUX and DEMUX has been presented, which can be extended up to 1:2n and 2n:1 respectively and these are developed by using only one type of Reversible gate i.e. Fredkin Gate (FRG) and Not Gate. The simulations are done in H-Spice using 90nm technology.

Evaluation and optimization of short channel ferroelectric MOSFET for low power circuit application with BSIM4 and Landau theory

Based on BSIM4 parameters of 45nm metal gate/high-k CMOS process and Landau theory, gate and output characteristics of short channel ferroelectric MOSFET (FeFET) are evaluated to explore its optimal structure for low power circuit application. Unlike previously reported simulation results of long channel FeFET, our work reveals that its current–voltage performance is quite susceptible to the parasitic capacitance between the gate and drain. As a consequence, there is a large threshold voltage increase with drain voltage and output characteristics hardly get saturated, indicating that short channel FeFET is not suitable for analog circuit applications. One effective way to address the issues is to minimize the gate-to-drain parasitic overlap and fringing field capacitances. With the tool Purdue Emerging Technology Evaluator, the inverter performance consisting of modified FeFETs is also simulated. Compared with intrinsic inverter, its energy consumption per cycle is much lower at any supply voltage VDD and the propagation delay is also smaller at very low VDD. Our work shows that the optimized FeFET structure, designed by mitigating gate-to-drain parasitic, is suitable for both analog and digital low power circuit designs.

Design of Low Voltage Low Power OP-AMP using DTMOS Technique

ABSTRACT This paper demonstrates the design of low voltage, low power CMOS op-amp using DTMOS technique for low-power applications. The design goal is to achieve high gain, phase margin and minimum power dissipation at lower supply voltage. DTMOS transistor is proposed in this paper for the design of op-amp which replaces the normal CMOS transistors for designing a low power, low voltage two stage op-amp. A dc gain of 96.38 dB, a phase margin of 71.46o by achieving a unity gain bandwidth of 4.077 MHz while operating at 1V supply voltage. The performed simulation results show a power dissipation of 12.19 µW is achieved under 5 pF load in this design. The design and analysis is performed using 180 nm CMOS technology in Cadence Virtuoso ADE . Keywords Low power applications, Diff-amp, op-amp, DTMOS, Low power, Low voltage . 1. INTRODUCTION From the past few years due to the extensive growth of market for portable devices such as cell phones, portable computers, other low power applications and also the design of analog circuits which requires low power, low voltage with high performance has become an important issue now a day’s [2]. One of the limitations for implementation of portable devices and design of other low power circuits at low voltage is the threshold voltage (V

Key characterization factors of accurate power modeling for FinFET circuits

Due to its excellent device features, manufacture process compatibility and diversity of the circuit structures, The FinFET is considered appropriate candidate for the conventional bulk-MOSFET in sub-22nm technology nodes. However, the power estimation CAD tools for FinFET are missing at the moment, which mainly results from the absence of FinFET power analysis and FinFET power model. Three key factors for FinFET power model are: the dimension of the look-up-tables, that to find out the most significant factors that influence FinFET power and to make them as indexes for the look-up-tables; the distance between sampling points; and the interpolation method. In this paper, various factors that may contribute to the FinFET power consumption are evaluated. Of all the factors, the continuous ones are compared with sensitivity method. As to other discrete factors, methods of building them in power model are given according to the features of the each factor and the way it influences the power. Based on the simulation result, standard cell power library model for FinFET is proposed. The research work lays foundation for accurate power analysis and modeling for high-level power analysis of FinFET circuits. Besides, these key factors are also crucial for low-power FinFET circuit design.

A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology

Sub-threshold leakage is a major issue for low power circuits design, especially for SRAM design in SoC. Sub-threshold leakage can be decreased by scaling down supply voltage. However, this may dramatically increase the circuit delay. In this paper, we propose a novel 6 T SRAM array structure with a switch module which operates in the near threshold region to reduce the leakage current. In order to verify our proposed leakage reduction scheme, we designed and simulated an 8192 kB SRAM array based on a 16 KB single port SRAM cell memory model in 55 nm process. Several 6 T SRAM Array instances are implemented in 55-nm 1P6M CMOS technology to measure the standby current of the proposed scheme as well. With the proposed technique, we achieved 28.3% reduction for leakage current compared to traditional 6 T SRAM array, in standby mode where gate leakage is dominant. The total penalty is 2% area increase and 1% speed reduction.

Design of Fully Integrated Impedimetric CMOS Biosensor for DNA Detection

This paper described a label-free and fully integrated impedimetric biosensor using standard Complementary Metal Oxide Semiconductor (CMOS) technology to measure both capacitance and resistance of the electrode-electrolyte interface. Conventional impedance biosensors usually use bulky and expensive instruments to monitor the impedance change. This paper demonstrates a low power, high gain and low cost impedance readout circuit design for detecting the biomolecular interactions of deoxyribonucleic acid (DNA) strands at the electrode surface. The proposed biosensor circuit is composed of a transimpedance amplifier (TIA) with two quadrature phase mixers and finally integrated with 5μm x 5μm microelectrode based on 0.18μm Silterra CMOS technology process with 1.8V supply. The output value of the readout circuit is used to estimate the amplitude and phase of the measured admittance. The developed TIA can achieve a gain of 88.6dB up to a frequency of 50MHz. It also has very good linearity up to 2.7mA and the overall dynamic range is approximately 90dB.

Low Leakage Circuits Design with Optimized Gate-length Biasing

With the technology process scaling, leakage power dissipation is becoming a growing number of percentage in total power dissipation. This study presents a new method in the gate-length biasing technique to achieve a cost-effective gate-length with a most benefit between leakage reduction and delay increasing. With the optimized gate-length, typical combinational and sequential circuits are realized and simulated using HSPICE with the BSIM4.6.4 predictive models at a 45nm COMS process. The results show that leakage currents of typical combinational circuits reduce more and delay increase less. Moreover, leakage currents of mirror adder and transmission gate adder decrease 13.9% and 8.90%, respectively; and leakage power of 4-bit binary counters using C 2 MOS D Flip-Flop and Transmission-Gate D Flip-Flop reduce 38.36% and 20.05%, with the frequency of 5M, respectively. Therefore, the optimized gate-length biasing technique is an attractive approach in low power circuits design. DOI : http://dx.doi.org/10.11591/telkomnika.v12i4.4791

ANALYSIS OF DIFFERENT TYPES OF CURRENT MIRROR IN 45NM TECHNOLOGY

Momentarily the analog electronics has made low vol tage, low power circuit designs extremely adorable . As power is the product of supplied voltage and flowing current through the circuit so power id directly varies with supplied voltage .That means reducing supply voltage is a direct way to achieve low power consumption. Low Voltage and low power current mir rors are essential blocks of analog IC design.

Power Efficient Design of Multiplexer based Compressor using Adiabatic Logic

Demand of low power circuits design is increasing due to the large growth in portable digital equipment. In this reference adiabatic structure are used that provides a dramatic reduction in power dissipation by recycling some of the energy from output load capacitor and saving power in upper half of the network instead of dissipated as heat. In this paper a low power multiplexer based 4-2 compressor is designed using Positive feedback adiabatic logic. The compressor design is simulated at 0.12μm technology using Microwind 3.1. Simulated results shows that proposed design saves 54.9% power than conventional CMOS based compressor.

Asynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops

For synchronous designs, a large portion of the total power consumption of the integrated circuit (IC) is due to the storage elements and the clock distribution. Energy efficiency from the clock elements plays a critical role in low-power circuit design. One technique for efficiency is the use of double edge-triggered flip-flops (DETFFs), since they can maintain the same throughput as single edge-triggered flip-flops (SETFFs) while only using half of the clock frequency. Clock gating is another well-accepted technique to reduce the dynamic power of idle modules or idle cycles. However, incorporating clock gating with DETFFs to further reduce dynamic power consumption introduces an asynchronous data sampling (i.e., a change in output between clock edges) that was not addressed in previous research. This asynchronous data sampling is explored in detail in this paper by analyzing the mechanisms of several different clock-gated DETFFs. Three special clock-gating strategies are evaluated to mitigate this issue in DETFFs. Each of these three solutions has limitations, and the respective tradeoffs are discussed.

Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)

The theoretical lower limit of subthreshold swing in mosfets (60 mV/decade) significantly restricts low-voltage operation since it results in a low ON -to- OFF current ratio at low supply voltages. This paper investigates extremely low-power circuits based on new Si/SiGe heterojunction tunneling transistors (HETTs) that have a subthreshold swing of . Device characteristics, as determined through technology computer aided design tools, are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that an HETT-based ring oscillator (RO) shows a 9-19 times reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional mosfets, namely, asymmetric current flow and increased Miller capacitance, analyze their effect on circuit behavior, and propose methods to address them. HETT characteristics have the most dramatic impact on static random access memory (SRAM) operation and we propose a novel seven-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7-37 times reduction in leakage power compared to CMOS.

Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design

In this paper, novel non-conventional techniques,11Note: In this paper the presented techniques are a national patent application registered by the Industrial Property Office in the Czech Republic under registration number 303698, for year 2013 [56]. named by the author of this paper “bulk-driven floating-gate (BD-FG)” MOS transistor (MOST) and “bulk-driven quasi-floating-gate (BD-QFG) MOST” for low-voltage (LV) low-power (LP) analog circuit design are presented. These novel techniques appear as a good solution to merge the advantages of floating-gate (FG) and quasi-floating-gate (QFG) with the advantages of bulk-driven (BD) technique and suppress their disadvantages. Consequently, the transconductance and transient frequency of BD-FG and BD-QFG MOSTs approach the conventional gate driven (GD) MOST values. Furthermore, a novel LV LP class AB second generation current conveyor based on BD-FG MOST is presented in this paper as an example. The supply voltage is only ±0.4V with a rail-to-rail voltage swing capability and total power consumption of mere 10μW. PSpice simulation results using the 0.18μm P-well CMOS technology are included to confirm the attractive properties of these new techniques.

A 2-Kb One-Time Programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 $\mu$m CMOS Process

We present a 2-Kb one-time programmable (OTP) memory for UHF RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Reliability of memory cell is enhanced by limiting the maximum terminal voltages of thin-oxide and thick-oxide transistors to 1.8 V and 3.3 V, respectively. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. To further reduce power consumption, we develop a novel power-efficient charge pump. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 m 1-poly 6-metal standard CMOS process with no additional masks. The total area of the chip including the I/Os and bonding pads is 2.3 × 1.5 mm2 where the OTP memory area is only 0.43 × 0.31 mm2. Our tag IC measurement shows that the read and write currents of the OTP memory are 17 μA and 58 μA, respectively.

A wireless and batteryless microsystem with implantable grid electrode/3-dimensional probe array for ECoG and extracellular neural recording in rats.

This paper presents the design and implementation of an integrated wireless microsystem platform that provides the possibility to support versatile implantable neural sensing devices in free laboratory rats. Inductive coupled coils with low dropout regulator design allows true long-term recording without limitation of battery capacity. A 16-channel analog front end chip located on the headstage is designed for high channel account neural signal conditioning with low current consumption and noise. Two types of implantable electrodes including grid electrode and 3D probe array are also presented for brain surface recording and 3D biopotential acquisition in the implanted target volume of tissue. The overall system consumes less than 20 mA with small form factor, 3.9 × 3.9 cm2 mainboard and 1.8 × 3.4 cm2 headstage, is packaged into a backpack for rats. Practical in vivo recordings including auditory response, brain resection tissue and PZT-induced seizures recording demonstrate the correct function of the proposed microsystem. Presented achievements addressed the aforementioned properties by combining MEMS neural sensors, low-power circuit designs and commercial chips into system-level integration.

Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model

The recently proposed BSIM6 bulk MOSFET compact model is set to replace the hitherto widely used BSIM3 and BSIM4 models as the de-facto industrial standard. Unlike its predecessors which were threshold voltage based, the BSIM6 core is charge based and thus physically continuous at all levels of inversion from linear operation to saturation. Hence, it lends itself conveniently for the use of a design methodology suited for low-power analog circuit design based on the inversion coefficient (IC) that has been extensively used in conjugation with the EKV model and allows to make simple calculations of, for example, transconductance efficiency, gain bandwidth product, etc. This methodology helps to make a near-optimal selection of transistor dimensions and operating points even in moderate and weak inversion regions. This paper will discuss the IC based design methodology and its application to the next generation BSIM6 compact MOSFET model.

Design of ternary counter based on adiabatic domino circuit

By researching the ternary counter and low power circuit design method, a novel design of low power ternary Domino counter on switch-level is proposed. Firstly, the switch-level structure expression of ternary loop operation circuit with enable pin is derived according to the switch-signal theory, and the one bit ternary counter is obtained combining the ternary adiabatic Domino literal operation circuit and buffer. Then the switch-level structure expression of enable signal circuit is derived, and the four bits ternary counter is obtained by cascade connection. Finally, the circuit is simulated by Spice tool and the output waveforms transform in proper order indicating that the logic function is correct. The energy consumption of the four bits ternary adiabatic Domino counter is 63% less than the conventional Domino counterpart.

Low Power and High Speed D-Latch Circuit Designs Based on Carbon Nanotube FET

In this paper we propose low power and high speed D-latche circuits base on carbon nanotube field effect transistor. D-latches are the important state-holding elements and systems performance enhancement will be achieved by improving the flip-flop latches structure. The circuit designs are simulated by Hspice .In this paper the consumption result of the circuit parameters such as delay, power and PDP for our three different D-latch circuit design in various voltages and different temperatures.

High-Precision Differential-Input Buffered and External Transconductance Amplifier for Low-Voltage Low-Power Applications

Recently, the demand for low-voltage low-power integrated circuits design has grown dramatically. For battery-operated devices both the supply voltage and the power consumption have to be lowered in order to prolong the battery life. This paper presents an attractive approach to designing a low-voltage low-power high-precision differential-input buffered and external transconductance amplifier, DBeTA, based on the bulk-driven technique. The proposed DBeTA possesses rail-to-rail voltage swing capability at a low supply voltage of ±400 mV and consumes merely 62 μW. The proposed circuit is a universal active element that offers more freedom during the design of current-, voltage-, or mixed-mode applications. The proposed circuit is particularly interesting for biomedical applications requiring low-voltage low-power operation capability where the processing signal frequency is limited to a few kilohertz. An oscillator circuit employing a minimum number of active and passive components has been described in this paper as one of many possible applications. The circuit contains only a single active element DBeTA, two capacitors, and one resistor, which is very attractive for integrated circuit implementation. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to prove the unique results.

Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).