Low-power Circuit Design Research Articles

Surface-Potential-Based Analytical Model of Low-Frequency Noise for Planar-Type Tunnel Field-Effect Transistors

Analytical models of low-frequency noise (LFN) characteristics for planar-type tunnel field-effect-transistors (TFETs) are proposed. A surface-potential-based current-voltage model is developed to physically represent the current fluctuation due to charge trapping/detrapping in the gate dielectric. An LFN model can be analytically derived from the current fluctuation with a reasonable approximation. The proposed model is verified using Technology Computer Aided Design (TCAD) and measurement data, which are in good agreement with each other. The analytical model can not only serve as a valuable reference and tool for low-power analog circuit design but also provide physical insights into the LFN of TFETs.

Low power circuit design using NCL based asynchronous method

The null convention logic (NCL) based circuit design methodology eliminates the problems related to noise, clock tree, electromagnetic interference and also reduces significant power consumption. In this paper, we would like to demonstrate the advantage of low power consumption of the NCL based asynchronous circuit design on a large design scale, thus we used the advanced encryption standard (AES) encryption design as an illustrative example. In addition, we also proposed two pipelined AES encryption models using the synchronous circuit design technique and the asynchronous circuit design technique based on NCL. Besides, these two models were realized by using version control system (VCS) tool to simulate and Design Compiler tool to synthesize parameters in power consumption, processing speed and area. The synthesis results of these two models indicated that power consumption of the NCL based asynchronous AES encryption model had a decrease of 71% compared with the synchronous AES encryption model. Moreover, we show the outstanding advantage of the power consumption of the NCL based asynchronous design model (a decrease of 91.12% and 93,23%) compared to the synchronous design model using clock gating technique and without using clock gating technique respectively.

Low Power Circuit and System Design Hierarchy and Thermal Reliability of Tunnel Field Effect Transistor

Tunnel FET is one of the promising devices advocated as a replacement of conventional MOSFET to be used for low power applications. Temperature is an important factor affecting the performance of circuits or system, so temperature associated reliability issues of double gate Tunnel FET and its impact on essential circuit design components have been addressed here. The temperature reliability investigation is based on double gate Tunnel FET, containing Si1-xGe x /Si, source/channel and HfO2 high-k gate dielectric material. During investigation, it has been found that at high temperature application range ~ 300 K - to - 600 K,the Tunnel FET device design parameters exhibit weak temperature dependency with switching current (ION), while the off-state current (IOFF) is slightly varying ~10−17A/μm-to-10−10A/μm. In addition, the impact of temperature on various device design element such as VTH(i.e.,switching voltage),on-current (ION), off-current (IOFF), switching ratio (ION/IOFF) and average subthreshold slope (i.e., SSavg), ambipolar current (IAMB) have been done in this research work.The essential circuit design components for digital and analog/RF applications, such as current amplification factor(gm) and its derivative (gm’),the C-V components of device design, Cgg, Cgd and Cgs, cut - off frequency (ƒT) and gain band width (GBW) product have deeply investigated. In conclusion, the obtained results show that the designed double gate Tunnel FET device configuration and its circuit design components are suitable for ultra-low power circuit,system applications and reliable for hazardous temperature environment.

Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology

Low power has arisen as a chief topic in these days and hardware enterprises. Power dissipation has become a significant thought as execution and zone of VLSI Chip plan. In this paper, a design of low power for footed quasi resistance scheme in 45nanometer VLSI technology, using appropriate standard digital gates with 45nm technology, considering footed quasi resistance technique for nanoscales is introduced. Transition of logic 1 and 0 is the main problem in the cascading circuits, this problem can solved by employing a basic inverter called as Domino logic at output.Due to the precharge propagation the power dissipation is observed in domino logic, this will be resolved using PDB (Pseudo Dynamic Buffer) model. With the help of PDB nearly 67% of power saved. Even though PDB is succeeded in precharge propagation, it fails in logic transition, this may results erroneous output during cascading. With contracting technology, power utilization can decreased and over all power of the executives on chip are the critical difficulties below 100nm because of expanded intricacy. In this paper execution of low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology. In this paper we will actualize and recreate low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology.

Compact model of nanometer STT-MTJ device with scale effect

The emergence and growing maturity of spintronics present new ideas and methods for low-power integrated circuit design. Spin-transfer torque magnetic tunnel junction (STT-MTJ) device is one of the spintronic candidates for future promising non-volatile memory. In this paper, a compact model for the STT-MTJ device in nanoscale is presented. By analyzing the influence of the device scale on its properties, the scale effect of the MTJ device is included. The thermal stability factor is trimmed to reflect the error rate of the scale effect of the device. Based on the compact model, the simulation is conducted with different device sizes to present the influence of the scale effect on the device characteristics, including the resistance, the critical current, the switching time, the write error rate, and other characteristics.

Performance Analysis for Tri-Gate Junction-Less FET by Employing Trioxide and Rectangular Core Shell (RCS) Architecture

With the advancement in technology scaling and featuring new device design is being explored to meet the demand for low power and high-speed circuit design. Tri-gate junction-less FET (TGJLFET) is taken as a reference model in this study. The structure of the reference model is modified to arrive at three different device structures; the first one with two dielectric materials for gate oxide, the second one with three dielectric materials, and the third with three dielectric materials with Rectangular Core–shell (RCS) Architecture having opposite doping at the center of the channel. The performance of these three new structures was evaluated and compared with one another and also with the reference model structure. Investigated performance parameters include leakage current, sub-threshold swing, Drain induced barrier lowering (DIBL), threshold voltage, transconductance (Gm), Output Conductance (Gd), Early Voltage (Ve), Intrinsic Gain (Av), the potential at core and surface fin of the Tri-gate device. The simulation results reveal that the device with gate trioxide with RCS Architecture shows good performance with respect to the above parameters when compared with the two new device structures and reference model. Further, an inverter is simulated using TGJLFET trioxide with RCS Architecture and its DC analysis and signal to noise margin were studied. For all the simulations 3D visual TCAD device simulator from Cogenda Pvt Ltd is used.

Design of a triple pocket multi-gate material TFET structure for low-power applications

In this paper we propose a triple-pocket multi-gate material TFET (TP-TFET) device structure for a low-power and high-performance circuit design. The proposed device structure integrates the good features of both the conventional MOSFET and tunnel FET. This is achieved through three doped pockets and dual work-function gate material on near the source–channel junction. In the proposed device, the ON state conduction mechanism is dominated by an over-the-barrier thermal diffusion of carriers, thereby offering a high-value drive current. On the other hand, the subthreshold conduction mechanism is dominated by the tunnelling of carriers, thereby incurring a very small leakage current and offering a small subthreshold slope. We use 2D TCAD device simulations for the analysis of the TP-TFET and its comparison with the existing pocketed-heterogate TFET (PHG-TFET). We observe that the proposed TFET offers the average subthreshold slope (SSavg) of 2.85 mV dec−1 and ON current of ∼230 µA µm−1 as compared to the existing PHG-TFET, which offers SSavg of 44.91 mV dec−1 and I ON = ∼62 µA µm−1. Further, some benchmark circuits are implemented using these devices. A ring oscillator designed using the TP-TFET shows approximately a 6× higher frequency as compared to that designed using the PHG-TFET. The power delay product of the NAND gate and NOR gate obtained using these devices differ by approximately 3× to 20× as the supply voltage is decreased from 1.0 to 0.5 V.

Analysis and optimal design of johnson counter

The power consumption and propagation delay in a digital system is mainly due to sequential circuits. VLSI designers were primarily focused with low power, decreased latency and area efficient sequential circuit design. In the fulfillment of these objectives, the application of optimum design technology is essential. A counter comprises of the sequential circuit, having a broad variety of applications, including PLL, Digital to Analog, Signal Generators, Signal Synthesizers, etc. In this study a 4-bit Johnson counter is proposed for low power, high speed and cost efficient. The flip flop circuit utilized 14 transistors to produce a master D flip flop operation that triggered negative edge. The proposed counter is similar to the conventional counter's performance and price. With 43.22 percent less power dissipation than conventional versions, the suggested design has been found 48.86 percent faster. In the proposed counter, the transistor requirements are also 69.5 percent reduced, giving them an optimal area design.

Low-power CMOS circuit design of audio frequency shift keying for emergency alert system

Low-power CMOS circuit design of audio frequency shift keying for emergency alert system

Low-power CMOS circuit design of audio frequency shift keying for emergency alert system

Emergency alert systems are highly essential during natural disasters like earthquake, flooding, volcanic eruption, landslides and hurricanes to make the public alert. Existing emergency alert systems use siren, text alert and broadcasting, but they are slow and may not alert at the right time in crucial situations. An Audio Frequency Shift Keying (AFSK) is designed to alert the public in emergency without hearing the text of the alert. It is designed with low power relaxation oscillator and voltage-controlled oscillator using CMOS technology. In this work, a relaxation oscillator is designed with inductor-less circuit for wideband tuning and provides huge area saving in the design. The control unit is designed to select the audio signal with two different oscillation frequencies based on input data. The public would be able to get awareness about the condition of natural disaster based on frequency of audio signal. An AFSK is designed with an operating voltage of 400 mV that consumes only 6.18 µW of power while implementing using 180 nm CMOS technology.

Low Power Circuit Design for Dynamic Comparator

Low Power Circuit Design for Dynamic Comparator

Construction of complete minimal test set for single intra-level bridging and stuck-at faults in reversible circuits

Reversible logic computing is gaining enough interest in the field of low-power circuit design technology. Moreover, the concept of reversible computing is widely used in quantum circuit computation. Therefore, it has motivated researchers to explore reversible logic as a circuit design alternative. Several problems of synthesis and optimisation of the reversible circuits have been reported in the present literature. In this context, the testing plays an important role in the effective performance of these circuits. For detecting all possible faults in the reversible circuits, numerous fault models have been proposed, where many of the proposed fault models common to conventional logic circuits. In this paper, we consider the problem of testing in the NCT or GT library-based reversible circuits with respect to an efficient test set generation for single intra-level bridging faults and single stuck-at faults. The proposed test generation method has been developed based on the concept of one-to-one mapping mechanism (reversible circuit property). Finally, experimental results show that the generated test is capable of 100% fault coverage for both the fault models and also the results are compared with the existing methods for analysing the test set size.

Effect of CNTs Parameter Variation on the Performance of Analog Device

Carbon nanotubes (CNTs) have emerged as a prominent material for present day nano-scale systems design. In spite of their widespread use in biology, and nano-electro mechanical systems (NEMS, CNTs have encroached upon conventional MOSFETs for the design of low power and high speed circuits. Because CNT possesses higher current carrying capability, higher transconductance and near ballistic transport of charge carriers. The diameter of the CNTs laid from the Source to the Drain in a CNFET has the significant influence on the characteristics of the device itself as well as on the features of circuits implemented using the said CNFET. Such variations in circuit parameters with CNT diameter can be shown to be more pronounced in analog circuits as compared to digital CNFET-based designs. The present work attempts to investigate the effect of diameter variation on a versatile analog building block (ABB) viz. the inverting current conveyor. It is demonstrated that various parameters of the ICC-II under scrutiny, like voltage bandwidth, current bandwidth, average power dissipation, etc. depend on the diameter of CNT(s) used in the CNFETs. HSPICE simulations performed on a 0.9V; 32nm CNFET-based ICC-II are included to exemplify the dependencies studied.

전자기유도 방식 에너지 하베스팅 메커니즘을 이용한 축산용 IoT 센서의 설계 및 구현에 관한 연구

To determine diseases and estrus periods, the biometric information of cows is important, which can directly affect the profits of livestock farmers. As such, real-time management incorporating IoT technology is desired. Since history information of individual objects is essential for determining diseases and estrus periods using IoT sensors, lifetime for more than 10 years and power supply of sensors are very important. Therefore, this study proposes a design technology that can extend the life of IoT sensors to more than 10 years by power supply based on the energy harvesting mechanism of the electromagnetic induction method and by low-power sensor circuit design. In this study, an electromagnetic induction method by cow"s kinetic energy is presented, and a prototype is constructed and tested to verify the applicability. Further, this study presents an algorithm for estimating the amount of internal power generation by using the acceleration data inside the sensor.

Analysis of gate-induced drain leakage in gate-all-around nanowire transistors

Gate-induced drain leakage (GIDL) is a serious problem in nanoscale transistors. In this paper, GIDL induced by longitude band-to-band tunneling (L-BTBT) in gate-all-around (GAA) nanowire transistors is investigated by 3D TCAD simulation. Effects of critical process parameters are analyzed, such as sidewall spacer characteristics, nanowire diameter, gate length and doping gradient in the source/drain extension region. The corner spacer and dual κ spacer are found to suppress L-BTBT current without degrading the dynamic performance. An underlap structure, a smaller nanowire diameter, and a gentle doping gradient at the source/drain extension are separately found as best choices, with regard to decreasing L-BTBT current. The underlying physical mechanisms are analyzed, and results indicate that increased L-BTBT width contributes to decreasing L-BTBT current. The results obtained here are reliable for optimizing the device structure, and help in low power circuit design based on nanoscale GAAFET.

Analysis and Design of a Robust, Low-Power, Inductively Coupled LSK Data Link

A low-power half-duplex data link transmits data at up to 4 Mb/s over coupled inductors across distances of up to 5 cm. The inductors are part of two resonators which tune a free-running oscillator to one of their natural modes. This gives robustness to changes in coil distance and relative orientation. With load-shift keying (LSK) employed in the remote transponder, the link is modeled analytically to reveal some unexpected properties. A complete design guide aids selection of coil size for range, carrier frequency for data rate, and $Q$ -switching to extend range. Owing to low power circuit design, the remote transponder consumes 0.075 pJ/b in transmit, 5 pJ/b in receive mode.

Construction of Complete Minimal Test Set for Single intra-level Bridging and Stuck-at Faults in Reversible Circuits

Reversible logic computing is gaining enough interest in the field of low-power circuit design technology. Moreover, the concept of reversible computing is widely used in quantum circuit computation. Therefore, it has motivated researchers to explore reversible logic as a circuit design alternative. Several problems of synthesis and optimisation of the reversible circuits have been reported in the present literature. In this context, the testing plays an important role in the effective performance of these circuits. For detecting all possible faults in the reversible circuits, numerous fault models have been proposed, where many of the proposed fault models common to conventional logic circuits. In this paper, we consider the problem of testing in the NCT or GT library-based reversible circuits with respect to an efficient test set generation for single intra-level bridging faults and single stuck-at faults. The proposed test generation method has been developed based on the concept of one-to-one mapping mechanism (reversible circuit property). Finally, experimental results show that the generated test is capable of 100% fault coverage for both the fault models and also the results are compared with the existing methods for analysing the test set size.

Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design

Low-voltage low-power (LVLP) circuit design and optimization is a hard and time-consuming task. In this study, we are interested in the application of the newly proposed meta-modelling technique to alleviate such burdens. Kriging-based surrogate models of circuits’ performances were constructed and then used within a metaheuristic-based optimization kernel in order to maximize the circuits’ sizing. The JAYA algorithm was used for this purpose. Three topologies of CMOS current conveyors (CCII) were considered to showcase the proposed approach. The achieved performances were compared to those obtained using conventional LVLP circuit sizing techniques, and we show that our approach offers interesting results.

An efficient design of reversible ternary full-adder/full-subtractor with low quantum cost

One of the major challenges of VLSI circuits is heat caused by energy loss. One of the successful solutions to this challenge is to design circuits in a reversible manner. Hence, the design of reversible circuits has attracted the attention of many researchers in the fields of low-power circuits design, DNA computing and quantum computing. Due to the benefits of ternary logic over binary logic such as reducing the complexity of interconnecting circuits, decreasing the occupied surface and reducing the number of quantum cells in quantum circuits, the ternary logic has been proposed for the design of VLSI circuits. In this paper, we first propose a new reversible ternary full-adder, called comprehensive reversible ternary full-adder, using the ternary logic capabilities. In the following, an efficient reversible ternary full-subtractor is provided. Finally, using the two proposed circuits, a new reversible ternary full-adder/full-subtractor is introduced. The results of the comparisons show that the proposed circuits have lower quantum cost and are more efficient than the other previous circuits.

Switching Enhancement via a Back-Channel Phase-Controlling Layer for p-Type Copper Oxide Thin-Film Transistors.

P-type copper oxide (CuxO) thin-film transistors (TFTs) with enhanced switching characteristics were fabricated by introducing a sputter-processed capping layer capable of controlling the back-channel phase (labeled as phase-controlling layer, PCL). By optimizing the processing conditions (the deposition power and postdeposition annealing parameters), the switching characteristics of the TFTs achieved a subthreshold swing of 0.11 V dec-1, an on/off current ratio (Ion/Ioff) of 2.81 × 108, and a field-effect mobility (μFET) of 0.75 cm2 V-1 s-1, a considerable enhancement in performance compared to that of CuxO TFTs without the PCL. Through optical/electrical analyses and technology computer-aided design simulations, we determined that the performance improvements were because of the CuxO back-channel phase reconstruction through PCL deposition and subsequent annealing. The two factors that occurred during the process, sputtering damage and heat treatment, played key roles in creating the phase reconstruction by inducing a local phase transition that sharply reduced the off-current via controlling back-channel hole conduction. As a sample application, we fabricated a complementary metal oxide semiconductor inverter based on our optimized CuxO TFT and an InGaZnO TFT that demonstrated a large inverter voltage gain of >14. The proposed approach opens up advancements in low-power circuit design by expanding the utilization range of oxide TFTs.