Design Of Low Noise Amplifier Research Articles

Applications of Body Biasing in Multistage CMOS Low-Noise Amplifiers

Low-noise amplifiers (LNAs) are one of the important building blocks of wireless receivers. LNA design parameters such as gain, noise figure, linearity, input matching, and stability are important metrics and typically affect the overall performance of the receiver. The strong trade-offs among these design parameters often necessitate several design iterations. While many of these trade-offs are due to the nature of the circuit and are inevitable, it is desirable to decouple the effects of each parameter on the others. In this work, body biasing is introduced as a technique to enhance the linearity, to improve the noise figure and to provide gain variation. These techniques are presented in the context of a three-stage LNA. By applying body biasing in each stage, noise figure, gain variation and linearity of the overall amplifier are adjusted almost independently, i.e., with minimal interrelation among these design parameters. As a proof-of-concept, a prototype 4.4-GHz LNA is designed and fabricated in a 0.13- μm CMOS technology. The LNA achieves a minimum noise figure of 3.8 dB, maximum gain of 20.2 dB, and a maximum IIP3 of -14 dBm while consuming 3.6 mW from a 1.2 V supply.

Reconfigurable dual-band low noise amplifier design and realization

A reconfigurable dual-band LNA is presented. The LNA employs switching capacitors and circuit in to realize the dual-band operation. These methodologies are used to design and implement a reconfigurable LNA for IMT-A and UWB application. The LNA is implemented using TSMC-0.13 μm CMOS technology. Measured performance shows an input matching of better than −13.5 dB, a voltage gain of 18–22.8 dB, with an NF of 4.3–4.7 dB in the band of 3.4–3.6 GHz, and an input matching of better than −9.7 dB, a voltage gain of 14.7–22.4 dB, and with an NF of 3.7–4.9 dB in the band of 4.2–4.8 GHz. According to the measure results, the proposed LNA achieves dual-band operation, and it proves the feasibility of the proposed topology.

TEMPERATURE ANALYSIS OF LNA WITH IMPROVED LINEARITY FOR RF RECEIVER

In this paper we are fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) is designing using post-linearization technique, in sub-120nm & sub-70nm technology. It developed using cascode amplifier with inductors. RC linearization circuit is designed to improve the linearity of the design. Cascode LNA circuit is designed for linearity improvement. In this work Temperature analysis is carried out for LNA circuit performance improvement fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) is designing using post-linearization technique, in sub-120nm & sub-70nm technology. Temperature stability of the circuit is analysed for different temperature ranges our results prove that the proposed LNA design achieve high gain with good linearity. Although power dissipation of the circuit is high, good temperature stability is achieved. Temperature stability of the circuit is analysed for different temperature ranges our results prove that the proposed LNA design achieve high gain with good linearity. Although power dissipation of the circuit is high, we are able to achieve good temperature stability. The Low Noise Amplifier is a special type of electronic amplifier used in communication systems which amplifies very weak signals captured by an antenna.

Intelligent GA optimizer for single supply operational amplifier and MMIC low noise amplifier

Single-Supply Operational Amplifier (Op-Amp) is important to the applications on battery-powered equipments whereas MMIC Low Noise Amplifier (LNA) is a type of integrated circuit device used in capturing operating signal in microwave frequency. This paper presents an optimization study of a Single-Supply Op-Amp and a MMIC LNA using Genetic Algorithm (GA). GA is proposed to optimize multiple input variables so as to achieve the required circuit design outputs. In Single-Supply Op-Amp, a single objective GA optimization study is conducted. Based on the single objective circuit design justification, GA is further investigated for its capability to deal with multiple design objectives in 5 GHz MMIC LNA. In this research, the Single-Supply Op-Amp design is synthesized via LTSpice whereas the MMIC LNA design is simulated through Agilent Advanced Design System (ADS). The optimization performance of GA for both single and multi-objective circuit designs is studied and the developed multi-objective GA optimizer is further compared with ADS built-in optimizers of Gradient and Quasi-Newton respectively. From the results, GA is shown to be capable in optimizing both single objective Op-Amp and multi-objective LNA.

Design 2. 4 GHz 130nm CMOS Low Noise Amplifier Design for Wireless Network

A low noise amplifier is one of the most commonly used components in analog and digital circuit designs. Low voltage, low power and low noise amplifier design has become an increasingly interesting subject as many applications switch to portable battery powered operations. An amplifier is linear electronic circuits that may used amplify an input signal and provide an output signal that is a magnified replica of the input signal. The need for design techniques to allow amplifiers to maintain an acceptable level of performance when the supply voltages are decreased is immense for maintain high gain and as low as possible noise. Popular LNA topologies are the inductive source degeneration common-source low noise amplifier. The common source low noise amplifier is commonly used for narrow-band applications due to its ease of input matching, high gain and low noise. Using this method, overall gain can be increased and the noise figure of the low noise amplifier can be decreased.. This work we presents a design of a low noise CMOS amplifier realized in a standard 130 nm CMOS technology with 1.3V supply voltage and consumes power less than 200uW with 18dB on given frequency range also have good input and output matching.

Design of Low Noise Amplifiers at 10 GHZ and 15 GHZ for Wireless Communication Systems

In this study, design and simulation of 15GHZ and 10GHZ Low Noise Amplifiers (LNA) have been explored. The simulation has been performed by using the Agilent Advanced Design System (ADS) Software. Tuning and optimization tools of ADS software have been used to optimize results. The minimum Noise Figure (NFmin) of the High Electron Mobility Transistor (HEMT) device in our simulation, is lower than previous works. We have designed a 15GHZ LNA based on three design methods basing on the lumped, the distributed and the radial stub elements. The scattering parameters of 15GHZ designed amplifier in the following manner, input return loss (S11), output return loss (S22), forward gain (S21), and isolation (S12) are -17.15dB, -16.92dB and 14.35dB as follow as -17.023 dB, respectively. Furthermore, noise figure of the 15GHZ designed amplifiers is 0.92 dB. Furthermore, the simulation results show that the scattering parameters and noise figure of 10GHZ LNA amplifiers are improved noticeably with respect to the previous works.

Constant Mismatch Circles and Application to Low-Noise Microwave Amplifier Design

Constant input and output mismatch circles in the output load plane are introduced as the basis for low-noise amplifier design methodology. Optimum tradeoff between input and output matching levels results as the application of a design chart providing, at the same time, the corresponding stage transducer gain. The role of degenerative series feedback is studied and systematically embedded in the design procedure, thus providing a direct way to evaluate its optimum level.

차세대 항공 감시시스템(ADS-BES) 지상국 수신기 저잡음 증폭기 설계 및 구현

본 논문에서는 차세대 항공 감시시스템에 대하여 소개하고, 지상국 수신기 전단부 저잡음 증폭기 설계에 관하여 연구하였다. 국제 표준 문서와 기존 제품의 성능을 고려하여 수신감도, 신뢰성 등이 경쟁력 있게 전체 시스템을 링크 버짓 하였으며, 이에 적합한 저잡음 증폭기를 얻기 위해 이득, 이득 평탄도, 반사손실 등을 최적이 되도록 설계 규격을 결정하였다. 설계시 저전력, 저잡음, 고이득 특성에 적합한 바이어스 회로를 구성하였으며, 최적 설계 후 실시한 모의실험 결과로 이득은 16.24dB, 잡음지수는 0.36dB, 입출력 반사손실은 각각 -18dB와 -28dB, 주파수 안정도는 1.11을 얻었고, 제작 후 측정 결과는 이득 17dB, 잡음지수 0.51dB, 이득 평탄도 0.23dB, 입출력 반사손실은 각각 -18.28dB, -24.50dB로 전체 시스템 구성에 적합한 결과를 얻었다. This article introduces the next-generation air surveillance system and investigates how to design of front-end low noise amplifier of the ground station receiver. In consideration of the international standard documentation and the performance of existing products, the study conducts the link budget on the entire system so that it can be competitive in terms of receive sensitivity or reliability. To obtain a proper low noise amplifier, standards of design are decided so that such factors as gain, gain flatness, and reflective loss can be optimal. In its design, the bias circuit appropriate for the characteristics of low power, low noise, or high gain was built, and according to the results of the simulation conducted after the optimal design, its gain was 16.24dB, noise factor was 0.36dB, input-output reflective loss was -18dB and -28dB each, and frequency stability was 1.11. According to the results measured after the design, its gain was 17dB, noise factor was 0.51dB, gain flatness was 0.23dB, and input-output reflective loss was -18.28dB and -24.50dB each, so the results gained were suitable for building the overall system.

Input impedance matching optimization for adaptive low-power low-noise amplifiers

Portable and implantable devices with wireless connectivity generate a high demand for low-power RF circuits. Biasing transistors in the subthreshold region allows significant reduction of power consumption, but calls for effective design techniques to minimize performance tradeoffs. This paper addresses one of the challenges associated with subthreshold RF low-noise amplifier (LNA) design: The input impedance of the ubiquitous CMOS inductor-degenerated common-source LNA operated in the subthreshold region is analyzed. By taking the increased impact of larger parasitic capacitances in the subthreshold region into account, the proposed input impedance equations provide more precise S11 prediction than the conventional approximation. In addition, a tuning method for the LNA's input impedance is presented to guarantee matching in the presence of manufacturing process variations. This tuning is implemented with a programmable capacitance to allow for digitally-assisted calibration. A 2.4 GHz LNA was designed in 0.18 μm CMOS technology and post-layout simulations were performed with device corner models across temperature and supply voltages variations. With these variations and ±15 % source/gate inductor tolerance, the simulated S11 (<?16 dB) of the tunable LNA is at least 8.5 dB better than for the identical reference design without tuning, while minimally affecting other performance parameters.

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6GHz. The resonance points were set in 3GHz and 10GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S21>10dB) with a good input impedance matching less than –10dB and a minimum noise figure of 2.9dB over the entire band. The proposed UWB LNA consumed 15.2mW from a 1.8V power supply.

Nonlinear Co-simulation of Component and System Using a New Parameter for WiMAX

Many Low Noise Amplifier (LNA) are used in the transceiver systems of Worldwide Interoperability for Microwave Access (WiMAX). Error Vector Magnitude (EVM) that is caused by a nonlinear distortion of the LNA degrades the quality of WiMAX systems. In general, the LNA design using a linear model (S-parameter) has not been focusing on the EVM, although focusing on the gain and Noise Figure (NF).A co-simulation of the components and system was carried out to evaluate the EVM of the WiMAX system using the LNA. In the co-simulation of the linear model components and systems, no saturation was observed for the EVM. This meant the co-simulation using the linear model was not effective for the design of the EVM.

Optimised LNA for wireless link in brain machine interface applications

Presentsed is an optimised design for the RF CMOS low-noise amplifier (LNA) as the analogue front-end circuit for the brain-machine interface's transceiver with an emphasis on the tradeoff between gain, noise and power consumption. A 360 nm cascode LNA operating in 404 MHz of the Medical Implant Communication Service frequency band is designed to demonstrate good performance achievable in the microwatt range. Overdrive voltage of the transistors is approximately 100 mV to exploit the high g m / I D achieving low power consumption, while avoiding performance degradation associated with the subthreshold region.

An Investigation of High Frequency Wide Band Low Noise Amplifier for Antenna Testing System

A design of wide band low noise amplifier for a typical antenna system is investigated here. This utilizes a wide frequency band from 1-6 GHz .The design objective is to achieve minimum Noise Figure at reasonable gain throughout the entire band. The transistor model used is ATF58143, An e pHEMTfamily member offering the best noise performance. After simulations a NF below 1db is achieved from 1-3.6 GHz band along with a gain above 10 dB. While below 2 dB noise figure is achieved between 3.6 -5.6GHz but at this the gain achieved is above 7dB. The input and output matching networks for the circuit are designed using micro wave transmission lines and PCB used is PTFE board.

Accurate modeling of nanoscale gate underlap SOI MOSFET and design of low noise amplifier for RF applications

Paper presents an accurate model by accounting non-quasi-static and extrinsic parasitic effects for 90 nm gate underlap SOI MOSFETs for RF applications. Generated Y-parameters from the model up to 20 GHz matched very well with 2D ATLAS (with an average error of ∼5%), whereas results from quasi-static predictive technology model differ significantly (>20%). Calculated transit frequency fT and maximum frequency of oscillation fmax have been found as ∼108 and ∼130 GHz respectively. Simulated noise figure at drain-to-source current IDS ≈ 0.64mA and drain-to-source voltage VDS=1 V was found to be ≈2.8 dB with gate resistance Rge = 3 Ω. A low noise amplifier (LNA) designed at operating frequency of 5.8 GHz using the model has shown good match at input (S11 ≈ −15 dB), output (S22 ≈ −16 dB) and gain (S21 ≈ 15 dB). A new figure-of-merit of LNA (FoMLNA) involving signal power gain G, noise factor F and dc power consumption Pdc has been proposed. By comparing with limited available measured data of 180 nm bulk, it has been found that underlap LNA (simulated using the developed model) gives almost three times improvement in the proposed FoMLNA.

65-nm CMOS Dual-Gate Device for Ka-Band Broadband Low-Noise Amplifier and High-Accuracy Quadrature Voltage-Controlled Oscillator

Design and analysis of a two-stage low-noise amplifier (LNA) and a bottom-series coupled quadrature voltage-controlled oscillator (QVCO) using a 65-nm CMOS dual-gate device are present in this paper. By using the proposed dual-gate device, the parasitic capacitance and the effective substrate resistance can be reduced. Moreover, the 3-dB cutoff frequency can be extended due to the reduction of the Miller effect. The bandwidth of the dual-gate LNA is investigated to compare with the conventional cascode configuration. Besides, the operation principle of the quadrature signal generation using the dual-gate device is also presented for the QVCO design. The two-stage dual-gate LNA demonstrates a flat 3-dB bandwidth of 7.3 GHz from 19.4 to 26.7 GHz and a maximum gain of 18.9 dB. At 24 GHz, the measured minimum noise figure is 4.7 dB, and the measured output third-order intercept point <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$({\rm OIP}_{3})$</tex></formula> is 11 dBm. The dual-gate QVCO exhibits an oscillation frequency of up to 25.3 GHz, a phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 109 dBc/Hz at 1-MHz offset frequency, an amplitude error of 0.16 dB, and a phase error of 0.8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}$</tex></formula> . The proposed dual-gate CMOS device is very suitable for the linear and nonlinear circuit designs above 20 GHz, especially for millimeter-wave applications due to its high speed and compact area.

CMOS Ultra-Wideband Low Noise Amplifier Design

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.

Low power, high gain, low noise amplifier (LNA) for ultra wide‐band applications

AbstractOne of the important components of a receiver is the low noise amplifier (LNA). The challenges of LNA design include ability to achieve high gain, low noise figure, and better linearity at low power consumption within the required frequency. In this article, our design is based on Impulse Response (IR) Ultra Wide‐Band (UWB) transceiver operating at 3.1–4.6 GHz. Hence, the LNA designed has been optimized for low noise figure, considerably high gain and better linearity at low power consumption, which make it suitable for implantable radio application. The process technology used here is 0.25 μm CMOS Silanna process. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1399–1401, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27588

A Novel Reconfigurable MB-OFDM UWB LNA Using Programmable Current Reuse

This paper presents a design of a reconfigurable low noise amplifier (LNA) for multiband orthogonal frequency division multiplexing (MB-OFDM) ultra wideband (UWB) receivers. The proposed design is divided into three stages; the first one is a common gate (CG) topology to provide the input matching over a wideband. The second stage is a programmable circuit to control the mode of operation. The third stage is a current reuse topology to improve the gain, flatness and consume lower power. The proposed LNA is designed using 0.18 μm CMOS technology. This LNA has been designed to operate in two subbands of MB-OFDM UWB, UWB mode-1 and mode-3, as a single or concurrent mode. The simulation results exhibit the power gain up to 17.35, 18, and 11 dB for mode-1, mode-3, and concurrent mode, respectively. The NF is 3.5, 3.9, and 6.5 and the input return loss is better than −12, −13.57, and −11 dB over mode-1, mode-3, and concurrent mode, respectively. This design consumes 4 mW supplied from 1.2 V.

3.1–10.6 GHz ultra-wideband LNA design using dual-resonant broadband matching technique

This paper presents an ultra-wideband low noise amplifier design using the dual-resonant broadband matching technique. The proposed LNA achieves a 10.2dB gain with ±0.9dB gain flatness over a frequency range of 3.1–10.6GHz and a −3-dB bandwidth of 2.4–11.6GHz. The measured noise figure ranges from 3.2 to 4.7dB over 3.1–10.6GHz. At 6.5GHz, the measured IIP3 and input-referred P1dB are +6dBm and −5dBm, respectively. The proposed LNA occupies an active chip area of 0.56mm2 in a TSMC 0.18μm RF-CMOS process and consumes 16mW from a 1.8V supply.

Design of Low Noise Amplifier for Radio over Fiber at 5.2 GHz

This paper presents the design and simulation of low noise amplifier (LNA) used in an active radio access point (RAP) for Radio over Fiber (RoF) technology at 5.2 GHz. RoF is integration of optical fiber for radio signal transmission within network infrastructures that is considered to be cost effective, practical and relative system configuration for long haul transport of millimeter frequency band wireless signal. The LNA designed function is to amplify extremely low signals without adding noise, thus preserving the required Signal Noise Ratio (SNR) of system at extremely low power signal. The implementation of design is based on Agilent ATF-5143 transistor and Microwave Office software is used to perform the simulation in S-parameters. The design and simulation process including selecting the transistor based on RoF requirements, stability of transistor, matching network, biasing and optimization. The design has shown an acceptable behavior with gain of 16.046 dB and noise figure of 0.9368 dB using conjugate matching method.