Design Of High-performance Devices Research Articles

3105 異方性多層膜の光学特性解析と最適設計に関する検討

Optical multilayer thin films are used by many optical dvices for appending a filter function. Design of high performance devices is expected by using anisotropic materials in the multi-layer structure. Numerical analysis considered anisotropy of films is required for obtaining the accurate optical characteristics. Formulation of numerical analysis for optical characteristics of uniaxial optical anisotropic multilayer thin films is presented. Optimization program for optimizing film thickness, refractive index and direction of director in each film is developed. Some results of optimum design are reported in this paper.

Phosphorus-doped silicon under uniaxial tensile strain investigated by PAC

At present, the use of strained silicon in the design of high performance devices has been shown to be very successful. However, even if the method has found wide application many open questions still persist. A lot of interesting aspects in conjunction with dopant atoms have not yet been fully understood or even studied. The perturbed angular correlation method (PAC) has been employed to study the local lattice distortions in the near surrounding of the probe atom 111In (Cd) due to applied stress. Our current experiments reveal that the reaction of a phosphorus doped silicon lattice to mechanical strain showed strong differences depending on the direction of stress.

Gate-dielectric permitivity and metal-gate work-function tradeoff in L/sub met/=25nm PDSOI device characteristics

Short-channel (L=25nm) silicon-on-insulator (SOI) device performances over a range of gate work function from band edge to midgap and a range of gate-dielectric permittivity from 3.9 to 15 are studied using a two-dimensional simulator that takes into account quantum-mechanical effects. A tradeoff between metal-gate work-function requirements, gate-dielectric permittivity, and device design criteria is presented. For a high-performance device design criteria, device performance benefits are also quantified as a function of gate work function and gate-dielectric permittivity. The results suggest that the maximum benefits can be obtained even when the metal-gate work function is within 110 meV (90 meV) below (above) the conduction (valence) band edge for 25-nm SOI nMOSFETs (pMOSFETs).

The power of using automatic device optimization, based on iterative device simulations, in design of high-performance devices

An automatic optimization tool for semiconductor devices based on iterative device simulations is developed. The tool is used for optimization of different kinds of semiconductor devices using various performance measures. High performance optimization algorithms, both local and global, are used to achieve an efficient design in shortest possible time. In this paper the effects of different optimization algorithms, performance measures, and number of variables in the optimization are studied. Both the computational efficiency and the devices achieved with different performance measures are studied. We give a demonstration of the usefulness of this method in a comparison between different device topologies, which have been optimized for best performance.

High Performance Device Design through Parasitic Junction Capacitance Reduction and Junction Leakage Current Suppression beyond 0.1 µm Technology

High performance 0.1 µm metal oxide semiconductor field effect transistors (MOSFETs) with 70 nm physical gate length and 1.7 nm gate oxide thickness are demonstrated. By reducing the parasitic junction capacitance and suppressing the junction leakage current (Ij,leak), high-speed/low-power transistors with a superior driving current are fabricated. Careful optimization of the channel, pocket and source/drain (S/D) doping profile results in a reduction of the N+/PW area junction capacitance (Cja) to 0.8 fF/µm2 and P+/NW Cja to 0.7 fF/µm2. In addition, area diode leakage current less than 50 nA/cm2 and perimeter diode leakage current less than 0.1 fA/µm are achieved. In this work, n-type MOS (NMOS) and p-type MOS (PMOS) drive current are 625 µA/µm and 285 µA/µm, respectively, at 1.0 V with an off-state current (Ioff) of 15 nA/µm. With the reduced parasitic capacitance and the high driving current, the unloaded ring oscillator (RO) exhibits the propagation delay time of 13 ps/stage in 1.0 V operation.