Chip Design Research Articles

Fabrication of monodisperse droplets and microcapsules using microfluidic chips: a review of methodologies and applications

Abstract Microfluidics has been applied in the preparation of monodisperse droplets and microcapsules due to its high encapsulation efficiency, its ability to create uniform particle sizes, and its capacity to control core–shell ratio and structure. To bring to the fore methodologies for the fabrication and application of monodisperse microcapsules using microfluidics, we present a review of the design, structure, materials, and surface modification techniques of various microfluidic chips. The review also covers fabrication methods, operating parameters and regulation methods of single and multiple monodisperse emulsion droplets fabricated from various microfluidic devices. Our findings show that particle size of monodisperse droplets depend mainly on microchannel characteristic size and flow rate, with particle size increasing with larger microchannel but decreasing with higher continuous phase flow rate. We additionally reviewed and compared various fabrication methods for monodisperse microcapsules, such as interfacial polymerization, free-radical polymerization, ionic cross-linking, and solvent evaporation. We further reviewed and examined the application of monodisperse microcapsules in biology applications, food engineering, composite materials development, and pharmaceutical industry. We found that high-throughput microfluidics for scale-up monodisperse microcapsule preparation towards uniform degradation and targeted release properties of monodisperse microcapsules would be key innovative direction for future applications.

Development Board Implementation and Chip Design of IEEE 1588 Clock Synchronization System Applied to Computer Networking

With the vigorous development of industrial automation and the Internet of things, the transmission of data is more dependent on immediacy, so network devices have higher and higher requirements for time synchronization accuracy. The clock source of common network devices is provided by the transistor oscillator in the server, but the oscillator will change with factors such as aging and temperature, and it cannot be guaranteed that the oscillator in the server will work at the same frequency. Time synchronization can be achieved by technologies such as IRIG-B, NTP, or IEEE 1588 (PTP), but the hardware cost of building IRIG-B is high, and NTP has the lowest cost, but it can only provide time accuracy from milliseconds to microseconds. PTP can provide sub-microsecond or even nanosecond time precision. It is a system of time synchronization mechanisms through Ethernet transmission. In this article, we first propose a time synchronization system using the development board and PDP protocol. On the Xilinx Zynq-7000 SOC platform of Petalinux, we implement the hardware solution of Linux PTP. The hardware time stamp is 20 ns. To improve the accuracy, the congenital frequency error between the oscillators must be considered. Therefore, a PTP auxiliary time stamp with dynamic frequency compensation is proposed and designed into a chip. Experimental results show that at 45 nm (TN40G) it can operate at 370 MHz and achieve 2.7 ns resolution, which can be applied to more demands.

Si Photonics FMCW LiDAR Chip with Solid-State Beam Steering by Interleaved Coaxial Optical Phased Array.

LiDAR has attracted increasing attention because of its strong anti-interference ability and high resolution. Traditional LiDAR systems rely on discrete components and face the challenges of high cost, large volume, and complex construction. Photonic integration technology can solve these problems and achieve high integration, compact dimension, and low-cost on-chip LiDAR solutions. A solid-state frequency-modulated continuous-wave LiDAR based on a silicon photonic chip is proposed and demonstrated. Two sets of optical phased array antennas are integrated on an optical chip to form a transmitter-receiver interleaved coaxial all-solid-state coherent optical system which provides high power efficiency, in principle, compared with a coaxial optical system using a 2 × 2 beam splitter. The solid-state scanning on the chip is realized by optical phased array without a mechanical structure. A 32-channel transmitter-receiver interleaved coaxial all-solid-state FMCW LiDAR chip design is demonstrated. The measured beam width is 0.4° × 0.8°, and the grating lobe suppression ratio is 6 dB. Preliminary FMCW ranging of multiple targets scanned by OPA was performed. The photonic integrated chip is fabricated on a CMOS-compatible silicon photonics platform, providing a steady path to the commercialization of low-cost on-chip solid-state FMCW LiDAR.

Design of an Automatic Resonance Frequency Tracking Chip for Power Ultrasonic Transducer With a Center Frequency Below 100 kHz

This paper presents a chip for automatic resonance frequency tracking of power ultrasonic transducer. The transducer admittance and the phase difference of voltage and current are both used for frequency tracking, which solves the disadvantages of narrow frequency tracking range, long tracking time, and easy losing frequency lock in the traditional circuit scheme. Using the transducer voltage signal as the clock, the chip can respond to the transducer signal in every cycle, then maximize the frequency tracking speed, and the total frequency tracking time is less than 10ms. A 12-bit digital-to-analog convertor (DAC) is built to control the off-chip voltage controlled oscillator (VCO), the frequency tracking accuracy can reach 0.2‰. Compared with the traditional scheme, it greatly improves the performance and saves the hardware cost.

Cerebras Architecture Deep Dive: First Look Inside the Hardware/Software Co-Design for Deep Learning

The compute and memory demands for deep learning and machine learning (ML) have increased by several orders of magnitude in just the last couple of years, and there is no end in sight. Traditional improvements in processor performance alone struggle to keep up with the exponential demand. A new chip architecture co-designed with the ML algorithms can be better equipped to satisfy this unprecedented demand and enable the ML workloads of the future. This article describes the Cerebras architecture and how it is designed specifically with this purpose, from the ground up, as a wafer-sized chip to enable emerging extreme-scale ML models. It uses fine-grained data flow compute cores to accelerate unstructured sparsity, distributed static random-access memory for full memory bandwidth to the data paths, and a specially designed on-chip and off-chip interconnect for ML training. With these techniques, the Cerebras architecture provides unique capabilities beyond traditional designs.

An Efficient Segmented Random Access Scan Architecture with Test Compression

Integrated circuit (IC) chip designs relying on Random Access Scan (RAS) architecture for post-production structural tests typically provide lower test power dissipation, test data volume, and test application time compared to the classical serial scan-based Design for Test (DFT) methodology. However, previous RAS schemes incur high signal routing and test area overheads relative to the serial scan way. Unlike serial scan schemes, previous RAS schemes have not been effectively combined with test compression to further reduce test application time and test data volume. Authors have already formally documented a locally addressed (segmented) and compressed Segmented RAS (SRAS) architecture with low area overhead and test application time. This paper describes the SRAS architecture in more detail and provides comparative experimental results. Area overhead is reduced using test access hierarchy (segmented), while adding compression to RAS lowers the test application time. Also presented is another enhancement to incorporate a scan channel multiplex block at hierarchy segments which helps drastically decrease the area and routing overhead of the original architecture to practically implementable levels on commercial circuits. The extra Segment Data Multiplexor (SDM) blocks reduce the area overhead of other components by the multiplexing factor, and the reduction in overall area is significant based on experimental data. Test data compression and auto addressing of segments are achieved by transmitting a seed address to select segments with auto-increment or auto-decrement capability followed by either single cell selection or entire leaf cell segment selection. To further reduce the area overhead and test power, this architecture is enhanced to contain multiple channels at a cost of increased overall test application time with no increase in test data volume. Results of applying the enhancements to a large circuit with one level of intermediate segments with each of them having 256 leaf segments are presented in the paper with and without multichannel multiplexing for comparison.

Directional movement of gold nanoparticles on the silicon substrate due to the Laplace pressure: A molecular dynamics simulation study

Due to superior ductility, oxidation resistance, and conductive properties, gold nanoparticles are widely used in semiconductor devices. From printing inks to electronic chips, gold nanoparticles are widely used as conductors. Nowadays, with the size of electronic chips getting smaller, gold nanoparticles have become an essential component in chip design. For example, they can connect resistors, conductors, and other electronic chip components. However, interactions of gold nanoparticles with curved substrates at high temperatures have rarely been studied. In our study, we simulated interactions of gold nanoparticles at high temperatures on a curved silicon substrate. It is observed that at above the metlting point, gold nanoparticles moved directionally under the effect of curvature gradients, and the curved surface can be used to control the coalescence of gold nanoparticles. The size, temperature of gold nanoparticles, and curvature gradients of the substrate are altered to observe their effects on gold nanoparticle movement. According to the results, we conclude that surface curvature gradients induce the Laplace pressure, and the Laplace pressure drives liquid gold nanoparticles to move directionally.

Design and Implementation of an Automatic Test and Verification System for SoC

With the development of semiconductor technology in recent years, the design of SoC has become more and more complex. [1]In order to ensure the correctness of chip design and the success rate of chip taping out, the verification test of SoC becomes more and more important. This paper designs an automated test and verification system based on STM32 and analog switch matrix chips. The system has high reusability, good scalability, convenient maintenance and automated test, and can improve the efficiency of test and verification, reduce the cost and shorten the development cycle of SoC.

On Securing Cryptographic ICs against Scan-based Attacks: A Hamming Weight Distribution Perspective

Scan chain-based Design for Testability is the industry standard in use for testing manufacturing defects in the semiconductor industry to ensure the structural and functional correctness of chips. Fault coverage is significantly enhanced due to the higher observability and controllability of the internal latches. These ensuing benefits to testing, if misused, expose vulnerabilities that can be detrimental to the security aspects, especially in the context of crypto-chips that contain a secret key. Hence, it remains of paramount importance for a chip designer to secure crypto-chips against various scan attacks. A countermeasure is proposed in this article that preserves the secrecy of an embedded key in a cryptographic integrated circuit running an Advanced Encryption Standard (AES) implementation. A novel design involving a hardware unit is illustrated that circumvents differential scan attacks by essentially performing bit flips deterministically, using a pre-computed mask value. This helps secure the chip while retaining full testability. The controller logic directly depends on a mask determination algorithm that can defend against any scan attack with 𝒪 theoretical complexity. Security analysis of our proposed defense procedure is performed in the framework of Discrete Event Systems (DES). The sequential scan circuit of an AES cryptosystem is modeled as a DES using Finite State Automata. A security notion, Opacity , is used to quantify and formally verify the security aspects of our controlled system, which shows that the entropy of the secret key is preserved. A case study is performed that shows to mitigate state-of-the-art differential scan attacks successfully at a nominal extra overhead of 1.78%.

Efficient Test Chip Design via Smart Computation

Submitted to the Special Issue on Machine Learning for CAD (ML-CAD). Competitive strength in semiconductor field depends on yield. The challenges associated with designing and manufacturing of leading-edge integrated circuits (ICs) have increased that reduce yield. Test chips, especially full-flow logic test chips, are increasingly employed to investigate the complex interaction between layout features and the process that improves the total process quality before and during initial mass production. However, designing a high-quality full-flow logic test chip can be time-consuming due to the huge design space and complex process to search for optimal result. This work describes a new design flow that significantly accelerates the logic test chip design process. First, we deploy random forest classification technique to predict potential synthesis outcome for test chip design exploration. Next, a new method is described to efficiently solve the integer programming problem involved in the design process. Various experiments with industrial design have demonstrated that the proposed two methods greatly improve the design efficiency.

Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators

The emerging non-volatile memory (eNVM) based mixed-signal Compute-in-Memory (CIM) accelerators are of great interest in today's AI accelerators design due to their high energy efficiency. Various CIM architectures and circuit-level designs have been proposed, showing superior hardware performance for deep neural network (DNN) acceleration. However, hardware-aware quantization strategies for CIM-based accelerators are not systematically explored. Since there are a variety of design options for neural network mapping on CIM systems while improper strategies may narrow the circuit-level design space and further limit the hardware performance, it is important to make a comprehensive early-stage design space exploration and find appropriate quantization/mapping strategies to achieve better hardware performance. In this paper, we provide a joint algorithm-hardware analysis and compare the system-level hardware performance for various design options, including quantization algorithms, data representation methods and analog-to-digital converter (ADC) configurations. This work aims to propose guidelines for choosing more hardware-friendly design options for chip architects. According to our evaluation results for CIFAR-10/100 and ImageNet classification, the properly chosen quantization approach and optimal mapping strategy (dynamic fixed-point quantization + 2’s complement representation/shifted unsigned INT representation + optimized precision ADC) could achieve ∼2 × energy efficiency and 1.2 ∼ 1.6 × throughput with 5%∼25% reduced area overhead, compared to naïve strategy (fixed-point quantization + differential pair number representation + full precision ADC).

Parity Quantum Optimization: Compiler

We introduce parity quantum optimization with the aim of solving optimization problems consisting of arbitrary k-body interactions and side conditions using planar quantum chip architectures. The method introduces a decomposition of the problem graph with arbitrary k-body terms using generalized closed cycles of a hypergraph. Side conditions of the optimization problem in form of hard constraints can be included as open cycles containing the terms involved in the side conditions. The generalized parity mapping thus circumvents the need to translate optimization problems to a quadratic unconstrained binary optimization problem (QUBO) and allows for the direct encoding of higher-order constrained binary optimization problems (HCBO) on a square lattice and full parallelizability of gates.

Ready-to-use interactive dual-readout differential lateral flow biosensor for two genotypes of human papillomavirus

Ready-to-use in vitro diagnosis of multiple genotypes is vital for the prevention and treatment of cervical cancer. Herein, a paper-film-based interactive dual readout differential lateral flow biosensor is proposed to simultaneously assay two high-risk types of human papillomavirus (HPV) within the body-fluid. The CuCo2S4/ZnIn2S4 heterostructure is fabricated on the paper-film compound chip with high thermostability, and surface sulfur vacancy is introduced by mild annealing treatment to endow unexceptionable photoexcitation activity, such structure can be served as an initial energy harvester and converter. With the assistance of differential channels, the dual-target-propelled self-assembly of annular DNA and the cleavage activity of CRISPR-Cas12a are stepwise activated by sequential solution transfer. Accordingly, the input and release of polydopamine-coated gold nanoparticles with photothermal/photoelectric characteristic were implemented. The fabricated biosensor not only realized intelligent thermal-response without large instruments, but also actuated dynamic interfacial charge separation and transfer kinetics to further transmit photoelectric-signal, resulting in desirable interactive dual-signal with low limit-of-detection (0.21 pM for HPV-18 and 42.92 pM for HPV-16). Thanks to the sophisticated design of differential lateral flow paper-film compound chip and interactive dual-signal amplification strategy, sensitive detection of two HPV genotypes is realized, which provides a promising candidate for home medical intelligent diagnosis.

A Comprehensive Strategy Combining Feature Selection and Local Optimization Algorithm to Optimize the Design of Low-Density Chip for Genomic Selection

Design of low-density SNP chips provides an opportunity for wide application of genomic selection at lower cost. A novel strategy referred to as the “block-free” method is proposed in this study to select a subset of SNPs from a high-density chip to form a low-density panel. In this method, Feature Selection using a Feature Similarity (FSFS) algorithm was first performed to remove highly correlated SNPs, and then a Multiple-Objective, Local-Optimization (MOLO) algorithm was used to pick SNPs for the low-density panel. Two other commonly used methods called the “uniform” method and the “block-based” method were also implemented for comparison purposes. A real pig dataset with 7967 individuals from three breeds containing 43,832 SNPs was used for comparison of the methods. In terms of genotype imputation accuracy and genomic prediction accuracy, our strategy was superior in most cases when the densities were lower than 1K. The genotype imputation accuracy from the low-density chip compared to the original high-density chip was higher than 90% in all pig breeds as the density increased to 1K. In addition, the accuracies of predicted genomic breeding values (GEBV) calculated using the imputed panel were nearly 90% of estimates from the original chip for all traits and breeds. Our strategy is effective to design low-density chips by making full use of information of close relationships for genomic selection in animals and plants.

Experimental Investigation of Microfluidic Device for Platelet Activation.

Wound healing is accelerated when Platelet Rich Plasma is activated and growth factors are released. In this study, it was aimed to stimulate platelets without using chemical stimulants. Two types of mechanical platelet activation methods have been proposed in this study. The first one is a microfluidic chip developed with the shear-induced platelet activation approach. The second one is a piezo-based ultrasound-assisted device which provides platelet activation by stimulating with an ultrasonic wave (0.55 and 1.1 MHz). Three different microfluidic chip designs were worked out to determine the optimal shear stress characteristics; 8-nodes (2789 µs, 288 shear pulses, and 98.3 dyne/cm2), 40-nodes (2765 µs, 1440 shear pulses, and 95.5 dyne/cm2) and pillar-shaped (1030 µs, 1656 shear pulses, and 48.1 dyne/cm2). The highest platelet activation rate (72.7%) was obtained from the chips with 8-nodes. In the ultrasound-assisted device, 32.4% activation rate was obtained from ultrasound waves with 0.55 MHz frequency and 10 Vp-p amplitude. These activation rates, determined by CD62P (P-Selectin) expression, are significantly higher than spontaneous activation of intact platelets (8.5%). In addition, the gradual increase in activation of stimulated platelets with incubation at room temperature showed that activation continued after stimulation. The results showed that these microfluidic devices can be used for platelet activation to enhance the effect of PRP treatment and might reduce adverse immune reactions that may happened due to the use of exogenous activator substances. Fast-response, low-cost, easy-to-use and controllable biomedical device have been developed for PRP applications.

An eFPGA Generation Suite with Customizable Architecture and IDE

From edge devices to cloud servers, providing optimized hardware acceleration for specific applications has become a key approach to improve the efficiency of computer systems. Traditionally, many systems employ commercial field-programmable gate arrays (FPGAs) to implement dedicated hardware accelerator as the CPU's co-processor. However, commercial FPGAs are designed in generic architectures and are provided in the form of discrete chips, which makes it difficult to meet increasingly diversified market needs, such as balancing reconfigurable hardware resources for a specific application, or to be integrated into a customer's system-on-a-chip (SoC) in the form of embedded FPGA (eFPGA). In this paper, we propose an eFPGA generation suite with customizable architecture and integrated development environment (IDE), which covers the entire eFPGA design generation, testing, and utilization stages. For the eFPGA design generation, our intellectual property (IP) generation flow can explore the optimal logic cell, routing, and array structures for given target applications. For the testability, we employ a previously proposed shipping test method that is 100% accurate at detecting all stuck-at faults in the entire FPGA-IP. In addition, we propose a user-friendly and customizable Web-based IDE framework for the generated eFPGA based on the NODE-RED development framework. In the case study, we show an eFPGA architecture exploration example for a differential privacy encryption application using the proposed suite. Then we show the implementation and evaluation of the eFPGA prototype with a 55nm test element group chip design.

THE STRATEGIC ROLE OF SEMICONDUCTOR INDUSTRY

ABSTRACT The semiconductor industry that produces microchips plays an increasingly important role in today’s world economy. This industry is characterized by cutting-edge technological complexity and prohibitively high costs; both factors lead to the concentration of microchip production in a few major companies in a few countries. The combination of these factors and recent disruptions caused by the pandemic and trade wars underlined the strategic role of semiconductor production. The paper reviews the basics of microchip fabrication, the types of companies in the semiconductor business, the market share of main companies, and the main countries in chip production. The authors emphasize the role of microchips in defense industries and the necessity for national sovereignty in this area. Special attention is paid to the current technological race for supremacy in the semiconductor industry and to numerous national programs to help national companies in bringing inshore chip design and manufacturing expertise. Keywords semiconductor industry, microchips, chip fabrication, chip shortage, strategic technology

Locality-based electromagnetic leakage assessment using CNN

Deep learning side-channel analysis (SCA) attacks have recently gained in popularity. The ability of deep learning models to retrieve a key byte while minimizing the need for pre-processing steps in both cases of misaligned traces and when the leakage model is multivariate has contributed to the popularity gain. Near-field electromagnetic (EM) probes have enabled leakage capture with high spatial resolution, and the field of deep learning side-channel research looks to find models which reduce the required number of leakage traces to retrieve a key byte successfully. However, despite the many papers researching techniques to reduce the number of traces required for a successful attack, location-based research for EM SCA remains untouched. Due to the nature of EM probes and the architecture of different boards and chips, the location of the collection probe becomes important when attempting to extract the secret key within a reasonable timeframe and with a level of certainty in the result. Our contribution is a framework to determine the best location to assess localized EM leakage against a given chip platform. We use a raster scan to collect localized leakage results at 25 points in a 5x5 grid pattern on a ChipWhisperer Lite XMEGA board running an open-source implementation of the AES-128 encryption algorithm. We demonstrate the use of our framework to locate the best points for an attacker to execute a profiling attack by identifying the grid point with the most detectable leakage for a chip platform. We further execute a smaller localized 25-point raster scan in a grid over the identified location to further refine our estimate of the optimal collection location. We then demonstrate that this location can be used to execute a side-channel profiling attack against the same chip architecture and will result in a lower number of traces required to retrieve the key byte.

Ultra-High-Throughput Absorbance-Activated Droplet Sorting for Enzyme Screening at Kilohertz Frequencies.

Droplet microfluidics is a valuable method to "beat the odds" in high throughput screening campaigns such as directed evolution, where valuable hits are infrequent and large library sizes are required. Absorbance-based sorting expands the range of enzyme families that can be subjected to droplet screening by expanding possible assays beyond fluorescence detection. However, absorbance-activated droplet sorting (AADS) is currently ∼10-fold slower than typical fluorescence-activated droplet sorting (FADS), meaning that, in comparison, a larger portion of sequence space is inaccessible due to throughput constraints. Here we improve AADS to reach kHz sorting speeds in an order of magnitude increase over previous designs, with close-to-ideal sorting accuracy. This is achieved by a combination of (i) the use of refractive index matching oil that improves signal quality by removal of side scattering (increasing the sensitivity of absorbance measurements); (ii) a sorting algorithm capable of sorting at this increased frequency with an Arduino Due; and (iii) a chip design that transmits product detection better into sorting decisions without false positives, namely a single-layered inlet to space droplets further apart and injections of "bias oil" providing a fluidic barrier preventing droplets from entering the incorrect sorting channel. The updated ultra-high-throughput absorbance-activated droplet sorter increases the effective sensitivity of absorbance measurements through better signal quality at a speed that matches the more established fluorescence-activated sorting devices.

Simplified quantitative analysis method and its application in the in-situ synthesized copper-based azide chips

Copper-based azide (Cu(N3)2 or CuN3, CA) chips synthesized by in-situ azide reaction and utilized in miniaturized explosive systems has become a hot research topic in recent years. However, the advantages of in-situ synthesis method, including small size and low dosage, bring about difficulties in quantitative analysis and differences in ignition capabilities of CA chips. The aim of present work is to develop a simplified quantitative analysis method for accurate and safe analysis of components in CA chips to evaluate and investigate the corresponding ignition ability. In this work, Cu(N3)2 and CuN3 components in CA chips were separated through dissolution and distillation by utilizing the difference in solubility and corresponding content was obtained by measuring N3− concentration through spectrophotometry. The spectrophotometry method was optimized by studying influencing factors and the recovery rate of different separation methods was studied, ensuring the accuracy and reproducibility of test results. The optimized method is linear in range from 1.0–25.0 mg/L, with a correlation coefficient R2 = 0.9998, which meets the requirements of CA chips with a milligram-level content test. Compared with the existing ICP method, component analysis results of CA chips obtained by spectrophotometry are closer to real component content in samples and have satisfactory accuracy. Moreover, as its application in miniaturized explosive systems, the ignition ability of CA chips with different component contents for direct ink writing CL-20 and the corresponding mechanism was studied. This study provided a basis and idea for the design and performance evaluation of CA chips in miniaturized explosive systems.