Analog System Design Research Articles

On the Structure of a Quasi-Optimal Algorithm for Circuit Designing

The formulation of the process of analog system design has been done on the basis of the control theory application as the problem of a special functional minimization. This approach generalizes the design process and produces the different design trajectories inside the same optimization procedure. Numerical examples show that the potential computer time gain of the optimal design strategy with respect to the traditional design strategy increases when the size and the complexity of the system increase. Some properties of an additional acceleration effect of the design process were analyzed. The special selection of the optimization process start point provides the acceleration effect with a great probability. The positions of the optimal switch points of the control vector were found on the basis of the analysis of the special Lyapunov function of the design process. The combination of the acceleration effect with the start point preliminary selection and the optimal switch points of the control vector serve as the principal ideas to the time-optimal design algorithm construction.

Selection of Design Solutions at the Optimization Stage under Conditions of Uncertainty on the Basis of a Functional-Parametric Approach

The paper considers the problem of circuit design of analog technical devices and systems taking into account random processes of changing their parameters and requirements of reliability. The difficulties that arise when using a functional-parametric approach with a problem area in the form of optimal parametric synthesis in conditions of a shortage of initial information are analyzed. The possibility of reducing the computational complexity through the use of preliminary analysis of the source data, parallel and distributed computing technology is evaluated. The evolutionary synthesis algorithm under the existing conditions is described, some ways to overcome the difficulties that arise at the optimization stage are proposed. The possibility of using evolutionary computations with the probabilistic nature of the optimality criterion, the nonlinearity of the objective function and the restrictions on it is estimated.

New Frontiers in Smart Sensors Based on Printed Organic Electronics

Organic printed electronics is an attractive platform to develop mechanically flexible and cost-effective solutions for innovative applications such as foldable displays, flexible sensing surfaces, or biomedical instrumentation that can adapt to the shape of the body. Despite the growing interest and the recent advancements of printed electronic technologies, their use in commercial products remains very limited till now. Processing challenges such as limited yield, large transistor variability, and poor electrical performance still prevent printed systems-on-foil from commercial exploitation. The approach proposed in this work aims to tackle several of these limitations at different levels of abstraction, starting from the fabrication process and reaching the system-on-foil design. From the processing side, the major mechanisms leading to defects in a gravure-printed unipolar Organic Thin-Film-Transistor (OTFT) technology have been identified, and a successful approach to improve both device yield and performance has been developed. The availability of a reliable transistor technology is indeed a key requirement to enable complex systems-on-foil with high-yield. Assisted design flows and reliable Process Design Kits (PDKs) are also a fundamental asset to simulate and predict the system performance, further improving yield and significantly reducing design time. For these reasons a complete PDK specifically suited for gravure printed technologies has been developed. Furthermore, a methodology for the design and transistor-level implementation of analog and mixed-signal systems has been proposed: it aims at minimizing the transistor count, thus maximizing the overall yield. Circuit techniques which make use of ratiometric radouts and passive feedback networks have been used to reduce the sensitivity to the parameter variability and decrease the risks of soft failures in circuits. This multidisciplinary approach allowed us to design and successfully fabricate state-of-the-art printed smart sensors. Flexible solutions for large-area proximity and pressure sensing applications have been demonstrated, using lamination of a foil containing sensing functionality to a foil carrying analog fronted readout electronics. Both fully organic and hybrid organic-Si CMOS electronic approaches have been exploited for the readout and signal conditioning of this class of sensors. Finally, an ultra-low cost printed smart temperature sensor on an RFID tag suitable for cold chain temperature monitoring applications has also been designed and built. These results demonstrate that printed electronics can be successfully used today to fabricate inexpensive smart sensing devices for a large number of applications in which sensing over a large area, mechanical flexibility and cost are important requirements.

ПРОБЛЕМЫ СХЕМОТЕХНИЧЕСКОГО ПРОЕКТИРОВАНИЯ АНАЛОГОВЫХ УСТРОЙСТВ НА ОСНОВЕ ФУНКЦИОНАЛЬНО-ПАРАМЕТРИЧЕСКОГО ПОДХОДА

The paper focuses on the problem of circuit design of analog technical devices and systems with due account of random processes of changing their parameters and reliability requirements. A functional-parametric approach is used, based on the computer modeling of the systems functioning and changes in their parameters; methods of optimal parametric synthesis under reliability criteria are used to solve it. The paper also discusses the problems caused by the lack of information about the patterns of ran-dom processes of parameter changes, the absence or lack information about disturbing influences, the effect of external factors on the processes within them. The possibility of applying search optimization algorithms that allow parallelization of computational processes, as well as the possibility of using evolutionary calculations with the probabilistic nature of the optimality criterion, the nonlinearity of the objective function and its restrictions are analyzed.

A class of unexcited hyperjerk systems with megastability and its analog and microcontroller-based embedded system design

Discovering chaotic systems with special features is of interest in the recent years. In this paper we introduce a new class of simple hyperjerk systems with infinitely coexisting chaotic attractors usually termed as megastability. The novelty of the proposed systems is that the systems shows megastability without external excitation which was not the case in most of the existing megastable attractors discussed in the literatures. Various dynamical properties of one of the proposed systems like the stability of equilibrium points, bifurcation and Lyapunov spectrum are discussed. Also, a circuit realization using off-the-shelf components is shown to prove the implementation feasibility of the systems. In addition, microcontroller based embedded design with graphic LCD of obtained new simple hyperjerk megastable oscillators was realized. Thus, the obtained new oscillators can be used both in a variety of real digital applications such as random number generators, encryption, communication and for educational purposes.

A multi-dimensional matrix keyboard interfacing circuit design

PurposeThis paper presents a novel design method for keyboard circuits. The purpose of this study is to enable a single-board computer with fewer pins to recognize a keyboard system consisting of a large number of switches. Through the study of different kinds of keyboard circuits, a general circuit schematic design method is abstracted. Several experiments are conducted to prove the feasibility of the proposed circuit design method.Design/methodology/approachConventional circuit schematic diagrams are often limited to two-dimensional planes. Through investigating higher dimensional alternatives, this paper proposes to place components in high-dimensional geometry before connecting all components. A multi-pin switch construction method is proposed to allow the switches to be arranged on the vertices of high-dimensional geometry and be connected sequentially to form the keyboard system. This proposed system can allow a keyboard system consisting of a large number of switches to be recognized by a single-board computer with less available pins.FindingsThe design scheme proposed in this paper can read more switch states with limited Input/Output pins. With the increase of the number of Input/Output ports and pins, the number of simultaneously identifiable switches increases exponentially, which is suitable for sensor design of array type.Research limitations/implicationsCompared with the classical keyboard circuits, the circuit designed using the proposed method will lead to a slightly longer recognition time for each key. This can be compensated by a single-board computer with a modestly higher clock speed.Originality/valueThe circuit schematic design method based on high-dimensional geometry is introduced for the first time. The feasibility of the proposed method is verified by the original experiments. The proposed approach is of importance in guiding the design of new analog and digital sensor circuit systems.

Design Of Low Power Two Stage Op-Amp Using Sub-20 nm CMOS Technology

An Operational amplifier is one of the most versatile and fundamental building block in almost every analog and mixed signal processing circuits.The design of analog and mixed signal system is always a challenging task. Nowadays researches are being carried out in the field of scaling down the CMOS devices so that their area and power consumption can be reduced. This paper presents the design of a two stage Op-Amp using sub20 nm CMOS technology. This design has a differential amplifier stage and an additional gain stage, implemented with minimum number of transistors, so that the area and power consumption is optimized. Design and simulation was done using cadence EDA software tool. The designed Op-Amp is operating with a supply voltage of 800 mV and a bias current of 10µA.The design attains an open loop gain of 88.74dB with unity gain bandwidth of 50.7 MHz and a phase margin of 57.98 degree with load capacitor of 1 pF. The average power consumption of the amplifier is found to be 533µW and the slew rate is 20V/µs.

Design of Mixed-Signal Systems With Asynchronous Control

This paper presents a novel workflow for the design of mixed-signal systems with asynchronous control. Current methods rely on synchronous control logic and full-system simulation, which might lead to suboptimal results and even project respins due to critical errors. Asynchronous circuits can provide greater robustness, reactivity, and power efficiency. The proposed workflow aims to combine state-of-the-art tools for asynchronous circuit design and formal verification of analog systems in a unified environment. The effectiveness of this methodology is demonstrated by the analysis of a buck converter.

Study and Design of 40 nW CMOS Temperature Sensor for Space Applications

In this paper, a novel CMOS temperature sensors based on sub-threshold MOS operation has been presented, which is designed for space and satellite applications. This proposed CMOS temperature sensor is enunciated good linearity between temperatures range from -55 O C to 150 O C with inaccuracy of 0.85 O C/V. This circuit is operated at supply 1V and static power consumption 40nW is achieved. The proposed circuit is based on the MOS threshold voltage and mobility. There are two type of sensor output in presented circuit first, voltage proportional to absolute temperature (PTAT) due to threshold voltage and second, negative temperature coefficient (NTC) due to mobility. This circuit is designed & simulated using Cadence analog & digital system design tools UMC90nm CMOS technology. The layout area of the circuit is 17.213μm 6.655μm. This is a low power and longer battery life for harsh environment, wireless sensor network applications etc.

Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation

The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-silicon bugs, minimizing design risk and cost. The unique features of the approach include: 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; and 3) compensation of ac performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45 nm node that can map AMS modules across 22-90 nm technology nodes. A systematic emulation approach to map any analog transistor to 45 nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22 and 90 nm nodes with less than a 5% error. Several other 90 and 22 nm analog blocks are successfully emulated by the 45 nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H).

A design-oriented methodology for accurate modeling of on-chip interconnects

An accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology.

Design and Assessment of a High Gamma-Dose Tolerant VCSEL Driver With Discrete SiGe HBTs

A digital VCSEL driver has been designed, simulated and assessed under radiation, using discrete SiGe HBT's. The circuit tolerates high levels of gamma radiation, up to 12 MGy, features less than 2% drift in the forward current of the VCSEL and operates well above 10 MHz. The output duty cycle shows no notable degradation at 200 kHz, enabling the design of robust analog and digital communication systems using pulse-width-modulation (PWM) schemes.

Hierarchical constraint transformation based on genetic optimization for analog system synthesis

In a top–down analog system design methodology, the task of translating high-level performance specifications and constraints into component level parameters is termed as constraint transformation. In this paper, we presented a genetic optimization based approach to constraint transformation. The salient features of this are a search space profiling technique and a hierarchical two-level genetic optimization engine. Performance estimation for profiling and hierarchical optimization uses both the performance equations embedded in an analog performance estimation module as well as detailed SPICE simulation. We described the constraint transformation method, and each of its constituents. The effectiveness of the two-level hierarchical approach was established by comparing it against a flat non-hierarchical method. Application of the constraint transformation method in the synthesis of design examples was also presented in the paper.

On time-optimal procedure for analog system design

The process of any analog system design has been formulated on the basis of the control theory application. This approach produces many different design strategies inside the same optimization procedure and allows determining the problem of the optimal design strategy existence from the computer time point of view. Different kinds of system design strategies have been evaluated from the operations number. The general methodology for the analog system design was formulated by means of the optimum control theory. The main equations for this design methodology were elaborated. These equations include the special control functions that are introduced artificially. This approach generalizes the design process and generates an infinite number of the different design strategies. The problem of the optimum design algorithm construction is defined as the minimum-time problem of the control theory. Numerical results of some electronic circuit design demonstrate the efficiency and perspective of the proposed methodology. These examples show that the computer time gain of the optimal design strategy with respect to the traditional design strategy increases when the size and complexity of the system increase. An additional acceleration effect of the design process has been discovered by the analysis of various design strategies with the different initial points. This effect is displayed for all analyzed circuits and it reduces additionally the total computer time for the system design.

Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS

High-level synthesis is highly demanded for managing the complexity of analog and mixed-signal system designs. However, synthesis methods are currently in their infancy. The absence of a high-level specification notation is an important limitation for the development of efficient synthesis methods. This paper presents a behavioral model and a VHDL-AMS subset for high-level synthesis of analog and mixed-signal systems. The model (named aBlox) offers a composition semantics for functionality description and an orthogonal declarative mechanism for expressing the performance requirements of a system. The model was developed after analyzing a large number of systems for telecommunication, signal processing, control engineering, and analog computing. The model expresses the meaning of: 1) analog and digital data; 2) continuous and event-driven functionality (behavior); 3) analog performance attributes; and 4) analog-digital interactions. The aBlox model serves as a foundation for defining a semantically sound VHDL-AMS subset for synthesis. Also, the VHDL-AMS subset is identified so that its constructs can be mapped to architectures of circuits. We introduce several restrictions to the VHDL-AMS instructions, such that their semantics match that of the aBlox model. To motivate the usefulness of the model and the VHDL-AMS subset, we present a case study that uses VHDL-AMS inputs.

Characterizing substrate coupling in deep-submicron designs

The accurate modeling of noise-coupling effects caused by crosstalk through the substrate is an increasingly important concern for design and verification of analog, digital, and mixed systems. With the technique described here, designers can efficiently extract accurate substrate-coupling parameters from deep-submicron designs.

A Current-Mode Logic for Low-Voltage, High-Speed Mixed-Mode VLSI Circuits

A wired-AND current-mode logic (WCML) circuit is designed for high performance mixed analog and digital system designs on a common silicon substrate, using standard CMOS process. Current is used for digital information carrier in order to be able to reduce supply voltage, power consumption, digital switching noise and to increase operating frequency. The WCML circuit uses current-steering technique. It is composed of a simple current mirror with a current injector. Wired-AND connections cause the logic circuit to operate as a NAND logic gate which provides to implement any boolean function. High-speed is achieved by varying the injection current level even at low-voltage supply (<1.5 V) with low-power consumption.

Behavioral simulation for analog system design verification

Synthesis of analog circuits is an emergent field, with efforts focused at the cell level. With the growing trend of mixed ASIC designs that contain significant portions of analog sections, compatible design methodologies in the analog domain are necessary to complement those in the digital domain. The synthesis process requires an associated verification process to ensure that the designs meet performance specifications at the onset. In this paper we present a behavioral simulation methodology for analog system design verification and design space exploration. The verification task integrates with analog system-level synthesis for an integrated synthesis-verification process that avoids expensive post synthesis simulation by invoking external simulators. Thus rapid redesign at the architectural level can be undertaken for design parameter variation and during optimization. The verification suite is composed of a repertoire of analysis modes that include time and frequency domain analysis, sensitivity analysis and distortion analysis. Besides verification of design specifications, these analysis modes are also used to generate metrics for comparison of various architectural choices that could realize a given set of specifications. The implementation is in the form of a behavioral simulator, ARCHSIM. >

ARCHGEN: Automated synthesis of analog systems

High-level design of analog systems is an open area that needs to be addressed with the emerging trend of integrating mixed analog-digital systems. Design methods compatible across the analog-digital boundaries would expedite the design process, and in this paper we address analog high-level design issues. An approach for systems-level synthesis of a class of analog systems is presented. A behavioral level for the analog domain is characterized in terms of state equations and transfer functions in the continuous and discrete domains. State-space representations are generated from transfer function specifications that exhibit system level characteristics such as controllability and observability as, well as decoupled and parallel architectures. These state-space representations are synthesized into behavioral-level, technology-independent architectures composed of analog functional components. An intermediate architecture in a circuit implementation technology is synthesized from the behavioral architecture. The various algorithmic procedures for synthesis are implemented in the program ARCHGEN. Behavioral simulation is used for architecture verification and design space exploration.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Computer-Aided Engineering Technology for the Design of Electronic Systems

The integration of system and architecture of the design process is key to reducing design cycle time and cost in developing complex hardware and software systems. In this paper, we present an Integrated Engineering Environment. It is a design, analysis, verification, and management environment for the system and architectural levels of complex systems, a system synthesis framework. Discussion is included about Computer-Aided Engineering software simulation tools which offer the opportunity to gain confidence in the performance of sophisticated digital, analog, and hybrid electronic system designs before making a commitment to hardware. This approach should be considered in today's environment, where it is important to find innovative ways to control development and operational costs. With the concern for the loss of our defense industrial base, and when the original design team may no longer be available, using this technique makes it possible to re-engineer existing designs, converting them to current technology.