Amplifier Design Research Articles

CMOS operational amplifier design for industrial and biopotential applications: Comprehensive review and circuit implementation

This paper provides a detailed exploration of CMOS operational amplifiers (Op-Amps) aimed at enhancing understanding of their development, design, and application. To achieve this, a comprehensive examination of the common characteristics, parameters, and bibliographic reviews of Op-Amps, distinguishing among various chosen operational amplifiers. A comprehensive bibliographic review of the operational amplifier's keywords between 2008 and 2018 has also been conducted. A bibliometric analysis of 4997 documents from the Web of Science (WOS) Collection is conducted using VOSviewer software. Furthermore, an analysis and comparison of these Op-Amps across functional aspects relevant to industrial and biomedical applications, emphasising the salient characteristics of each technique. After the survey, a novel Op-Amp design is proposed, incorporating a differential amplifier at the first stage, along with a compensating capacitor and a high gain stage. The biasing circuitry is replaced with an active load resistor (MOS transistor), simplifying layout design, and reducing the amplifier's area and power consumption compared to traditional two-stage designs. The power source for this design is 3.3 V. This designed operational amplifier achieved a gain of 62.9449 dB, a high CMRR of 92.8079 dB, and a unity gain bandwidth of 33 MHz, and the optimised layout area is 0.001476 μm2. The proposed circuit was designed and simulated utilising the Cadence Virtuoso 180 nm CMOS process. The simulation results show that the desired criteria have been met. Additionally, the challenges and future possibilities in analog circuits, laying the groundwork for research in both analogue and digital circuits to tackle complex real-world issues have been addressed.

Design of a broadband high-efficiency power amplifier based on ring-resonant filter with compensation architecture and a series of continuous modes

Design of a broadband high-efficiency power amplifier based on ring-resonant filter with compensation architecture and a series of continuous modes

A Low Frequency Power Amplifier Design Based on Output CapacitorLess Circuit

This low-frequency power amplifier utilizes the AT89S51 microcontroller as the main control chip. The system can be divided into several modules: power amplification circuit module, pre-amplification module, band-stop filtering module, protection circuit module, volume control module, power supply voltage, AC voltage, and AC current testing module, A/D conversion module, power module, and single-chip microcomputer subsystem control module. We chose class AB audio power amplifiers. To ensure circuit stability and higher fidelity, we selected the TDA2030 integrated chip to build the OCL power amplifier circuit, preventing efficiency from being too low. Through the control of single-chip microcomputer subsystem, it can measure and display output power, the supply power of the DC power source, and overall efficiency. This system utilizes electronic switches connected with band-stop filters, with the band-stop frequency ranging from 40～60Hz.

Design of High Gain Single Stage Telescopic Cmos Operational Amplifier

A need for high gain operational amplifiers (op-amps) exists for certain applications. This requires research in the area of its gain without affecting other parameters drastically. In this paper, high gain single stage Telescopic CMOS operational amplifier has been designed and verified, using PSPICE simulation software. The designed circuit operates at ±5V power supply in the 1µm CMOS technology. The simulation results show that the proposed single stage Telescopic CMOS op-amp has an open loop gain of 77.777dB, unity gain frequency of 7.3054MHz, ICMR of -0.248V to 4.4120V and output voltage swing of 7688.8 times to that of input. A 2pF load capacitor is applied in performing a stable phase margin of 80.669°. As result shows that the designed circuit has high gain, which is used for various applications where very large gain is required to amplify weak signals, such as heart beat in medical instrumentations. The total power consumed by the device is 0.589mW. This shows that the power consumed by the device is too small. Therefore, this device can operate for longer duration of time. The smaller the power dissipation the better the device is. Low power operation is a very important quality factor for batteries that should supply the system for hours or days to power more and more electronic systems.

Design, optimization, and analysis of thulium-doped optical fiber amplifiers for E-band communication

Design, optimization, and analysis of thulium-doped optical fiber amplifiers for E-band communication

Enhancing the design of a two-stage CMOS operational amplifier utilising the Bat Algorithm

ABSTRACT The increasing demand for high-performance two-stage CMOS Op-Amps in electronic, communications, and biomedical applications necessitates their operation with wide bandwidth, high voltage gain, and low power consumption. By leveraging the Bat Algorithm global search and local exploration capabilities, the study demonstrates a significant improvement in the amplifier’s overall performance. This design of a two-stage CMOS Op-Amp using 0.18 µm TSMC technology, powered by a ± 1.8 V supply voltage. The simulation outcomes were gathered using the PSPICE software (version 17.4). These design strategies prove highly efficient, achieving high gain, high frequency, and low power consumption. Additionally, the paper showcases the execution and simulation results of a two-stage CMOS Op-Amp based on the Bat Algorithm, utilising MATLAB for this purpose. The employment of the BA results in substantial enhancements in performance metrics. Specifically, the Unity Gain Bandwidth sees a doubling in its value, the voltage gain rises by 20%, power consumption falls by 39.1%, and the Common Mode Rejection Ratio improves by 20% compared to a two-stage CMOS Op-Amp designed without the BA. The findings underscore the BA potency as a robust optimisation method for boosting the performance of a two-stage CMOS Op-Amp.

A wideband inductorless LNA exploiting three-stage feedback and thermal noise canceling

In inductorless wideband low-noise amplifier (LNA) design, input-matching is traded off with noise figure (NF). The common-source noise-canceling (CSNC) structure and the gyrator alleviate this trade-off, but the corresponding study is insufficient. This work combines the CSNC and gyrator and introduces a three-stage feedback loop to achieve high feedback gain while minimizing the added input capacitance. Hence, the trade-off between NF and input impedance matching is significantly released. Consequently, the lowest NF among inductorless LNAs was achieved, while an operation bandwidth of more than 3 GHz was obtained. Post-layout simulation results in 40 nm CMOS technology show that the circuit achieves an NF of 1.35 dB–1.7 dB while maintaining a wide operation bandwidth of 100 MHz to 3.46 GHz. As far as the author knows, this is the lowest NF inductorless LNAs have achieved. Furthermore, S21 of 10.9 dB and IIP3 (input third-order intercept point) of −5.6 dB m are obtained, and the circuit consumes 14.9 mW at a 1.2 V voltage supply. Being self-biased, the circuit core consumes only 0.0032 mm2 die area.

Simulation and Design of Quantum Phase Slip Junction-Based Parametric Amplifiers

Simulation and Design of Quantum Phase Slip Junction-Based Parametric Amplifiers

Physics‐informed neural network assisted automated design of power amplifier by user defined specifications

AbstractThis article presents a model that can automatically produce a power amplifier's (PA) design parameters, that is, transmission lines (TLs) dimension, from a dataset of user‐specified design goals like gain, efficiency, linearity, and scattering (S‐) parameters. Based on the applied boundary conditions, a synthetic dataset is generated with the best range of design parameters (W and L). This dataset is utilized for training the physics‐informed neural network (PINN) model with user‐specified design goals as input and design parameters as target to produce the optimum value of W and L as the resultant output. Furthermore, utilizing the obtained dimensions, design, simulation, fabrication, and measurement of a PA are performed to validate our proposed model. The results of large signal measurements of PA are drain efficiency (DE) of 26.9%, power added efficiency (PAE) of 24.7%, output power (Pout) of 30.98 dBm at an input power of 19 dBm, and gain of 12.41 dB at an operating frequency of 1.625 GHz. It has been observed that the design parameters produced by the model have a significant agreement with the validated output. Also, the statistical error analysis is done by calculating the error metrics between the validated output and the actual output of the PA design.

Asymmetric Doherty power amplifier design considering the effects of peaking power amplifier early conduction

During the design of a Doherty power amplifier (DPA), the phenomenon of peaking PA turning on in advance is commonly observed. This is mainly due to the feedback of the main PA signal to the gate of the peaking PA through the gate-drain feedback capacitor, which results in an increase in its gate voltage. As a result, the overall efficiency of the back-off region is significantly reduced. This paper first describes the phenomenon of peaking PA turning on in advance. The formula for the voltage (referred to as the feedback gate voltage, FGV) imposed on the gate of the peaking PA by the main PA signal is then deduced. On this basis, the FGV is analysed numerically. For verification, an asymmetric DPA with a 9 dB output back-off (OBO) power level is designed and fabricated in this paper using GaN CGH40010F and CGH40025F transistors. According to the measurement results, the saturated drain efficiency of the DPA is 53.5%–63.3% in the 0.75–1.25 GHz band, the efficiency at the 9 dB OBO level is between 45.5%–54%, and the saturated output power is between 45 dBm–45.7 dBm, with a saturation gain of more than 8 dB.

Broadband dual-input doherty power amplifier design based on a simple adaptive power dividing ratio function

Broadband dual-input doherty power amplifier design based on a simple adaptive power dividing ratio function

Design and Development of GaN-Based Power Amplifier for Radar Applications

This paper presents a comprehensive overview of Gallium nitride (GaN)-based power amplifier (PA) design for various frequency bands. GaN-based technology has emerged as a promising alternative to traditional silicon-based amplifiers due to its superior performance characteristics, which are discussed in this paper. This paper also discusses the key design parameters and challenges associated with PA design. Various design techniques and topologies for GaN power amplifiers are explored besides addressing theoretical considerations of PA design along with a complete systematic design procedure for L-Band amplifier using the wolfspeed large signal GaN HEMT model. To further demonstrate the useful methodology, the designs of S-band and C-band PAs are also presented. GaN-based devices are very promising candidates for high-power applications. It is widely used in various high-power applications including communication and radar.

Design, Implementation and Performance Analysis of RF Power Amplifier for 5G Mobile Communication in the Sub-6 GHz Band Using Advanced Node 18nm FinFET Technology

Design, Implementation and Performance Analysis of RF Power Amplifier for 5G Mobile Communication in the Sub-6 GHz Band Using Advanced Node 18nm FinFET Technology

A gm/ID-Based Low-Power LNA for Ka-Band Applications.

This article presents the design of a low-power low noise amplifier (LNA) implemented in 45 nm silicon-on-insulator (SOI) technology using the gm/ID methodology. The Ka-band LNA achieves a very low power consumption of only 1.98 mW andis the first time the gm/ID approach is applied at such a high frequency. The circuit is suitable for Ka-band applications with a central frequency of 28 GHz, as the circuit is intended to operate in the n257 frequency band defined by the 3GPP 5G new radio (NR) specification. The proposed cascode LNA uses the gm/ID methodology in an RF/MW scenario to exploit the advantages of moderate inversion region operation. The circuit occupies a total area of 1.23 mm2 excluding pads and draws 1.98 mW from a DC supply of 0.9 V. Post-layout simulation results reveal a total gain of 11.4 dB, a noise figure (NF) of 3.8 dB, and an input return loss (IRL) better than 12 dB. Compared to conventional circuits, this design obtains a remarkable figure of merit (FoM) as the LNA reports a gain and NF in line with other approaches with very low power consumption.

Modeling extended L-band fiber amplifiers using neural networks trained on experimental data

Producing high performance amplifiers requires accurate numerical models. As the optimization space is large, computationally efficient models are of great value. Parameter-based models for L-band amplifiers have accuracy limited by difficulty in estimating the Giles-parameter. The use a neural network model can avoid parametrization. We exploit a rich, experimentally captured training set to achieve a high accuracy neural network model. Our approach creates independent models for gain and noise figure. We examine both core and cladding pumping methods, again with independent models for each. The neural networks outperform parameter-based models with higher accuracy (variance of error reduced by 50%) and extremely fast simulation times (400 times faster), greatly facilitating amplifier design. As an example application, we design an amplifier to optimize optical signal-to-noise ratio by exhaustive search with our fast neural network models.

Slew-Rate Enhancement Techniques for Switched-Capacitors Fast-Settling Amplifiers: A Review

This review is aimed at the integrated circuit design community and it explores slew-rate enhancement techniques for switched-capacitor amplifiers, with a primary focus on optimizing settling time within power constraints. Key challenges are addressed, including the selection between single-stage and two-stage amplifiers, along with the utilization of advanced circuit-level techniques for slew-rate enhancement. Presently, there exists a gap in comprehensive discussion, with reliance primarily on two Figures of Merit aimed at assessing power efficiency under specific capacitive loads. However, these metrics fail to adequately assess the performance of the existing slew-rate enhancer solutions at different values of capacitive loads. As a consequence, the designer lacks clear guidelines in practical situations. This review provides a state-of-the art mapping under a figure of merit dedicated to assess the whole settling delay, and also introduces a novel performance metric which highlights the role of the circuital architectures, regardless of external operating conditions. By offering a thorough examination, this review seeks to steer future research in switched-capacitor amplifier design, thereby facilitating informed decision-making and fostering innovation in the field.

ECG signal quality in intermittent long-term dry electrode recordings with controlled motion artifacts.

Wearable long-term monitoring applications are becoming more and more popular in both the consumer and the medical market. In wearable ECG monitoring, the data quality depends on the properties of the electrodes and on how they interface with the skin. Dry electrodes do not require any action from the user. They usually do not irritate the skin, and they provide sufficiently high-quality data for ECG monitoring purposes during low-intensity user activity. We investigated prospective motion artifact-resistant dry electrode materials for wearable ECG monitoring. The tested materials were (1) porous: conductive polymer, conductive silver fabric; and (2) solid: stainless steel, silver, and platinum. ECG was acquired from test subjects in a 10-min continuous settling test and in a 48-h intermittent long-term test. In the settling test, the electrodes were stationary, whereas both stationary and controlled motion artifact tests were included in the long-term test. The signal-to-noise ratio (SNR) was used as the figure of merit to quantify the results. Skin-electrode interface impedance was measured to quantify its effect on the ECG, as well as to leverage the dry electrode ECG amplifier design. The SNR of all electrode types increased during the settling test. In the long-term test, the SNR was generally elevated further. The introduction of electrode movement reduced the SNR markedly. Solid electrodes had a higher SNR and lower skin-electrode impedance than porous electrodes. In the stationary testing, stainless steel showed the highest SNR, followed by platinum, silver, conductive polymer, and conductive fabric. In the movement testing, the order was platinum, stainless steel, silver, conductive polymer, and conductive fabric.

A new design approach of Rat-Race coupler based compact GaN HEMT power amplifier towards flat high efficiency over broadband

This paper presents a high efficiency Rat-Race Coupler based compact GaN HEMT power amplifier (PA) design over broadband for high power transmitter in wireless communication. The rat-race coupler integrated PA Compact design is proposed for the first time as per author best knowledge. The design methodology used a higher order two open stubs and a rat-race coupler (RRC) at input/output sections to control harmonics impedances. The RRC is used to enhance the i/o power, and efficiency over broadband, which provides a good insertion loss, and consumes the least power and non-crucial impedance bandwidth for the normalized frequency band of interest. As a proof of concept, a PA is fabricated using a monolithic microwave integrated circuit (MMIC) 0.15 µm gallium nitride high electron mobility transistor (GaN HEMT) process. The measured result shows that the designed PA achieves a flat power added efficiency (PAE) of 65 % − 74 %, output power (Pout) of 44.8 dBm − 46 dBm, and drain efficiency (DE) of 72 % − 85 %, over a record wide frequency of 1.8 GHz − 3.6 GHz, which is the highest one among all reported harmonic tuned PAs.

Catalyzing satellite communication: A 20W Ku-Band RF front-end power amplifier design and deployment.

This paper presents a groundbreaking Ku-band 20W RF front-end power amplifier (PA), designed to address numerous challenges encountered by satellite communication systems, including those pertaining to stability, linearity, cost, and size. The manuscript commences with an exhaustive discussion of system design and operational principles, emphasizing the intricacies of low-noise amplification, and incorporating key considerations such as noise factors, stability analysis, gain, and gain flatness. Subsequently, an in-depth study is conducted on various components of the RF chain, including the pre-amplification module, driver-amplification module, and final-stage amplification module. The holistic design extends to the inclusion of the display and control unit, featuring the power-control module, monitoring module, and overall layout design of the PA. It is meticulously tailored to meet the specific demands of satellite communication. Following this, a thorough exploration of electromagnetic simulation and measurement results ensues, providing validation for the precision and reliability of the proposed design. Finally, the feasibility of that design is substantiated through systematic system design, prototype production, and exhaustive experimental testing. It is noteworthy that, in the space-simulation environmental test, emphasis is placed on the excellent performance of the Star Ku-band PA within the 13.75GHz to 14.5GHz frequency range. Detailed power scan measurements reveal a P1dB of 43dBm, maintaining output power flatness < ± 0.5dBm across the entire frequency and temperature spectrum. Third-order intermodulation scan measurements indicate a third-order intermodulation of ≤ -23dBc. Detailed results of power monitoring demonstrate a range from +18dBm to +54dBm. Scans of spurious suppression and harmonic suppression, meanwhile, show that the PA evinces spurious suppression ≤ -65dBc and harmonic suppression ≤ -60dBc. Rigorous phase-scan measurements exhibit a phase-shift adjustment range of 0° to 360°, with a step of 5.625°, and a phase-shift accuracy of 0.5dB. Detailed data from gain-scan measurements show a gain-adjustment range of 0dB to 30dB, with a gain flatness of ± 0.5dB. Attenuation error is ≤ 1%. These test parameters perfectly align with the practical application requirements of the technical specifications. When compared to existing Ku-band PAs, our design reflects a deeper consideration of specific requirements in satellite communication, ensuring its outstanding performance and uniqueness. This PA features good stability, high linearity, low cost, and compact modularity, ensuring continuous and stable power output. These features position the proposed system as a leader within the market. Successful orbital deployment not only validates its operational stability; it also makes a significant contribution to the advancement of China's satellite PA technology, generating positive socio-economic benefits.

Design of a charge-sensitive amplifier for MEMS piezoelectric hydrophone

Hydrophone is an important part of sonar system and convert acoustic signal into electrical signal. However, the electrical signal generated by the hydrophone is relatively weak and cannot be directly used for underwater detection and communication. Therefore, it is necessary to preprocess the generated electrical signal. In this paper, a switched capacitor charge-sensitive amplifier for MEMS piezoelectric hydrophone is designed. In the structure, two single-channel charge amplifiers are used for time-division multiplexing. The noise sampling and charge amplification are performed separately in the same half cycle to achieve the effect of alternating output, thereby increasing the sampling rate and solving the problem of discontinuous output of the switched capacitor circuit. In the circuit design, virtual switch and two-phase non-overlapping clock are adopted to reduce the error caused by charge injection and clock feedthrough effect of CMOS switch. What’s more, the correlated double sampling technique is used to reduce the offset and low frequency noise of the circuit. The gain of the charge-sensitive amplifier designed in this study is 26 dB, the bandwidth is 0.8Hz∼17.6kHz, the equivalent input noise power spectral density is 115.6 nV/Hz at 0.1Hz, and the charge sensitivity is 2 mV / pC. The fitting line between the input charge and the amplitude of the output curve is similar to the theory. The simulation results show that the charge-sensitive amplifier proposed in this study meets the design requirements of the MEMS piezoelectric hydrophone readout circuit.