Depletion MOSFETs Research Articles

60Co gamma and high energy ion impacts on threshold characteristics and its recovery in N-channel depletion MOSFETs

60Co gamma and high energy ion impacts on threshold characteristics and its recovery in N-channel depletion MOSFETs

High temperature operation of a monolithic bidirectional diamond switch

We report the 250 °C operation of a diamond-based monolithic bidirectional switch. A normally-ON double gate deep depletion MOSFET was fabricated with a 400 nm p-type channel with a boron doping of [NA-ND] = 2.3 × 1017 cm−3 and an Al2O3 gate oxide thickness of 50 nm. The Ist and IIIrd quadrants transistor characteristics are successfully measured by controlling the channel conductivity with both gates separately, with a clear ON and OFF state. A threshold voltage around 35 V is obtained with a low minimum gate leakage current of 1.00 × 10−4 mA/mm at a gate-source bias VGS = 50 V. The bidirectional switch is then obtained by operating the MOSFET in the Ist quadrant of each gate setup. This first proof of concept offers a reverse conducting and reverse blocking diamond MOSFET, with only one drift region layer.

A SiC CMOS Linear Voltage Regulator for High-Temperature Applications

The first SiC integrated circuit linear voltage regulator is reported. The voltage regulator uses a 20-V supply and generates an output of 15 V, adjustable down to 10 V. It was designed for loads of up to 2 A over a temperature range of 25-225 °C. It was, however, successfully tested up to 300 °C. The voltage regulator demonstrated load regulations of 1.49% and 9% for a 2-A load at temperatures of 25 and 300 °C, respectively. However, the load regulation is less than 2% up to 300 °C for a 1-A load. The line regulation with a 2-A load at 25 and 300 °C was 17 and 296 mV/V, respectively. The regulator was fabricated in a Cree 4H-SiC 2-μm experimental process and consists of 1000, 32/2-μm NMOS depletion MOSFETs as the pass device, an integrated error amplifier with enhancement MOSFETs, and resistor loads, and uses external feedback and compensation networks to ensure operational integrity. It was designed to be integrated with high-voltage vertical power MOSFETs on the same SiC substrate. It also serves as a guide to future attempts for voltage regulation in any type of integrated SiC circuitry.

Analysis of 80-MeV Carbon and 80-MeV Nitrogen Ion Irradiation Effects on N-Channel MOSFETs

N-channel depletion MOSFETs were irradiated with 80 MeV Carbon (C6+) and 80 MeV Nitrogen (N6+) ions in the dose range from 100 krad (Si) to 30 Mrad (Si). The electrical characteristics of MOSFET such as threshold voltage (Vth), density of interface trapped charges ( ${{\Delta }}\text{N}_{\mathrm{ it}}$ ), density of oxide trapped charges ( ${{\Delta }}\text{N}_{\mathrm{ ot}}$ ), transconductance (gm), mobility ( ${{\mu }}$ ), leakage current (IL) and drain saturation current (IDSat) were studied as a function of dose. A considerable increase in ${{\Delta }}\text{N}_{\mathrm{ it}}$ and ${{\Delta }}\text{N}_{ot}$ and decrease in $\text{V}_{\mathrm{ th,}}\text{g}_{\mathrm{ m}}$ , ${{\mu }}$ , and $\text{I}_{\mathrm{ D~Sat}}$ was observed after irradiation. The ${{\mu }}$ was correlated with ${{\Delta }}\text{N}_{\mathrm{ it}}$ and it is found that the contribution of ${{\Delta }}\text{N}_{\mathrm{ ot}}$ in degrading the mobility of charge carriers is negligible.The ion irradiated results were compared with Co-60 gamma irradiated results and found that the degradation is more for Co-60 gamma irradiated devices at lower doses, whereas at higher doses, the degradation is more for heavy ion irradiated devices.

Deep depletion concept for diamond MOSFET

A stable deep depletion regime is demonstrated in metal oxide semiconductor capacitors using p-type oxygen-terminated (100) diamond as a semiconductor and Al2O3 deposited by Atomic Layer Deposition at 380 °C. Current voltage I(V) and capacitance voltage C(V) measurements were performed to evaluate the effectiveness of diamond semiconductor gate control. An effective modulation of the space charge region width is obtained by the gate bias, where the deep depletion regime is demonstrated for a positive gate bias. The deep depletion concept is described and proposed for MOSFET devices. Finally, a proof of concept of diamond deep depletion MOSFETs is presented.

A comparison of 4 MeV Proton and Co-60 gamma irradiation induced degradation in the electrical characteristics of N-channel MOSFETs

N-channel depletion MOSFETs were irradiated with 4MeV Proton and Co-60 gamma radiation in the dose range of 100krad(Si) to 100Mrad(Si). The electrical characteristics of MOSFET such as threshold voltage (Vth), density of interface trapped charges (ΔNit), density of oxide trapped charges (ΔNot), transconductance (gm), mobility (μ), leakage current (IL) and drain saturation current (ID Sat) were studied as a function of dose. A considerable increase in ΔNit and ΔNot and decrease in Vth,gm, μ, and ID Sat was observed after irradiation. The results of 4MeV Proton irradiation were compared with that of Co-60 gamma radiation and it is found that the degradation is more for the devices irradiated with 4MeV Protons when compared with the Co-60 gamma radiation. This indicates that Protons induce more trapped charges in the field oxide region when compared to the gamma radiation.

Swift heavy ion irradiation and annealing studies on the I–V characteristics of N-channel depletion Metal–oxide–semiconductor field-effect transistors

N-channel depletion MOSFETs were irradiated with different swift heavy ions viz., 175 MeV Ni13+ ions, 140 MeV Si10+ ions, 100 MeV F8+ ions, 95 MeV O7+ ions and 48 MeV Li3+ ions in the same dose range of 100 krad–100 Mrad. The different electrical characteristics of MOSFETs were studied before and after irradiation and after annealing. The degradation and recovery mechanisms were studied systematically. It was found that around 80 % degradation in transconductance and mobility and almost 100 % recoveries in the electrical characteristics of irradiated MOSFETs after annealing.

A SiC NMOS Linear Voltage Regulator for High-Temperature Applications

The first SiC integrated circuit linear voltage regulator is reported. The voltage regulator uses a 20-V supply and generates an output of 15 V, adjustable down to 10 V. It was designed for loads of up to 2 A over a temperature range of 25-225 °C. It was, however, successfully tested up to 300 °C. The voltage regulator demonstrated load regulations of 1.49% and 9% for a 2-A load at temperatures of 25 and 300 °C, respectively. However, the load regulation is less than 2% up to 300 °C for a 1-A load. The line regulation with a 2-A load at 25 and 300 °C was 17 and 296 mV/V, respectively. The regulator was fabricated in a Cree 4H-SiC 2-μm experimental process and consists of 1000, 32/2-μm NMOS depletion MOSFETs as the pass device, an integrated error amplifier with enhancement MOSFETs, and resistor loads, and uses external feedback and compensation networks to ensure operational integrity. It was designed to be integrated with high-voltage vertical power MOSFETs on the same SiC substrate. It also serves as a guide to future attempts for voltage regulation in any type of integrated SiC circuitry.

The effect of swift heavy ion irradiation on threshold voltage, transconductance and mobility of DMOSFETs

N-channel depletion MOSFETs were irradiated with 140 MeV Si 10+ ions, 100 MeV F 8+ ions and 48 MeV Li 3+ ions in the dose range from 100 krad to 100 Mrad. The MOSFET parameters such as threshold voltage ( V TH), transconductance ( g m) and mobility of carriers ( μ) were determined by systematically studying the I– V characteristics before and after irradiation. The ion irradiated results were compared with Co-60 gamma irradiated results in the same dose range. The degradation in V TH, g m and μ was found to be more for the devices irradiated with Co-60 gamma radiation than that irradiated with swift heavy ions.

Novel Method of Intrinsic Characteristic Extraction in Lightly Doped Drain Metal Oxide Semiconductor Field Effect Transistors for Accurate Device Modeling

A lightly doped drain (LDD) region, particularly a gate-overlapped LDD (GOLD) region, is subjected to a gate electric field and its gate-controlled resistance affects the device characteristics. We developed a new extraction method for determining the intrinsic characteristics of LDD MOSFETs using a simple series resistance model, in which the GOLD region is assumed to be a depletion MOSFET with a negative threshold voltage derived from C–V measurement. Polycrystalline-silicon (poly-Si) TFTs with a channel length of 4–100 µm were used for the test LDD samples, particularly GOLD MOSFETs. It was demonstrated that the new proposed method precisely extracts the intrinsic characteristics of poly-Si GOLD TFTs by comparing them with the intrinsic characteristics of poly-Si Self-Aligned (SA) TFTs extracted by the conventional method.

Threshold voltage characteristics of ion-implanted depletion MOSFETs

An analytical model for the threshold voltage characteristics of depletion MOSFETs with implanted channels is developed. The model is based on the transformation of an implanted channel profile into an electrically equivalent triangular profile. As a result of this transformation, it is possible to incorporate into the model the effect of nonuniform channel doping in a simple and practical manner. Another important effect taken into account is sharing of the depletion charge between the channel and the source and drain regions in short-channel devices. The model equations are applicable to transistors with both shallow and deep implanted channels. Very good agreement between the simulated and measured characteristics is observed.

A semi-analytical approach to the evaluation of threshold voltage in depletion MOS's with nonuniformly doped substrates

D.A. Antoniadis' algorithm (ibid., vol.ED-31, no.3, p.303-7, 1984) is extended to cover the computation of threshold voltage for depletion or buried-channel MOSFETs. It is shown that a key factor in its evaluation, of the derivative of the integral charge of the mobile minority carriers in the substrate with respect to the gate-source bias, can easily be calculated using the concept of flat-band capacitance. The threshold voltage is thus computed without requiring strict numerical solution of Poisson's equation, yet the accuracy is very good. This modified algorithm has been implemented in SUPREM III, and good agreement between simulation and experimental results has been achieved. >

CW argon-laser-induced zone-melting recrystallization of thin silicon on oxide

Silicon on insulator (SOI) technologies offer significant possibilities for high-speed and high-density integrated circuit applications. Single-crystal silicon islands of 50 μm width and 165 μm length have been successfully obtained by a combination of seeding structures, a specially-shaped laser beam spot and locally altered capping layers. No grain boundaries and no sub-grain boundaries were observed in the island etched with Secco etchant. The recrystallized film had the same 〈100〉 crystal orientation as the silicon substrate. The layers were smooth on the surface. The silicon recrystallization obtained with a CW argon laser is described, and two types of seeding structures are compared. The mechanisms of the single-crystal seeding growth of these structures are discussed. p-Channel depletion MOSFET's with L=10 μm and w=40 μm were fabricated in the recrystallized film. The I D- V D characteristics of the devices were excellent. The surface hole mobility was calculated to be 170 cm 2/V·s, the same as for devices fabricated in bulk single crystal.

Simulation of the accumulation-punchthrough mode in depletion MOSFETs

An analytical model is developed for a depletion MOSFET with a built-in channel operating in the accumulation-punchthrough mode. The model equations take into account several important effects associated with this mode of operation, including charge sharing between the channel and the source and drain regions. Closed-form expressions are derived for the output I–V characteristics, drain conductance in the linear region, and gate and substrate transconductances in the saturation region. Useful equations for the threshold and saturation voltages are also provided. High accuracy of the model is confirmed by the experimental results.

Relationship between short channel behavior and long term stability of n-channel enhancement and depletion MOSFETs

Enhancement and depletion mode n-channel MOSFETs are investigated with respect to short channel effects and hot carrier related instabilities. It is found that subthreshold characteristics of normally off type devices are improved by additional deep channel implants. However, long term stability of enhancement mode devices decreases with the deep channel implant dose. A similar behavior is observed for depletion mode devices. Significant improvement in device stability can be realized using buried channel conduction. However, short channel effects attain untolerable magnitudes in devices with deep buried channels. It is concluded in this paper, that the conventional approaches used for optimization of long term stability and d.c. characteristics of small size MOSFETs are technologically incompatible. In the outlook, device design requirements are discussed to circumvent these problems.

A Simulation Method to Completely Model the Various Transistor I-V Operational Modes of Long Channel Depletion MOSFET's

It is known that a depletion MOS device behaves quite differently from an enhancement device. Because of its intrinsic difference, depletion I-V characteristics are much more complicated than are the I-V functions of an enhancement MOSFET. The conventional transistor I-V equation developed for enhancement transistors cannot be applied directly to depletion transistors. In this paper, seven operating modes a depletion device can have are discussed. The concept of extended depletion regions is introduced to calculate transistor I-V characteristics. A graphical representation of the universal channel depth versus the channel potential is proposed to help in understanding the engineering significance of operational modes depletion devices can assume. A flowchart is developed to calculate the depletion transistor I-V characteristics. The simulation and analysis aid can be easily adapted to computer-oriented circuit and device investigations.

Modeling gate modulation effects on FET electrical characteristics with arbitrary doping profiles

A generalized approach for modeling the device characteristics of a JFET/MESFET, depletion MOSFET and MESFET/BUFFER structure with non-uniform doping profiles is derived from the depletion MOSFET viewpoint including the oxide layer explicitly. The results are exemplified for the power-law doping case with different oxide thickness and different dopant gradient.

Analytical model and characterization of small-geometry buried-channel depletion MOSFETs

Small-geometry buried-channel depletion MOSFETs (BCD-MOSFETs) are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity saturation effects. The drain current is calculated based on the surface electrons induced by the gate-bias voltage and the buried-channel junction FET. The narrow-channel effect is modeled not only by the additional depletion-layer charges created by a fringing-field effect in the field region, but also by the effective channel width as a function of gate-bias voltage. Surface-electron mobility is modeled as a function of the vertical and lateral electrical fields created by the gate-bias and drain voltages, while bulk-electron mobility is described as a function of the lateral electric field due to the drain voltage. Theoretical results on drain current are in good agreement with experimental results.

GaAs microwave MOSFET's

GaAs microwave metal-oxide-semiconductor field-effect transistors (MOSFET's) with plasma-grown native oxides as gate insulator have been fabricated using a low-temperature magnetically controlled plasma-oxidation technique. A small-signal enhancement device with the gate length of 2.0 µm has demonstrated useful unilateral power gains in the 2-8-GHz frequency range. A maximum frequency of oscillation in the enhancement device is 13 GHz. This is the highest in all enhancement-mode GaAs devices reported up to this time. A medium-power depletion device with the gate length of 1.8 µm has the maximum frequency of oscillation of 22 GHz. This value is 10 percent larger than that of the best analogous metal-semiconductor field-effect transistor (MESFET). The intrinsic current-gain cutoff frequency for the depletion MOSFET is 4.5 GHz which is 22 percent higher than that of the MESFET. The superiority of the depletion MOSFET in the small-signal microwave performance over the MESFET results from the smaller gate parasitic capacitance in the MOSFET as compared to the MESFET. The depletion MOSFET has produced 0.4-W output power at 6.5 GHz as a Class A amplifier. Quite a large frequency dispersion of transconductance is observed in the enhancement MOSFET at a frequency range between 10 and 100 kHz and attributed to interface states. The effect of the interface states does not severely restrict the microwave-frequency capabilities of the enhancement MOSFET as well as the depletion MOSFET since the interface states are unable to follow the input-signal variations at high frequencies.

Analysis of the deep depletion MOSFET and the use of the d.c. characteristics for determining bulk-channel charge-coupled device parameters

A qualitative and quantitative analysis of the deep depletion MOSFET operated in the regimes of depletion, enhancement and depletion/enhancement, is presented. The quantitative analysis presented here does not make any of the simplifications made in some earlier papers, applicable to shallow channel depletion MOSFETs, and uses a four terminal device model so as to provide a complete set of characterisation equations for each mode of operation. It is demonstrated that the device parameters of flatband voltage, implanted channel doping and depth, and bulk and surface carrier mobilities, can easily be determined by use of some of the characteristics equations in conjunction with simple measurements made directly from the drain current/drain voltage characteristics. Furthermore these parameters are applicable to bulk-channel charge-coupled devices fabricated under the same implantation and drive-in conditions. As the device parameters are determined from the drain current/drain voltage characteristics the techniques presented offer an attractive alternative to the more complicated C- V methods used for bulk-channel charge-coupled device characterisation. The validity of the model and the techniques used to determine the device parameters is demonstrated by the good agreement between calculated and measured results obtained from fabricated devices.