The most promising emerging technology that can reduce the power, area and delay in digital circuits is Quantum-dot Cellular Automata (QCA) technology. The Serial Input-Serial Output (SISO) Shift Register (SR) is a basic component in digital circuits. The SISO SR can be designed using two methods in the QCA technology, directly mapping circuits from the CMOS technology and using the inherent capability of the QCA technology. This paper presents and evaluates the new [Formula: see text]-bit QCA SISO SR that not only uses the inherent capability of QCA technology but also has a regular architecture. The proposed [Formula: see text]-bit SISO SR is developed based on the building block, which is designed in this paper. In addition, the developed QCA SISO SR has coplanar architecture and it has the ability to correct or change data. The proposed [Formula: see text]-bit SISO SR is evaluated for 3, 4 and 5 bits using QCADesigner-[Formula: see text]. The results demonstrate that the designed circuits for 3-, 4- and 5-bit QCA SISO SRs require 68 (0.06 [Formula: see text]m[Formula: see text], 92 (0.08[Formula: see text][Formula: see text]m[Formula: see text] and 116 (0.09[Formula: see text][Formula: see text]m[Formula: see text] cells (area), respectively. The comparison demonstrates that the developed QCA SISO SRs have advantages in comparison to other QCA SISO SR circuits.