1. Introduction Depleted body devices such as FinFETs and Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) MOSFETs have emerged as architectures of choice for technology nodes where conventional planar bulk devices do not provide enough immunity against short channel effects and variability. Offering unsurpassed electrostatic control of the channel, NanoWire FETs (NWFETs)-based architectures are considered as promising successors for future nodes. In all these depleted-body architectures, the control of active power is a strong requirement. Along with supply voltage scaling, it imposes design-level power management strategies, parasitic capacitance reduction and it calls for the use of high-mobility channel materials. For p-type channels, compressively strained silicon germanium alloys (SiGe) are attractive candidates. When depleted-body devices are fabricated on SOI, local germanium enrichment can convert Si to SiGe. This fabrication sequence starts with the growth of an epitaxial SiGe layer, followed by oxidation. During the latter, the surface of the SiGe layer is converted to silicon dioxide while Ge is segregated to the lower part of the stack, which gradually becomes more Ge-rich. This paper discusses the fabrication of SiGe channel for UTBBSOI MOSFETs, FinFETs and NWFETs. It reviews the key points associated to each architecture and critical aspects related to SiGe thermal budget, critical thickness, growth rate control and crystal quality. Results highlight the interest of NWFETs for future technology nodes. 2. SiGe channel UTBB FDSOI MOSFETs The Ge enrichment technique was initially developed for the planar FDSOI architecture and in that context, it was shown that high quality uniform SiGe films can be fabricated by alternating oxidizing and diffusion steps. For a SiGe/Si initial stack of given thickness and composition, the enrichment thermal budget needs to be significantly different when it is performed on SOI or on tensile SOI (sSOI). In the last case, the film initial tensile strain slows Ge diffusion (Fig. 1-a), which can lead to Ge pile up and defect formation if process temperature is too high with respect to the peak concentration (Fig. 1-b). Defect-free SiGe layers can be obtained on sSOI by using longer diffusion steps and reducing process temperature (Fig. 1-c). 3. SiGe-channel FinFET Although Ge enrichment can produce fully-strained layers, the patterning of SiGe blanket film into finite-dimension active areas yields elastic stress relaxation. This feature is particularly attractive for the fabrication of SiGe channel FinFETs where channel configuration results in longitudinal uniaxial compression, which is most favorable to hole transport. However, this processing sequence involves the elaboration of a thick blanket SiGe layer (through Ge enrichment and epitaxial thickening). Even with optimized processing, for a targeted Fin height (SiGe thickness) of 35 nm, significant crystal quality degradation is observed by X-Ray Reciprocal Space Mapping for {113} (RSM) when the Ge fraction approaches 50% (Fig. 2-a), in agreement with literature. To overcome this limit, Ge enrichment of already patterned Si Fins was investigated. This sequence relieves the limits set by SiGe critical thickness in the vertical direction, but it also constricts the pre-enrichment SiGe growth conditions. If SiGe growth rate is strongly dependent on crystal orientation, the final Fin profile is degraded (Fig. 2-b). In contrast, Fin profile can be maintained (Fig. 2-c) when uniform SiGe thickness can be achieved on Fin sidewalls (Fig. 2-d). RSM shows that Fins with up to 50% Ge fraction exhibit no significant relaxation (Fig. 2-e). This approach is expected to be most beneficial for tall Fins. 4. SiGe-channel NWFETs W-gate NWFETs were fabricated in a gate first scheme (Fig. 3-a). This configuration combines the respective benefits of SiGe channel FDSOI MOSFETs and FinFETs in terms of SiGe crystal stability [5] and uniaxial strain. With this and excellent electrostatic integrity, significant mobility gains are demonstrated down to a gate length of 14nm (Fig. 3-b), paving the way for future energy-efficient systems. 5. Acknowledgment Part of these results was obtained in a Joint Development Program between IBM, STMicroelectronics and LETI CEA. Figure 1
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Oct 4, 2016
Mehbuba Tanzid + 7
Open Access