Gate Oxide Degradation Research Articles

A Comparative Study of the Curing Effects of Local and Global Thermal Annealing on a FinFET

Recently, localized thermal annealing has been spotlighted as an effective method to cure aged devices. The degraded gate oxide can be successfully cured by local annealing, which utilizes Joule heat inherently generated in the device. But, despite this advantage, there has been no study comparing the curing effects with various other annealing methods. In this study, the curing effects of local annealing and a conventional global annealing method applied to SOI FinFETs are compared. The measured electrical characteristics are discussed to evaluate the damage curing with respect to curing level and variability.

Stable Operation of AlGaN/GaN HEMTs for 25 h at 400°C in air

Extreme environments such as the Venus atmosphere are among the emerging applications that demand electronics that can withstand high-temperature oxidizing conditions. While wide-bandgap technologies for integrated electronics have been developed so far, they either suffer from gate oxide and threshold voltage ( $V_{th}$ ) degradation over temperature, large power supply requirements, or intrinsic base current. In this letter, AlGaN/GaN high electron mobility transistors (HEMTs) are suggested as an alternative platform for integrated sensors and analog circuits in extreme environments in oxidizing air atmosphere over a wide temperature range from 22°C to 400°C. An optimal biasing region, with a peak of transconductance ( $g_{m,peak}$ ) at −2.3 V with a negligible shift over the temperature range was observed. Moreover, remarkably low $V_{th}$ variation of 0.9% was observed, enabling the design of analog circuits that can operate over the entire temperature range. Finally, the operation of the devices at 400°C and 500°C over 25 hours was experimentally studied, demonstrating the stability of the DC characteristics after the 5 hours of burn-in, at 400°C.

<italic>In situ</italic> Condition Monitoring of IGBTs Based on the Miller Plateau Duration

Aging precursor identification is crucial to achieving online condition monitoring and estimating the remaining lifetime of insulated-gate bipolar transistors (IGBTs). However, existing failure precursors are limited with respect to in situ monitoring. In this paper, the duration of the Miller plateau during the IGBT turn- on transition is proposed as an online precursor indicating two dominant types of failures. Based on the theoretical closed-form expressions, the adverse effects of package-related bond wire fatigue and chip-related gate oxide degradation on the Miller plateau duration are explained. By using a dedicated online measurement system that is implemented on the gate driver side, the proposed precursor is extracted during operation. Discrete IGBTs of two gate structures are employed during the accelerated aging tests. Negative and positive degradation trends of the Miller plateau duration under power cycling and high electric field stress, respectively, are revealed, thus illustrating the validity of the proposed method. Finally, the main differences in physics-of-failure between two types of aged devices are investigated using post-failure analysis. The innovation of applying the Miller plateau duration as a failure precursor involves its ability to accomplish real-time field monitoring and its sensitivity to multiple failure mechanisms.

Effect of Gate-Oxide Degradation on Electrical Parameters of Power MOSFETs

Gate oxide in power metal–oxide–semiconductor field effect transistors (MOSFETs) degrades over time. The degradation leads to an accumulation of oxide-trapped charges within the gate oxide and an accumulation of interface-trapped charges at the oxide–semiconductor surface of power MOSFETs. Overtime, such charges significantly alter the electrical parameters of power MOSFETs; to observe this, the electrical parameters are utilized as precursors of gate-oxide degradation. The purpose of this paper is threefold: 1) to propose a new online precursor of gate-oxide degradation—the gate plateau time; 2) to demonstrate a simultaneous dip-and-rebound variation pattern of four precursors of gate-oxide degradation: threshold voltage, gate plateau voltage, gate plateau time, and on-resistance; and 3) to compare the shift tendencies of each precursor over the course of gate-oxide degradation. The existing studies of gate-oxide degradation mechanisms and their effects on threshold voltage and mobility reduction were extended to correlate a variation of all four precursors using analytical expressions. The variation patterns were experimentally verified using high-electric field stressing in two different commercial power MOSFETs. The new precursor, the gate plateau time, was found to be a competitive gate-oxide degradation precursor, as it had a higher positive shift than threshold voltage and gate plateau voltage. In addition, the threshold voltage was found to be the most sensitive indicator of the negative shift (dip), while the on-resistance and gate plateau time were found to be the most sensitive indicators of the positive shift (rebound).

Bias temperature instability and condition monitoring in SiC power MOSFETs

Threshold voltage shift due to bias temperature instability (BTI) is a major concern in SiC power MOSFETs. The SiC/SiO2 gate dielectric interface is typically characterized by a higher density of interface traps compared to the conventional Si/SiO2 interface. The threshold voltage shift that arises from BTI has significant implications on the reliability of SiC power MOSFETs, hence, techniques for detecting the change in electrical parameters due to gate oxide degradation are desirable. Using accelerated high temperature gate bias stress tests on SiC MOSFETs, it has been shown that the output and transfer characteristics are affected by BTI. This paper presents the impact BTI induced threshold voltage shift on the forward voltage of the SiC MOSFET body diode during third quadrant operation. Using the forward voltage of the body diode during reverse conduction of low currents, threshold voltage shift can be detected, hence, the impact of BTI can be evaluated. The implications of the body diode forward voltage shift on junction temperature measurements are also studied in the context of TSEPs. The findings in this paper are important for engineers seeking to implement condition and health monitoring techniques on SiC power devices.

The threshold voltage degradation model of N Channel VDMOSFETs under PBT stress

With the voltage increasing in DC power systems, positive bias temperature instability (PBTI) induced gate oxide degradation of commercial n-channel power vertical double diffused MOSFETs (VDMOSFETs) has been greatly enhanced recently. However, it is not mature in some aspects, e.g., parametric models of PBTI and the turn-around phenomenon are rarely studied. Aiming at these disadvantages, the experimental study and the argument are proposed in this paper. First, the simulation was used to identify and verify the threshold voltage as the characteristic parameter and the accelerated experiment test was conducted to collect data for degradation modeling. Then, a Power law-Arrhenius combined model was adopted in the degradation model to take into account the electrical and thermal influence. Besides that, a two-phase PBTI degradation model was presented, which can describe the turn-around phenomenon. Moreover, the comparison of the estimated remaining useful life (RUL) results with the experimental data verified the accuracy of the developed model.

(Invited) Metallic Contamination Issues in Advanced Semiconductor Processing

As semiconductor devices continue to shrink, metallic contamination on silicon surfaces become to have a detrimental impact on VLSI device performance and yield. Surface metal impurities degrade gate oxide integrity [1] and cause the whisker growth in film deposition [2], while metal impurities dissolved in silicon cause recombination centers, junction leakage [3] and dark current in image sensors [4]. In this article, we have extensively reviewed metallic contamination issues including the analysis, prevention, removal, and gettering in advanced semiconductor processing. Trace metallic contamination on the silicon surfaces can be detected with VPD- or LPD-TXRF, AAS, and ICP-MS and these methods have been widely used. These analyses provide average metal concentration on the whole wafer surface with high detection sensitivity, while they do not give in-wafer distribution of metal concentration. However, metal impurities accidentally deposited in wafer processing are often localized. Direct TXRF provides in-wafer distribution of metal concentration, while its sensitivity is insufficient. Therefore, the methods to detect localized metal atoms with high sensitivity are required. TXRF following vapor phase treatment (VPT) has been developed to enhance the detection sensitivity without droplet collection [5] and the influence of VPT-induced trace particles on the detection sensitivity has been studied [6]. When III-V compound semiconductor materials are introduced for high mobility channels, the detection sensitivity on the III-V semiconductor surface by TXRF [7] and the metal collection efficiency [8] becomes critical issues. In order to control metal impurities in silicon, understanding of their penetration and diffusion behaviors is valuable. The amount of metals penetrating the silicon substrate depends on metal species, underlying films, their thickness, and annealing temperature. Cr and W penetrate the silicon substrate through the Si3N4 film more easily than through the thermally-grown SiO2 [9]. These metals on Si3N4 films must be strictly controlled before ion implantation. In-wafer distribution of recombination centers should be detected with high sensitivity and visualized with high detection sensitivity for advanced contamination control [10]. The deep energy levels, their depth profiles, and dark currents induced by metal impurities are varied with metal species [10-12]. The sensitivity of the deep level measurements should be improved. Gettering is effective to mitigate the influence of metal impurities on device characteristics. When extrinsic gettering such as ion implantation defects is used, the gettering design based on physical properties of metal species is required [13]. One of the intrinsic gettering techniques is gettering using oxide precipitates in silicon. For effective gettering by the oxide precipitates, the sufficient total surface area of the oxide precipitates should be close to the DZ [14]. Reference [1] P. S. D. Lin, J. Electrochem. Soc., 131, 1878 (1983). [2] G. M. Choi, ECS transactions, vol. 11, no. 2, p.133. [3] T. Kuroi, et. al, Tech. Digest of SSDM ’92 (1992). [4] W. C. McColgin, et.al, Mat. Res. Soc. Symp., Proc. Vol. 262, 1992 Material Research Society. [5] H. Takahara, et. al., Spectrochimica Acta Part B, 65, 1022 (2010). [6] R. Ohno and K. Saga, to be presented in 14th Symposium on Ultra Clean Processing of Semiconductor Surfaces, 2-5, Sept.2018, Leuven, Belgium. [7] K. Saga and R. Ohno, Solid State Phenomena, Vol. 255, pp 319-322 [8] H .Fontaine, T. Lardin, ECS transactions, 58 (6) 327-335 (2013). [9] K. Saga, et.al, ECS Journal of Solid State Science and Technology, 4 (5) P131-P136 (2015). [10] P. W. Mertens, et. al, Solid State Phenomena, Vol. 255, pp 309-312 [11] F. Russo, et. al, ECS J. Solid State Sci. Technol,. 6 (5), P217-P226 (2017). [12] E. Simoen, et.al, ECS Journal of Solid State Science and Technology, 5 (4) P3001-P3007 (2016). [13] K. Saga, Solid State Phenomena Vol. 187 (2012) 283-286 [14] K. Saga, et. al, ECS Journal of Solid State Science and Technology, 6 (5) P231-P234 (2017). [14] K. Saga, et. al, ECS Journal of Solid State Science and Technology, 6 (5) P231-P234 (2017).

SiC MOSFETs robustness for diode-less applications

ABSTRACTSilicon-Carbide (SiC) technology presents several advantages over silicon for power electronics applications, such as lower losses. However, SiC technology is not totally mature, and some reliability problems remain. This paper studies the robustness of SiC MOSFETs in the case of diode-less applications and the associated phenomena, such as gate oxide degradation. Several devices were stressed under conditions of inductive switching and inverse current conduction. These devices were periodically characterized. As a result, a threshold voltage shift was observed in the MOSFET, with a dependence on the duty cycle of the transistor. On the contrary, no significant degradation of the internal P-N junction of the transistor was observed.

A New Approach for VDMOSFETs’ Gate Oxide Degradation Based on Capacitance and Subthreshold Current Measurements Under Constant Electrical Stress

In this brief, we proposed a new gate oxide degradation model for vertical double diffused MOS devices under constant electrical stress. To form a complete model, we separated the changes associated with gate oxide and Si-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface. We presented oxide trap-induced gate oxide and interface trap-induced Si-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface degradation effects on the model, separately. We used capacitance measurements for gate oxide and subthreshold current measurements for Si-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface degradation. We presented the survive of the stress-induced gate oxide and interface capacitances during stress time. We also expressed the mathematical expressions for parts of the proposed model.

Online Condition Monitoring of Power MOSFET Gate Oxide Degradation Based on Miller Platform Voltage

The condition monitoring problem of power devices is significant for diagnostics and prognostics of a switched-mode power supply (SMPS) system. For power mosfet , the gate oxide degradation often occurs in various applications. However, there is no online condition monitoring method for gate oxide degradation so far. In this paper, a new precursor that can be used for online condition monitoring of power mosfet gate oxide degradation is proposed. Gate oxide degradation mechanisms and effect are summarized, and the mosfet turn-on process is analyzed. Then, a theoretical model is established to describe the relationship between miller platform voltage and two types of gate oxide defects, and miller platform voltage is identified as a new precursor. The precursor can be extracted without impacting system operation, thus online condition monitoring can be accomplished. The accelerated degradation test is carried out for power mosfet s with both high electric field and gamma irradiation methods, and the degraded devices injection and in situ monitoring of miller platform voltage are conducted on a BOOST circuit to verify the feasibility of the new precursor. Experimental results demonstrate that the new precursor can be applied to online condition monitoring of power mosfet gate oxide degradation in the SMPS system.

Single-trap analysis of hot-carrier-induced gate oxide degradation in Flash memory cells

Using a test structure containing two memory cells with a shared floating gate (FG), we analyzed the processes of hot-electron-induced charge trapping in the FG oxide with a single-trap resolution. Unlike the traditional RTN-based method for single-trap study, the proposed approach allows one to detect not only the interface traps showing capture-emission events in the time domain, but also to resolve virtually all individual trapping-detrapping events in the floating gate oxide during the program-erase cycling.

(Dielectric Science and Technology Division Thomas D. Callinan Award Address) Dielectrics for MOS Integrated Circuits

Introduction Insulator films are one of the fundamental elements of the semiconductor integrated circuits together with semiconductor substrate/films and metal/silicide interconnects. Functions of the insulator films in ICs (Integrated Circuits) are roughly classified into the following 6 categories; a) isolation between active devices, b) gate insulator of MOSFETs/MOS capacitors/MIM (Metal Insulator Metal) capacitors, c) sidewall insulation films for gate electrode, d) interlayer isolation films for interconnects, e) passivation films above the interconnects to cover and protect the IC chip surface, and f) insulator film between surface Si layer and Si substrate in SOI (Silicon On Insulator) wafer. In this paper, author’s past works related to the insulator films used ICs are reviewed. Introduction of BPSG reflow technique into NMOS LSI technology One of the severe problems for ICs until the middle of 1970’s was the disconnection of the aluminum interconnects at the steps of insulation film over the edges of poly Si lines and field SiO2 regions. The author applied BPSG (BoroPhospho Silicate Glass) reflow technique for the first time in the world to his developed NMOS LSI technologies in Toshiba, making the steps completely smooth, verifying the yield, and long term reliability in the 1k bit SRAM products in 1975. Finding of plasma induced damage to the gate oxide during ion-implantation and reactive ion etching The author developed a 64k bit DRAM technology from late 1970’s to the beginning of 1980’s. The introduction of source/drain heavy ion-implantation and RIE (Reactive Ion Etching) techniques of poly Si gate electrodes (2nd poly Si) were necessary to fabricate the designed small cell size. The accumulated ionic charge to the capacitor poly electrodes (1st poly Si) during the ion-implantation and reactive ion etching broke the 3 nm gate oxide of the 1st poly Si capacitor, causing bit errors of DRAM. This phenomena were published at the late news of ECS for the first time in the world in 1982 (1). Introduction of RTN gate oxide to prevent the boron penetration In early 1990’s CMOS technology changed from that of single n+-poly Si gate to dual poly Si gate (n+-poly Si for NMOSFETs and p+-poly Si for PMOSFETs) technology, in order to suppress the short-channel effect of PMOSFETs. Because the boron diffusion through the gate SiO2 during the high temperature thermal process is very large, the high-concentration boron penetration from the p+-poly Si to the PMOSFET channel through the gate SiO2 became a big problem. This was known to be solved by introduction of nitrogen to the SiO2. The author and his colleagues demonstrated that the RTN (Rapid Thermally Nitrided) SiO2 gate film completely suppress the boron penetration even the nitrogen concentration in SiO2 is only several percent, for the first time in 1990 (2). Introduction of direct-tunneling gate oxide for CMOS logic device It has been assumed that the gate oxide thinning limit would be 3 nm, because of the significant increase of the gate leakage current by direct-tunneling mechanism. However, the author and his colleagues demonstrated that MOSFETs with 1.5 nm thick direct-tunneling gate oxide operate quite normally, even though there is the direct-tunneling leakage, when decreasing the gate length less than 0.1 um, because the ratio between the gate leakage current and the drain current deceases in proportion to the square of the gate length reduction rate (3). Demonstration of the 0.4 nm EOT La-silicate gate oxide MOSFETs In order to decrease the gate length of MOSFETs to 5 nm, EOT (Equivalent Oxide Thickness) of the gate oxide should be 0.4 nm. The author and his colleagues developed La-silicate high-k metal gate technology and demonstrated the excellent operation of 0.4 nm EOT MOSFETs (4). Reference S. Sawada, S. Maeda, Y. Matsumoto, H. Iwai, H. Nihira, and O. Ozawa, “Degradation of thin gate oxide under process induced electrical stress”, 162nd ECS Fall Meeting, Recent Newspapers, Detroit, USA, October, (1982).T. Morimoto, H. S. Momose, K. Yamabe, and H. Iwai, “Prevention of boron penetration from p+ poly gate by RTP produced thin gate oxide”, ESSDERC 90, Nottingham, England, September, (1990), 73.H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, H. Iwai, “Tunneling gate oxide approach to ultra-high current drive in small-geometry MOSFETs”, in IEDM Tech. Dig., December, (1994), 593H. Iwai, T. Yasuda et al., “Research and development for second generation of ultra-thin gate insulator material”, NEDO Forum 2012 on energy saving technology, Tokyo, November, (2012): in Japanese

Aging Precursor Identification and Lifetime Estimation for Thermally Aged Discrete Package Silicon Power Switches

Thermal/power cycles are widely acknowledged methods to accelerate the package related failures. Many studies have focused on one particular aging precursor at a time and continuously monitored it using custom-built circuits. Due to the difficulties in taking sensitive measurements, the reported findings are more on the quantities requiring less sensitive measurements. In this paper, two custom-designed testbeds are used to age a number of power MOSFETs and insulated gate bipolar transistors. An automated curve tracer is utilized to capture parametric variations in I-V curves, parasitic capacitances, and gate charges at certain time intervals. The results suggest that the only viable aging precursors are the on-state voltage drop/on-state resistance, body diode voltage drop, parasitic capacitances, and gate threshold voltage for die attach solder and gate-oxide degradation mechanisms. Based on the experimental results, gate threshold voltage variation is empirically modeled to estimate the remaining useful lifetime of the switches experiencing gate oxide degradation. The model parameters are found by the least squares method applied to inliers determined by the random sample and consensus outlier removal algorithm.

Investigations on the Degradation of 1.2-kV 4H-SiC MOSFETs Under Repetitive Short-Circuit Tests

The long-term operational reliability of silicon carbide (SiC) MOSFETs needs to be further verified before they could replace silicon counterparts in power applications. In this paper, the failure mechanism of commercial 1.2-kV SiC MOFSETs under repetitive short-circuit (SC) tests has been investigated. Relatively low stress defined as low bias voltage and short SC duration is imposed on the devices, eliminating the effect of gate oxide degradation and metal deterioration. The generation of hot holes in the oxide is confirmed by the charge pumping experiments and measurements on the transfer characteristics of the stressed devices during the tests. Electrothermal simulation results demonstrate that the trapped holes are located above the channel region due to the high local impact ionization generation rate and electric field. Besides, the additional positive electric field to the channel makes $V_{\mathrm {th}}$ decrease and $I_{\mathrm {dss}}$ increase, which are consistent with the experimental results. What is more, the trapped holes get indeed released, as the ambient temperature increases when the stress is removed.

Gate oxide degradation of SiC MOSFET under short-circuit aging tests

SiC MOSFETs reliability issues remain a challenge that requires further investigation. In this article, a short-circuit aging test was developed to characterize the electrical parameter evolution. The threshold voltage and gate drain capacitance seem to be relevant degradation indicators. These two parameters indicate a gate oxide degradation. Electron trapping in the oxide layer could be the mechanism behind this deterioration.

Swift heavy ion irradiation induced electrical degradation in deca-nanometer MOSFETs

In this work, degradation of the electrical characteristics of 65nm nMOSFETs under swift heavy ion irradiation is investigated. It was found that a heavy ion can generate a localized region of physical damage (ion latent track) in the gate oxide. This is the likely cause for the increased gate leakage current and soft breakdown (SBD) then hard breakdown (HBD) of the gate oxide. Except in the case of HBD, the devices retain their functionality but with degraded transconductance. The degraded gate oxide exhibits early breakdown behavior compatible with the model of defect generation and percolation path formation in the percolation model.

A concise study of neutron irradiation effects on power MOSFETs and IGBTs

Over the past years there have been growing concerns on the adverse effects of atmospheric neutrons on power semiconductors even at sea level. In this paper we report recent results of neutron irradiation (1.9MeV) experiments conducted on 650V Super-Junction MOSFETs and Field-Stop Trench Insulated Gate Bipolar Transistors (IGBTs). The typical experiments found in literature which study the irradiation of power electronics chose a white line spectrum of neutron energies, ranging from 1 to 180MeV; however, we have deliberately chosen to study the effect of monochromatic radiation of fast neutrons, as a first in a series of experiments, to better understand the full range of interactions from fast to ultra fast neutrons (100MeV). We show that a multitude of failure modes already appear at neutron energies of 1.9MeV ranging from gate oxide degradation to single event effects (SEE). Moreover an outstanding ruggedness of devices is demonstrated, which shows no failures at 80% rated break down and below under extreme aging conditions.

A Structural Based Thermal Model Description for Vertical SiC Power MOSFETs under Fault Conditions

The accurate prediction of the SiC MOSFET withstanding time for single fault events greatly influences the requirements for device protection circuits for these devices in power converter applications, like voltage source inverters or power electronic transformers. For this reason, a thermal model, based on the structural design and the physical dimensions of the chip as well as material properties of 4H-SiC, is proposed. This article gives a general description of the thermal behaviour of vertical SiC MOSFET under various driving and boundary conditions in case of a short-circuit event. The thermal model substitutes destructive tests of a device for an individual set of boundary conditions of an occurring fault event. The validity of the analytically parametrised thermal model is verified by experimental short-circuit tests of state-of-the-art vertical SiC MOSFETs for a set of various boundary conditions. The investigated thermal model can furthermore be used to standardise different gate-oxide degradation values from the literature for means of lifetime prediction of the gate oxide for an individual application under repetitive occurring fault or overload conditions. These manufacturer specific reported values measured with no standardised testing procedures can be translated into a maximum junction temperature, which is repeatedly reached. The thermal model therefore provides a unifying parameter for the gate-oxide lifetime calculation for an individual chip and application.

(Invited) Metallic Contamination Control in Advanced ULSI Processing

As semiconductor devices continue to shrink, metallic contamination on silicon surfaces become to have a detrimental impact on ULSI device performance and yield. Surface metal impurities degrade gate oxide integrity [1] and cause the whisker growth in film deposition [2] and the crystal defect growth on a photomask for 193nm exposure [3], while metal impurities dissolved in silicon cause recombination centers and result in junction leakage [4] and cause dark current in image sensors [5]. In this article, we have extensively reviewed metallic contamination control including the analysis, prevention, removal, and gettering in advanced ULSI manufacturing. Trace metal contamination on the silicon surfaces can be detected with VPD- or LPD TXRF, AAS, and ICP-MS and these methods have been widely used. These analyses provide average concentration on the whole wafer surface and even direct TXRF provide average concentration on the 10 mm diameter area. However, metal impurities accidentally deposited in wafer processing such as reactive ion etching are localized [6]. Therefore, the methods to easily detect localized metal atoms are required. When III-V compound semiconductor materials are introduced for high mobility channels, the detection sensitivity on the III-V semiconductor surface by TXRF and the metal collection efficiency become critical issues [7]. Changing chemistry for the cleaning of the III-V surface will be inevitable [8]. As wafer diameter becomes larger and gate dielectric thickness become smaller, single-wafer cleaning have become popular. The single-wafer cleaning can prevent re-deposition of metals and use ozone-based liquid or dilute chemistries. In order to control metal impurities in silicon, understanding of the penetration and diffusion behaviors and efficient gettering are necessary. Surface metals penetrate silicon even through SiO2 or Si3N4 films by the collision of the surface metals and dopant atoms during ion implantation and subsequent annealing [9]. The amount of metals penetrating the silicon substrate depends on metal species and the oxide thickness. W is more difficult to penetrate the SiO2 film than Fe, Cr, Ni and Cu. The penetration of metals with a low diffusion coefficient in SiO2 such as W can be controlled by varying the SiO2 thickness. On the other hand, fast diffusers such as Fe and Cu cannot be always reduced by an increase in the SiO2 thickness. It is remarkable that Cr and W metals penetrate the silicon substrate through the Si3N4 film more easily than through the thermally-grown SiO2 [9]. This phenomenon can be explained by the ab-initio calculations of the diffusion barriers of metals in high temperature cristobalite SiO2 and β-Si3N4. These metals on Si3N4 films must be strictly controlled before ion implantation. Metals penetrating silicon generate deep levels in silicon. The depth profiles of the metal-induced deep level depend on metal species. We have demonstrated the deep level, capture cross-section, and the depth profile of thermally-diffused W in silicon [10]. In-wafer distribution of recombination centers can be detected with high sensitivity and visualized with μ-PCD and photoluminescence. The distributions of surface metal concentration measured with TXRF before ion implantation are in good agreement with that of recombination lifetime after ion implantation followed by annealing. The low level surface Fe and Ni contamination as little as 2 × 1011 atoms/cm2 can generate recombination centers even when dopants were implanted through even 20-nm-thick SiO2 [9]. Gettering is effective to mitigate the influence of metal impurities on device characteristics. Transition metals are trapped at the high-dose boron or phosphorous implanted region and the dislocation loops in low-energy ion implanted silicon [11]. The oxygen-containing dislocation loops generated by phosphorous ion implantation can be gettering sites for Fe and Cr, while high concentration of phosphorous and/or vacancies will chemically bond with Cu and Ni. Gettering design based on physical properties of metal species must be necessary. Reference [1] P. S. D. Lin, J. Electrochem. Soc., 131, 1878 (1983). [2] G. M. Choi, ECS transactions, vol. 11, no. 2, p.133. [3] K. Saga, et.al, Proc. of SPIE, 6730-44 (2007). [4] T. Kuroi, et. al, Tech. Digest of SSDM ’92 (1992). [5] W. C. McColgin, et.al, Mat. Res. Soc. Symp., Proc. Vol. 262, 1992 Material Research Society. [6] T. Tomita, et. al, ECS proceeding volume, PV 98-13. [7] H .Fontaine, T. Lardin, ECS transactions,58 (6) 327-335 (2013). [8] D. H. van Dorp, et. al, Solid State Phenomena Vol. 219 (2015) pp 56-58 [9] K. Saga, et.al, ECS Journal of Solid State Science and Technology, 4 (5) P131-P136 (2015). [10] E. Simoen, K. Saga, J. Lauwaerta, and H. Vrielincka, ECS Transactions, 64 (11) 219-228 (2014). [11] K. Saga, Solid State Phenomena Vol. 187 (2012) 283-286

Defect generation and activation processes in HfO2thin films: Contributions to stress-induced leakage currents

An important source of degradation in thin dielectric material layers is the generation and migration of oxygen vacancies. We investigated the formation of Frenkel pairs (FPs) in HfO2 as the first structural step for the creation of new defects as well as the migration of preexisting and newly built oxygen vacancies by nudged elastic band (NEB) calculations and stress induced leakage current (SILC) experiments. The analysis indicates, that for neutral systems no stable intimate FPs are built, whereas for the charge states q = ± 2 FPs are formed at threefold and at fourfold coordinated oxygen lattice sites. Their generation and annihilation rate are in equilibrium according to the Boltzmann statistics. Distant FPs (stable defects) are unlikely to build due to high formation energies and therefore cannot be accounted for the measured gate leakage current increase of nMOSFETs under constant voltage stress. The negatively charged oxygen vacancies were found to be very immobile in contrast to positively charged V0's with a low migration barrier that coincides well with the experimentally obtained activation energy. We show that rather the activation of preexisting defects and migration towards the interface than the defect generation are the cause for the gate oxide degradation.