Wafer Defect Research Articles

Optimized YOLOv8 based on SGW for surface defect detection of silicon wafer

Abstract Wafer detection is a critical procedure in IC manufacturing. Deep learning models are extensively used to identify the wafer defects. The key issue is how to recognize the small defects in complex backgrounds reducing the probability of misjudge and enhancing the detection accuracy. To solve the problems, we proposed a new detection model, SGW-YOLOv8 (SimAM-GhostConv-Wise IOU), based on the YOLOv8 model. The SimAM attention mechanism was added to enhance the network's focus on important positions without increase of the parameter numbers. The GhostConv improved the backbone network, and the Wise-IOU (Weighted Intersection over Union) loss function was introduced to address the deviation of evaluation results caused by the traditional loss function. Moreover, an additional detection head was appended to YOLOv8 to improve the model's capability of recognizing small targets. The dataset containing six types of defects was established by generating 6000 images of silicon wafers. The experimental results demonstrated that the mAP@0.5 of SGW-YOLOv8 increased by 4.8% compared to YOLOv8, and the model parameters are decreased by 11.8%. Therefore, the proposed SGW-YOLOv8 model is potential for wafer detection in IC industry.

Semiconductor Wafer Defect Detection Based on Machine Learning

Semiconductor wafers are widely used in integrated circuit chips. Because of the complex production process, it is easy to cause various defects. Therefore, the defect detection of semiconductor wafers is an important means to ensure their yield and productivity. This paper mainly expounds on the detection method of wafer defects combined with the machine vision algorithm, including the CNN model, and the classification of the learning-based methods. Current problems and future prospects for total crystalline circle defect detection are discussed in the end.

Elevating Wafer Defect Inspection with Denoising Diffusion Probabilistic Model

Elevating Wafer Defect Inspection with Denoising Diffusion Probabilistic Model

Polarized Light Observation for Visualization of Crystalline Defects in SiC Wafers for Power Device Applications

Polarized Light Observation for Visualization of Crystalline Defects in SiC Wafers for Power Device Applications

Dislocation evolution in anisotropic deformation of GaN under nanoindentation

The exceptional performance of GaN semiconductors in lasers, wireless communication, and energy storage systems makes them crucial for future multi-functional devices. However, during the polishing of GaN wafers, abrasive particles can induce subsurface damage, compromising device performance. This study investigates dislocation loops in GaN single crystal to understand dislocation nucleation and glide under external stress. Using nanoindentation for compressive stress, we confirmed multiple slip system activation via transmission electron microscopy after pop-in. We also performed molecular dynamics to simulate the nucleation and multiplication of U-shaped dislocation loops. Furthermore, we developed a theoretical model using Peierls–Nabarro stress to quantify GaN's critical shear stress. Raman spectroscopy was also used to analyze shear stress on U-shaped loops, supporting our model. This study provides insights into GaN dislocation dynamics under mechanical stress, aiding in wafer defect evaluation during machining and offering guidance for dislocation evolution.

Wafer defect pattern recognition based on differentiable architecture search with dual attention module

Wafer defect pattern recognition based on differentiable architecture search with dual attention module

A Self-Training-Based System for Die Defect Classification

With increasing wafer sizes and diversifying die patterns, automated optical inspection (AOI) is progressively replacing traditional visual inspection (VI) for wafer defect detection. Yet, the defect classification efficacy of current AOI systems in our case company is not optimal. This limitation is due to the algorithms’ reliance on expertly designed features, reducing adaptability across various product models. Additionally, the limited time available for operators to annotate defect samples restricts learning potential. Our study introduces a novel hybrid self-training algorithm, leveraging semi-supervised learning that integrates pseudo-labeling, noisy student, curriculum labeling, and the Taguchi method. This approach enables classifiers to autonomously integrate information from unlabeled data, bypassing the need for feature extraction, even with scarcely labeled data. Our experiments on a small-scale set show that with 25% and 50% labeled data, the method achieves over 92% accuracy. Remarkably, with only 10% labeled data, our hybrid method surpasses the supervised DenseNet classifier by over 20%, achieving more than 82% accuracy. On a large-scale set, the hybrid method consistently outperforms other approaches, achieving up to 88.75%, 86.31%, and 83.61% accuracy with 50%, 25%, and 10% labeled data. Further experiments confirm our method’s consistent superiority, highlighting its potential for high classification accuracy in limited-data scenarios.

Enhancing wafer defect detection via ensemble learning

Enhancing wafer defect detection via ensemble learning

Efficient Mixed-Type Wafer Defect Pattern Recognition Based on Light-Weight Neural Network.

Wafer defect pattern recognition can help engineers improve the production process of semiconductor chips. In real industrial scenarios, the recognition of mixed-type wafer defects is difficult and the production scale of semiconductor wafers is large, which requires high accuracy and speed in wafer defect pattern recognition. This study proposes a light-weight neural network model to efficiently recognize mixed-type wafer defects. The proposed model is constructed via inverted residual convolution blocks with attention mechanisms and large kernel convolution downsampling layers. The inference speed of the inverted residual convolution block is fast, and the attention mechanism can enhance feature extraction capabilities. Large kernel convolutions help the network retain more important feature information during downsampling operations. The experimental results on the real Mixed-type WM38 dataset show that the proposed model achieves a recognition accuracy of 98.69% with only 1.01 M parameters. Compared with some popular high-performance models and light-weight models, our model has advantages in both recognition accuracy and inference speed. Finally, we deploy the model as a TensorRT engine, which significantly improves the inference speed of the model, enabling it to process more than 1300 wafer maps per second.

Chip-Level Defect Analysis with Virtual Bad Wafers Based on Huge Big Data Handling for Semiconductor Production

Semiconductors continue to shrink in die size because of benefits like cost savings, lower power consumption, and improved performance. However, this reduction leads to more defects due to increased inter-cell interference. Among the various defect types, customer-found defects are the most costly. Thus, finding the root cause of customer-found defects has become crucial to the quality of semiconductors. Traditional methods involve analyzing the pathways of many low-yield wafers. Yet, because of the extremely limited number of customer-found defects, obtaining significant results is difficult. After the products are provided to customers, they undergo rigorous testing and selection, leading to a very low defect rate. However, since the timing of defect occurrence varies depending on the environment in which the product is used, the quantity of defective samples is often quite small. Unfortunately, with such a low number of samples, typically 10 or fewer, it becomes impossible to investigate the root cause of wafer-level defects using conventional methods. This paper introduces a novel approach to finding the root cause of these rare defective chips for the first time in the semiconductor industry. Defective wafers are identified using rare customer-found chips and chip-level EDS (Electrical Die Sorting) data, and these newly identified defective wafers are termed vBADs (virtual bad wafers). The performance of root cause analysis is dramatically improved with vBADs. However, the chip-level analysis presented here demands substantial computing power. Therefore, MPP (Massive Parallel Processing) architecture is implemented and optimized to handle large volumes of chip-level data within a large architecture infrastructure that can manage big data. This allows for a chip-level defect analysis system that can recommend the relevant EDS test and identify the root cause in real time even with a single defective chip. The experimental results demonstrate that the proposed root cause search can reveal the hidden cause of a single defective chip by amplifying it with 90 vBADs, and system performance improves by a factor of 61.

Influence of Growth Process on Suppression of Surface Morphological Defects in 4H-SiC Homoepitaxial Layers.

To address surface morphological defects that have a destructive effect on the epitaxial wafer from the aspect of 4H-SiC epitaxial growth, this study thoroughly examined many key factors that affect the density of defects in 4H-SiC epitaxial wafer, including the ratio of carbon to silicon, growth time, application of a buffer layer, hydrogen etching and other process parameters. Through systematic experimental verification and data analysis, it was verified that when the carbon-silicon ratio was accurately controlled at 0.72, the density of defects in the epitaxial wafer was the lowest, and its surface flatness showed the best state. In addition, it was found that the growth of the buffer layer under specific conditions could effectively reduce defects, especially surface morphology defects. This provides a new idea and method for improving the surface quality of epitaxial wafers. At the same time, we also studied the influence of hydrogen etching on the quality of epitaxial wafers. The experimental results show that proper hydrogen etching can optimize surface quality, but excessive etching may lead to the exposure of substrate defects. Therefore, it is necessary to carefully control the conditions of hydrogen etching in practical applications to avoid adverse effects. These findings have important guiding significance for optimizing the quality of epitaxial wafers.

A new ViT-Based augmentation framework for wafer map defect classification to enhance the resilience of semiconductor supply chains

Wafer map defect classification plays a crucial role in sustaining the semiconductor supply chain during industrial disruptions by ensuring continuity, resilience, and efficiency while aligning with sustainability principles. Up to 30 percent of production costs is lost to chip testing and yield losses for semiconductor manufacturing supply chain. In the semiconductor practice, wafer map defects recognition plays a linchpin role in the front-end-of-line stage. Defect pattern recognition can directly pinpoint the assignable causes and provide the domain experts with actionable insights. However, various wafer defect types occur differently from each other, which makes the collected wafer map dataset to be highly imbalanced in defect classes. In the face of data imbalance, the classification model usually cannot provide satisfactory classification performance. In this aspect, this paper intends to investigate the wafer defect map classification problem by using Vision Transformer (ViT) as an alternative data augmentation approach. The primary purpose is to alleviate the class-imbalance issue and then the performance of a deep learning-based convolutional neural network for wafer defect classification can be effectively improved. The experimental results demonstrate that the proposed data augmentation method by using ViT proves to be a potential generative model for improving wafer map defect classification, particularly robust on the individual minority class. In a word, the proposed augmentation framework for wafer map defect classification facilitates a more targeted and efficient approach to quality control, resource utilization, and production optimization in maintaining a sustainable semiconductor supply chain, particularly in times of industrial disruption.

Sample-imbalanced wafer map defects classification based on auxiliary classifier denoising diffusion probability model

This paper research on the classification task of wafer map defects under imbalanced sample. To improve the number of imbalanced wafer maps, a denoising diffusion probabilistic model with auxiliary classifier is proposed to generate new wafer maps. The developed model has an U-net structure with multiple inputs and outputs, taking wafer images, noise degree and category features as inputs, and outputs predicted noise and prediction category. When performing data augmentation, the trained model gradually removes prediction noise from the initial random noise and obtains new wafers. Finally, the balanced wafer defect maps are classified using a residual neural network. The proposed auxiliary classifier denoising diffusion probabilistic model and residual neural networks (ACDDPM-ResNet) method has validated on the MIR-WM811K dataset and MixedWM38 dataset, and the defect classification results of the imbalanced wafer map are remarkable improved after data augmentation. In addition, the paper also discusses and analyzes the influence of the maximum noise addition steps and the data augmentation size on the accuracy of wafer classification. It is further validated that the proposed wafer map classification method based on data augmentation can solve the classification problem caused by sample imbalance.

Hybrid Semiconductor Wafer Inspection Framework via Autonomous Data Annotation

Abstract In smart manufacturing, semiconductors play an indispensable role in collecting, processing, and analyzing data, ultimately enabling more agile and productive operations. Given the foundational importance of wafers, the purity of a wafer is essential to maintain the integrity of the overall semiconductor fabrication. This study proposes a novel automated visual inspection (AVI) framework for scrutinizing semiconductor wafers from scratch, capable of identifying defective wafers and pinpointing the location of defects through autonomous data annotation. Initially, this proposed methodology leveraged a texture analysis method known as gray-level co-occurrence matrix (GLCM) that categorized wafer images—captured via a stroboscopic imaging system—into distinct scenarios for high- and low-resolution wafer images. GLCM approaches further allowed for a complete separation of low-resolution wafer images into defective and normal wafer images, as well as the extraction of defect images from defective low-resolution wafer images, which were used for training a convolutional neural network (CNN) model. Consequently, the CNN model excelled in localizing defects on defective low-resolution wafer images, achieving an F1 score—the harmonic mean of precision and recall metrics—exceeding 90.1%. In high-resolution wafer images, a background subtraction technique represented defects as clusters of white points. The quantity of these white points determined the defectiveness and pinpointed locations of defects on high-resolution wafer images. Lastly, the CNN implementation further enhanced performance, robustness, and consistency irrespective of variations in the ratio of white point clusters. This technique demonstrated accuracy in localizing defects on high-resolution wafer images, yielding an F1 score greater than 99.3%.

Spot scanning imaging calibration method based on deviation model for wafer inspection

The spot scanning defect detection system has good detection performance for wafer defects. However, due to the existence of system assembly errors, the wafer defect inspection system could not scan following the planned trace, which resulted in distortion of the reconstructed image and had a greater impact on defect feature extraction and accurate defect location. The system deviation calibration and adjustment can further facilitate the accuracy of the system position and image reconstruction. To address this issue, the causes and shapes of imaging distortion were analyzed and simulated, and a simple and effective calibration method based on a scanning deviation model for the spot scanning defect detection system was proposed. First, a scanning deviation model was established following the characteristics of the spot scanning system, and different degrees of reconstructed image distortion were simulated and analyzed as the system deviation changes. Then, an 8-inch wafer with a grid was used as the calibrator and scanned using the developed spot scanning system. Serveral grid corners in the reconstructed image are selected and used as the calibration feature points. The constraint function is constructed using the equidistant features between adjacent grid points, and then the quasi-Newton method is used to optimize the parameters of the function to obtain the best deviation estimation of the spot scanning system. To prove the validity of the estimated deviation parameters, another patterned wafer was scanned and the distortion image was used for reconstruction. The experiment demonstrated that an accurate and distortion-free wafer image can be reconstructed using the calibrated deviation parameters, and the root mean square error of the measured distance between two points of interest was only 0.61 pixels, which proved the effectiveness of the proposed calibration method.

Low complex CNN for semiconductor wafer defect detection

Fabrication of semiconductor wafers is a complex process and chances of defect wafers are high. Because of defective wafers the circuit patterns will not be created correctly and it is necessary to identify them. Manual identification of defects are time consuming and expensive. Deep learning methods are widely used for defect detection. In this paper we propose a simple Convolutional Neural Network (CNN) model for classification of nine defects in wafers. A custom CNN consisting of 9 layers is used for the classification of defects as Center, Donut, Edge-Loc, Edge-Ring, Loc, Random, Scratch, Near-full, and None. Performance of the model is evaluated using WM-811K dataset. Results shows that the model classifies the defects with high confidence score and an accuracy of 99.1% is achieved using this method. Further, the convolution operation in the CNN is realized using Coordinate Rotation Digital Computer (CORDIC) algorithm. The model is implemented in Field Programmable Gate Arrays (FPGA) and proved less complex method and consume less computational power than conventional methods.

Progressive Hierarchical Deep Reinforcement Learning for defect wafer test

Wafer testing plays a critical role in the wafer fabrication process. It involves using a probe to inspect all the wafers on a map, which presents a Coverage Path Planning (CPP) problem. Deep Reinforcement Learning (DRL) has emerged as a state-of-the-art (SOTA) solution for automating regular wafer testing. However, in the presence of production defects, the wafer maps become irregular, requiring more advanced probe strategies. Unfortunately, SOTA DRL methods cannot be directly applied to defect wafer testing due to high computational complexity, low sample efficiency, and limited transferability between tasks. To address these challenges, we propose a novel DRL solution called the Progressive Hierarchical DRL method for automated defect wafer testing. Specifically, our method utilizes a Visual Memory Attention Model (VMAM) to create a high-level strategy, referred to as a manager, which generates a goal specifying the most crucial image region for the task. Subsequently, a low-level strategy, referred to as a worker, generates precise cruising actions to navigate to the designated area. Additionally, we employ transfer learning to generalize the method to handle more complex defect wafer maps. Our approach outperforms seven SOTA DRL baselines in the domains of CPP and wafer testing. It achieves significant improvements in task duration and wafer visit overlap, ranging from 6.0% to 30.5%. Furthermore, we explore the application of our method to a dual-probe defect wafer testing system.

Auto-Labeling for Pattern Recognition of Wafer Defect Maps in Semiconductor Manufacturing

Abstract In practical semiconductor processes, the defect analysis for wafer map is a critical step for improving product quality and yield. These defect patterns can provide important process information so that the process engineers can identify the key cause of process anomalies. However, in supervised learning, the manual annotation for wafer maps is an extremely exhausting task, and it can also induce misjudgment when a long-term operation is implemented. Toward this end, this paper proposes a new auto-labeling system based on ensemble classification. The noted VGG16 model is used in ensemble learning as the building block to train the classifier via a limited number of labeled data. Through the model being trained, the auto-labeling procedure is executed to annotate abundant unlabeled data. Therefore, the classification performances between the models trained by supervised and semi-supervised learning can be compared. In addition, the gradient-weighted class activation mapping (Grad-CAM) is also adopted to analyze and verify the quality of auto-labeling by visual inspection. Based on the experimental results, the proposed auto-label system can return a satisfactory classification performance, and then, the manual labeling operation can be drastically reduced. The classification performance for wafer defect patterns can be further assured as the auto-labeled data are given with corresponding confidence scores of specific defect patterns being identified in this study.

Antecedent hash modality learning and representation for enhanced wafer map defect pattern recognition

In wafer map defect pattern recognition, deep learning methods are predominantly used. These models autonomously learn features without explicit human intervention due to their black-box type network architectures. While preceding feature extraction and modality representation may seem neglected in deep learning for wafer map defect pattern recognition, we addressed this question by proposing an innovative approach. Our proposed method employs an antecedent feature learning module to create a more compact and informative hash modality representation from input wafer maps. The method exceeds in achieving high recall, crucial for identifying actual defective wafers as much as possible in semiconductor manufacturing, where defects can impact integrated circuit functionality and reliability. Smaller-sized hash modalities against larger wafer maps allow the same model to speed up the process and require fewer computational resources.

Interpolation based Semi supervised Contrastive Learning for wafer defect pattern classification

Interpolation based Semi supervised Contrastive Learning for wafer defect pattern classification