Defects In Si Substrate Research Articles

Characterization of dynamic behaviors of defects in Si substrates created by H2 plasma using conductance method

Energetic ion bombardment during plasma etching processes creates latent defects which play a role as carrier trapping/de-trapping sites in materials. In this study, we investigated the latent defects in Si substrate created by H2 plasma exposure. In the case of light-mass ion such as H+, the created defects were difficult to detect by conventional capacitance-based methods. We found that a modified conductance method with an equivalent circuit considering the plasma-damaged layer can identify the latent defects created in Si substrates after H2 and He plasma exposures. The conductance method quantifies the areal defect densities and the characteristic time constant of carrier trapping/de-trapping processes. Then, the reconstruction of the damaged structures by a rapid thermal annealing (RTA) was evaluated. It was confirmed that the RTA changes the conductance of damaged structures in response to the annealing temperature and the total thermal budget. The obtained results suggest that the modified conductance method is an effective tool to quantify the dynamic behaviors of latent defects in Si substrates after H2 and He plasma exposures.

Investigation of spatial and energy profiles of plasma process-induced latent defects in Si substrate using capacitance–voltage characteristics

Spatial and energy profiles of latent defects in Si substrate created during plasma processes were investigated based on a model prediction framework using capacitance–voltage (C–V) characteristics in combination with experimental results. The C–V curves of metal–oxide–semiconductor (MOS) capacitor were simulated with respect to various spatial and energy profiles of the defects predicted by numerical simulations and experimental surface analyses reported so far. The distortions of C–V curves significantly depend on the defect profiles. As the peak density of defects locates at deeper levels in the Si bandgap, the characteristic hump appears in the depletion region of the C–V curve. The position of the hump moves as the energy profile changes against the depth. We compared the model predictions with experimental results for damaged devices after Ar plasma irradiation. We found the difference in the distortion of C–V curves after an inductively coupled plasma or a capacitively coupled plasma exposures, which implied that the energy profiles significantly depend on plasma conditions. We experimentally revealed that, for a certain plasma process condition, the major portion of defects locates at deep levels in the Si bandgap. The present prediction model is useful for an in-depth understanding the nature of defect creation and controlling plasma process-induced damage to future MOS devices.

An evaluation method of the profile of plasma-induced defects based on capacitance–voltage measurement

Aggressive shrinkage and geometrical transition to three-dimensional structures in metal–oxide–semiconductor field-effect transistors (MOSFETs) lead to potentially serious problems regarding plasma processing such as plasma-induced physical damage (PPD). For the precise control of material processing and future device designs, it is extremely important to clarify the depth and energy profiles of PPD. Conventional methods to estimate the PPD profile (e.g., wet etching) are time-consuming. In this study, we propose an advanced method using a simple capacitance–voltage (C–V) measurement. The method first assumes the depth and energy profiles of defects in Si substrates, and then optimizes the C–V curves. We applied this methodology to evaluate the defect generation in (100), (111), and (110) Si substrates. No orientation dependence was found regarding the surface-oxide layers, whereas a large number of defects was assigned in the case of (110). The damaged layer thickness and areal density were estimated. This method provides the highly sensitive PPD prediction indispensable for designing future low-damage plasma processes.

Observation of spatial distribution of vacancy defects in semiconductor by positron microscope and electron beam induced current measurement

A complementary study of vacancy defects in Si substrates by using scanning positron microscope (SPM) and electron beam induced current (EBIC) method were demonstrated for the same samples and in the same chamber. Both the S parameter and EBIC contrast were found to be enhanced in the regions containing vacancy defects introduced by ion implantation. That is, the SPM provides a criterion if the spatially resolved carrier recombination centres by the EBIC method are originating from vacancy defects or not.

Characteristics of Spontaneous Reaction Occurred by Metal Contamination and Silicon Substrate for Ultralarge-Scale Integration Semiconductor Process

Heavy metals such as Cu, Fe, and Ni are well known to cause defects in Si substrate and to degrade thin oxide quality in ultralarge-scale integration (ULSI) circuits. This degradation can seriously reduce yield and long-term reliability, which are the two critical factors in ULSI manufacturing. Metallic contamination originates in such process materials as gases and wet chemicals. As devices shrink, microcontamination is having an increasingly negative effect on operation function and yield. Semiconductor manufacturers can markedly increase wafer yield by reducing contamination. This work analyzes the contamination of processed wafers by heavy metals before the deposition of gate oxide. Many bamboo-shoot-like defects are present on the wafer edge. Additionally, many pits are also formed in the active region of a device when silicon substrate suffers from heavy metallic contamination. Transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS) are adopted to study the bamboo-shoot-like defects and pit defects. A possible mechanism was identified to explain the problem stage in manufacturing process. This work demonstrates the spontaneous dissolution of the contaminating metal in the silicon substrate. Tiny pits are becoming a serious problem in the manufacturing of submicrometer and deep-submicrometer ULSIs , which always suffer from yield loss at the wafer edge because of bamboo-shoot-like defects that are associated with design rule limitations. A detailed analysis and process flow check reveal that metal contamination generates tiny pits around the wafer edge in the raw material wafer process flow. These tiny pits result in bamboo-shoot-like defects in the non-o.d. (periphery) region and pits in the o.d. (active) region. These two defects cause failure of the device because of leakage. This work is the first to describe this issue regarding ULSI manufacturing and demonstrates that tiny pits represent high risk of device operation at the deep submicron level. An effective solution is to more strictly limit the degree of metallic contamination.

Improvement on the Electrical Characteristics of HfO[sub x]N[sub y]-Gated Metal-Oxide-Semiconductor Devices by High-Temperature Annealing

The electrical characteristics of HfO x N y -gated metal-oxide-semiconductor devices are significantly affected by the amount of defects in Si substrate. Devices with a low defect region near the Si surface were formed in this work using high-temperature annealing in a hydrogen ambient. Experimental results show longer minority carrier lifetime in silicon substrate, lower gate leakage current, and reduced interface trap density (D it ), which are attributable to the decrease in the interstitial oxygen (O i ) and crystal-originated-particle defects as well as better surface quality at HfO x N y /Si interface.

Advanced Ion Implantation Technology for High Performance Transistors

ABSTRACTCryo-implantation technology is proposed for reducing crystal defects in Si substrates. The substrate temperature was controlled to be below at -160°C during ion implantation. No dislocation was observed in the implanted layer after rapid thermal annealing. Pn junction leakage was successfully reduced by one order of magnitude as compared with room temperature implantation. Precise dose control is indispensable in channel region of high performance MOSFETs. In order to improve the precision of implanted dose, chip size implantation technology without photoresist mask was developed. In this technology, chip-by-chip implantation can be carried out by step-and-repeat wafer stage, and different implantation conditions are available in the same wafer independent of wafer size.

Silicide-Formation-Induced Defects in Si Substrates in Ti/Si and Ni/Si Systems by a Monoenergetic Positron Beam

The formation of silicides via the thin-film deposition of transition metals Ti and Ni onto Si substrates using a monoenergetic positron beam has been investigated. From the depth dependence of positron annihilation characteristics, the diffusion length of positrons was determined on the basis of a one-dimensional diffusion model. In the case of the Ti/Si system, the formation of the silicides did not induce shortening of the diffusion length of positrons in the Si substrate. On the contrary, the diffusion length of positrons in the resulting silicides was very short, indicating the presence of a great number of positron traps in silicides. The diffusion of Si atoms as a dominant diffusion species during TiSi2 formation could not be recognized in the present experiment. On the other hand, in the case of the Ni/Si system, the silicidation induced a very short diffusion length of positrons in the Si substrate. On the contrary, the diffusion length in the resulting silicide is long, to an extent comparable with that for defect-free metals. The diffusion of Si during NiSi2 formation was observed in the present experiment.