DC Offset Cancellation Circuit Research Articles

A direct-conversion WLAN transceiver baseband with DC offset compensation and carrier leakage reduction

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11a/b/g standards is described. Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications. The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing. The calibration loop achieves constant high-pass pole when gain changes; and a fast response time by programming the pole to 1 MHz during preamble and to 30 kHz during receiving data. The transmitter baseband employs an auto-calibration loop with on-chip AD and DA to suppress the carrier leakage, and AD can be powered down after calibration to save power consumption. The chip consumes 17.52 mA for RX baseband VGA and DCOC, and 8.3 mA for TX carrier leakage calibration (5.88 mA after calibration) from 2.85 V supply. Implemented in a 0.35 μm SiGe technology, they occupy 0.68 mm2 and 0.18 mm2 die size respectively.

A novel reconfigurable variable gain amplifier for a multi-mode multi-band receiver

This paper presents a novel approach for designing a reconfigurable variable gain amplifier (VGA) for the multi-mode multi-band receiver system RF front-end applications. The configuration, which is comprised of gain circuits, control circuit, DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing. The VGA is realized in 0.18 μm CMOS technology with 1.8 V power supply voltage providing a gain tuning range from 5 to 87 dB when the control voltage varies from 0 to 1.8 V. The 3 dB bandwidth is about 80 MHz for all levels of control voltage (all gains). Also, the DC offset cancellation circuit can effectively suppress DC offset to a value of less than 40 mV at the output regardless of the input. The overall power consumption is less than 3 mA, and die area is 705 × 100 μm2.

A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications

UHF RFID reader transceiver for Chinese local standard (840-845 MHz and 920-925 MHz), in concord with the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C, is presented. A highly linear RF front-end with low flicker noise, an on-chip self-jammer cancellation (SC) circuit with fast time-varying cut-off frequency and a DC-offset cancellation (DCOC) circuit are proposed to deal with the large self-jammer in the receiver. In the presence of 22 dBm PA output power, the receiver achieves a sensitivity of -79 dBm including the 15 dB loss of the directional coupler. A CMOS class-AB PA is integrated in the transmitter, with 22 dBm output power and 35% PAE. The spectrum mask achieves ACPR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> of -45 dBc and ACPR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> of -60 dBc . A sigma-delta fractional-N PLL with a single <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> VCO is also implemented for good phase noise (-126 dBc/Hz @ 1 MHz offset) and high frequency resolution within 1 kHz. This single-chip is fabricated in a 0.18 standard CMOS process. It occupies a silicon area of 13.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 203 mW from a 1.8 V supply voltage when transmitting 7.5 dBm output power.

Complex DC-offset cancellation circuit

A novel DC-offset cancellation circuit that is applicable to complex filters is presented. The proposed circuit allows for a high-gain complex filter, which leads to a small chip size and low current consumption. Adopting the proposed scheme, a 10 to 73 dB gain complex filter that cancels an input referred DC-offset by more than ±100 mV is designed based on 0.18 µm CMOS technology, which dissipates 2.4 mA from a 1.8 V supply.

A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader

This paper describes a single-antenna low-power single-chip radio frequency identification (RFID) reader for mobile phone applications. The reader integrates an RF transceiver, data converters, a digital baseband modem, an MPU, memory, and host interfaces. The direct conversion RF receiver architecture with the highly linear RF front-end circuit and DC offset cancellation circuit is used to give good immunity to the large transmitter leakage. It is suitable for a mobile phone reader with single-antenna architecture and low-power reader solution. The transmitter is implemented in the direct I/Q up-conversion architecture. The frequency synthesizer based on a fractional-N phase-locked-loop topology offering 900 MHz quadrature LO signals is also integrated with the RF transceiver. The reader is fabricated in a 0.18 mum CMOS technology, and its die size is 4.5 mm times 5.3 mm including electrostatic discharge I/O pads. The reader consumes a total current of 89 mA apart from the external power amplifier with 1.8 V supply voltage. It achieves an 8 dBm P1dB, an 18.5 dBm IIP3, and a maximum transmitter output power of 4 dBm.

Electrical Backplane Equalization Using Programmable Analog Zeros and Folded Active Inductors

In this paper, we present a low-power small-area electrical backplane equalizer using programmable analog zeros and folded active inductors. We also present a dc-offset cancellation circuit, which occupies less chip area than the traditional offset cancellation schemes. The equalizer circuit was fabricated in a 1.0-V 90-nm CMOS process. With one zero stage, the equalizer occupies 0.015-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area and dissipates 12 mW of power. At 4.25-Gb/s data rate, the equalizer provides 7.8-dB gain boost at the Nyquist frequency. Without the use of any transmitter equalization, the analog zero equalizer demonstrated error-free transmission for pseudorandom-bit-sequence-31 data patterns over 34-in lossy FR4 backplanes.

Analog VLSI Circuit Implementation of an Adaptive Neuromorphic Olfaction Chip

In this paper, we present the analog circuit design and implementation of the components of an adaptive neuromorphic olfaction chip. A chemical sensor array employing carbon black composite sensing materials with integrated signal processing circuitry forms the front end of the chip. The sensor signal processing circuitry includes a dc offset cancellation circuit to ameliorate loss of measurement range associated with chemical sensors. Drawing inspiration from biological olfactory systems, the analog circuits used to process signals from the on-chip odor sensors make use of temporal spiking signals to act as carriers of odor information. An on-chip spike time dependent learning circuit is integrated to dynamically adapt weights for odor detection and classification. All the component subsystems implemented on chip have been successfully tested in silicon

A Dual-Mode 2.4-GHz CMOS Transceiver for High-Rate Bluetooth Systems

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-on-chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on-chip filters. The chip is fabricated on a 6.5-mm2 die using a standard 0.25-μm CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of −5 dBm, and a sensitivity of −77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4-diffrential quadrature phase-shift keying (π/4-DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

A 450-Mb/s analog front end for PRML read channels

The high user densities and data rates supported by today's hard-disk drives (HDD) demand complex read channel ICs. High-performance analog front-end (AFE) circuits provide automatic gain control (AGC), programmable band limiting and pulse shaping prior to signal sampling and further processing of the data in the digital domain. A 450 Mb/s analog front-end, integrated into a 16/17 code rate EPR4 read channel, contains an AGC loop, which includes a programmable gain stage (PGA), an exponential variable-gain amplifier (VGA), a 7/sup th/-order 120 MHz lowpass filter (LPF), an active dc offset cancellation circuit, and digital feedback. Utilizing multilevel qualification and a variable loop time constant, the AGC acquires a 12 dB gain change within 5 data bytes. Thermal asperity (TA) and amplitude asymmetry compensation make the analog front-end ideally suited for magnetoresistive (MR) head-based applications. Implemented in 5V/3.3V dual voltage 0.35 /spl mu/ BiCMOS, the complete circuit occupies 2.29 mm/sup 3/ and dissipates 232 mW.