dBm Sensitivity Research Articles

Explainable Machine Learning for LoRaWAN Link Budget Analysis and Modeling

This article explores the convergence of artificial intelligence and its challenges for precise planning of LoRa networks. It examines machine learning algorithms in conjunction with empirically collected data to develop an effective propagation model for LoRaWAN. We propose decoupling feature extraction and regression analysis, which facilitates training data requirements. In our comparative analysis, decision-tree-based gradient boosting achieved the lowest root-mean-squared error of 5.53 dBm. Another advantage of this model is its interpretability, which is exploited to qualitatively observe the governing propagation mechanisms. This approach provides a unique opportunity to practically understand the dependence of signal strength on other variables. The analysis revealed a 1.5 dBm sensitivity improvement as the LoR’s spreading factor changed from 7 to 12. The impact of clutter was revealed to be highly non-linear, with high attenuations as clutter increased until a certain point, after which it became ineffective. The outcome of this work leads to a more accurate estimation and a better understanding of the LoRa’s propagation. Consequently, mitigating the challenges associated with large-scale and dense LoRaWAN deployments, enabling improved link budget analysis, interference management, quality of service, scalability, and energy efficiency of Internet of Things networks.

Periodic-threshold amalgamated quasi-one-junction SQUID comparator

This article proposes a periodic-threshold superconductive comparator named amalgamated quasi-one-junction SQUID comparator (AQOS) for sensitivity enhancement. The comparator employs a pair of compound Josephson-junction SQUID with magnetically-controlled effective critical current in quantization to relieve the constraints on the period current without disrupting the non-hysteresis operation state. As a result, the AQOS comparator can achieve three times more comparing operations than the quasi-one-junction SQUID (QOS) comparators, corresponding to a 9 dB sensitivity improvement. The AQOS comparator also adopts the complementary structure and feedback-free topology for linearity and robustness. It can reach a 30 GS/s sampling rate, 0.5 mA period current, −25 dBm sensitivity, more than ±10 % bias current margin, deviation of quantization current peak-to-peak magnitude that is about 10 % of the mean, and the 4.4 dB average DC duty bias margin in simulation from 1 GHz to 30 GHz with a process of 6 kA/cm2 Josephson critical current density. A 2-bit AQOS comparator has been fabricated with the SIMIT Nb03 process for the qualification test. It has passed functional tests at low frequency, and its performance metrics, including period current, sensitivity, and bias current margin, have also been proven.

A 112-Gb/s, -10 dBm Sensitivity, +5 dBm Overload, and SiPh-Based Receiver Frontend in 22-nm FDSOI

A 112-Gb/s, -10 dBm Sensitivity, +5 dBm Overload, and SiPh-Based Receiver Frontend in 22-nm FDSOI

A Wide Input Range All-NMOS Rectifier With Gate Voltage Boosting Technique for Wireless Power Transfer

This brief presents an all-NMOS RF-DC rectifier with a wide high power conversion efficiency (high-PCE) input power range by utilizing gate voltage boosting technique (GVBT). The all-NMOS architecture combines the benefits of crosscoupled and GVBT-based diode-like rectifiers for maximum electron mobility and reduced the conduction losses. The GVBT applied to rectifying transistors not only reduces the reverse leakage current, but also enhances the conductivity. As a result, the PCE and the input power range are improved simultaneously. The proposed rectifier is fabricated with a 0.18-lm standard CMOS technology. The measurement results show that the all-NMOS rectifier achieves 57.6% PCE, -14.8 dBm sensitivity and large than 20 dB high-PCE input power range with a 10 kΩ load.

An Energy Efficient Coherent IR-UWB Receiver With Non-Coherent-Assisted Synchronization

This paper presents a non-coherent assisted synchronization mechanism for low data rate coherent () receivers. A two-step coarse and fine acquisition mechanism is utilized to simplify the coherent synchronization and minimize the total required packet length. This hybrid scheme reduces the total power consumption of the receiver. The reception of a UWB packet begins with an energy efficient non-coherent synchronization portion in () modulation non-coherent acquisition. This reduces the search space for the coherent reception by first finding the best integration window that has the most energy of the received signal. Afterwards, the receiver searches coherently in () modulation within only the pre-selected integration window instead of the whole symbol time. Self-mixing and template-based correlation are utilized for the non-coherent and coherent reception, respectively. Most of the front-end blocks are shared between the coherent and non-coherent modes, including the LNA, mixer, and the baseband circuitry that follows to minimize the total power consumption of the receiver. A differential architecture including a (), a mixer, a fast start-up template generator, an integrator, and a differential comparator are utilized for the receiver front-end. A prototype of the proposed receiver operating from 3.5 to 5 GHz over four bands, each spaced by 500 MHz, is implemented in 65-nm CMOS technology. The proposed receiver architecture achieves a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 68 dBm, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 70.5 dBm, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 70.8 dBm sensitivity at a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-3}$</tex-math> </inline-formula> BER at 50 MHz () in the non-coherent, coherent, and proposed hybrid synchronization modes, respectively. The receiver consumes 6.8 mW and 8.8 mW in the non-coherent and coherent mode, respectively, when continuously ON. Using its novel synchronization mechanism, the receiver can reduce the ON time of the receiver by 68% and 34% in order to coherently synchronize and receive a 100-bit and 1024-bit payload, respectively. As a result, the () of the receiver is reduced by a factor of 2.9 from 1.24 nJ/b to 422 pJ/b for 100-bit payloads, and by a factor of 1.5 from 309 pJ/b to 204 pJ/b for 1024-bit payloads, increasing energy efficiency while maintaining the sensitivity benefits of coherent detection.

Fully Passive RF Wake-Up Receiver Including a Small Loop Antenna with -30.7 dBm Sensitivity at 26 kbps Bitrate

Fully Passive RF Wake-Up Receiver Including a Small Loop Antenna with -30.7 dBm Sensitivity at 26 kbps Bitrate

Dual-Band 802.11ax Transceiver Design With 1024-QAM and 160-MHz CBW Support

A 2W2 802.11ax transceiver design is presented to support dual band simultaneous operation (DBS) and 1024-QAM modulation. The proposed architecture features linearity enhancement for uplink OFDMA and wideband transmission. With integrated low phase noise clock generation and PLL, bestin-class receiving sensitivity and lowest transmission EVM floor are demonstrated through measurements. With 20MHz (HE20) receiving, -96.5dBm/-66dBm sensitivity level is measured for MSC0/11, respectively. The output power reaches 18dBm with -35dB EVM for 80MHz 1024-QAM (HE80 MCS11) transmission at 5GHz band. Narrowband OFDMA signals can be transmitted at full power capacity, and 160MHz channel bandwidth (CBW) can also be supported without digital predistortion (DPD). The fully integrated transceiver occupies 10.5 mm2 silicon area in 22nm CMOS.

Concurrent Multiband Direct RF Sampling Receivers

Direct radio frequency (RF) sampling receivers are investigated for use in concurrent multiband reception for mobile broadband (MBB) applications. The recent proliferation of different frequency bands and standards in wireless communications has allowed large increases in mobility and throughput, but the number of receivers in a device is limited by physical space and power consumption. Software Defined Radio (SDR) is increasingly being explored to reduce the number of analog RF components required. This paper examines the use of direct RF digitization, allowing tunable and concurrent reception of multiple bands with a single RF front-end. Full mathematical models of both Nyquist and subband sampling receivers are presented and used to investigate a quadband LTE receiver, which is modeled in Simulink and implemented in a hardware-in-the-loop (HWIL) testbed. Individual bands are simulated to have at worst -95dBm sensitivity for 16-QAM with Nyquist sampling and -83dBm with subband sampling. Desensitization of the receivers due to multiband processing is evaluated theoretically and experimentally, showing a maximum of 3dB degradation, which is within the LTE standard for adjacent band interference.

A Reconfigurable Hybrid RF Front-End Rectifier for Dynamic PCE Enhancement of Ambient RF Energy Harvesting Systems

This paper presents a reconfigurable hybrid Radio Frequency (RF) rectifier designed to efficiently convert AC RF power to DC voltages for an energy harvesting system. The proposed reconfigurable rectifier adopts the advantage of low conduction loss in the switch-connected rectifier and low reverse current loss in the diode-connection rectifier topology to enhance its power conversion efficiency (PCE). Capable of reconfiguring into different rectifier topologies, the proposed circuit can reconfigure into a switch-based cross-coupling differential drive (CCDD) at low input power and a diode-based hybrid rectifier at higher input power for a wide dynamic range operation. Designed and implemented on a CMOS 65 nm technology, the post-layout result records a peak PCE of 88.7% and a wide PCE dynamic range (PDR) of 16 dBm for PCE &gt;40%. The proposed circuit also demonstrates a −21 dBm sensitivity output across a 1 MΩ output load.

Chip-Level GHz Capable Balanced Quantum Homodyne Receivers

We present a design of balanced homodyne receivers suitable for ultra-low noise quantum applications such as continuous-variable quantum key distribution and quantum random number generation. For best noise and bandwidth performance a die-level low-parasitic photodiode together with a low-noise high-speed transimpedance amplifier are explored together with a planar lightwave circuit splitter chip serving as a photomixer. Bandwidths of 750 MHz and 2.6 GHz were accomplished while maintaining optimum noise performance, as evidenced by very high quantum-to-classical noise ratios of 26.8 and 18.6 dB, respectively. A common-mode rejection ratio of at least 40 dB was achieved for a frequency range of up to 1 GHz. Its application for continuous-variable quantum key distribution was evaluated by means of estimations under a strict untrusted receiver assumption, showing its potential for generating up to 43 Mbit/s secure-key rate over a reach of 10 km, whereas up to 100 Mbit/s could be supported at shorter reaches. Moreover, the high quantum-to-classical clearance values can enable high quality quantum random number generation at Gb/s rates. The multi-purpose operation of the designed balanced receivers for classical communications was examined showing reception sensitivities of −55.8 and −52.6 dBm at 500 Mbit/s and 1 Gbit/s quadrature phase shift keying transmission, respectively, using the 750 MHz receiver. The faster 2.6 GHz receiver enabled 10 Gbit/s duobinary transmission at −14.8 dBm sensitivity.

From Demodulation to Decoding: Toward Complete LoRa PHY Understanding and Implementation

LoRa, as a representative of Low Power Wide Area Network technology, has attracted significant attention from both academia and industry. However, the current understanding of LoRa is far from complete, and implementations have a large performance gap in SNR and packet reception rate. This article presents a comprehensive understanding of LoRa physical layer protocol (PHY) and reveals the fundamental reasons for the performance gap. We present the first full-stack LoRa PHY implementation with a provable performance guarantee. We enhance the demodulation to work under extremely low SNR (-20 dB) and analytically validate the performance, where many existing works require SNR &gt; 0. We derive the order and parameters of decoding operations, including dewhitening, error correction, deinterleaving, and so on, by leveraging LoRa features and packet manipulation. We implement a complete real-time LoRa on the GNU Radio platform and conduct extensive experiments. Our method can achieve (1) a 100% decoding success rate while existing methods can support at most 66.7%, (2) -142 dBm sensitivity, which is the limiting sensitivity of the commodity LoRa, and (3) a 3,600-m communication range in the urban area, even better than commodity LoRa under the same setting.

System-on-chip approach microwave imaging reflectometer on DIII-D tokamak.

System-on-chip millimeter wave integrated circuit technology is used on the two-dimensional millimeter-wave imaging reflectometer (MIR) upgrade for density fluctuation imaging on the DIII-D tokamak fusion plasma. Customized CMOS chips have been successfully developed for the transmitter module and receiver module array, covering the 55-75GHz working band. The transmitter module has the capability of simultaneously launching eight tunable probe frequencies (>0 dBm output power each). The receiver enclosure contains 12 receiver modules in two vertical lines. The quasi-optical local oscillator coupling of previous MIR systems has been replaced with an internal active frequency multiplier chain for improved local oscillator power delivery and flexible installation in a narrow space together with improved shielding against electromagnetic interference. The 55-75GHz low noise amplifier, used between the receiver antenna and the first-stage mixer, significantly improves module sensitivity and suppresses electronics noise. The receiver module has a 20 dB gain improvement compared with the mini-lens approach and better than -75 dBm sensitivity, and its electronics noise temperature has been reduced from 55000K down to 11200K. The V-band MIR system is developed for co-located multi-field investigation of MHD-scale fluctuations in the pedestal region with W-band electron cyclotron emission imaging on DIII-D tokamak.

A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant Wake-Up Receivers and Low-Noise Primary Receivers.

Wake-up receivers (WuRX) present an opportunity to reduce average power consumption of IoT transceivers, however achieving sensitivity and interferer tolerance while providing wideband matching and sharing an antenna interface present a significant challenge for existing architectures. This paper presents a primary/WuRX which utilizes a quadrature hybrid coupler based N-Path mixer first architecture to simultaneously achieve low noise, wideband matching and a shared antenna interface. The passive-mixer first approach and a two-code modulated multi-tone signaling scheme provide interferer tolerance in the WuRX. The paper analyzes gain/power trade-offs in the proposed architecture in the context of noise impact with multi-tone WuRX signaling. The proposed architecture is implemented in 65 nm CMOS and occupies 2.25 mm 2. The primary RX achieves 3.8 dB NF and 0.75 dBm out-of-band P1dB with 440μW power consumption. The WuRX achieves -86 dBm sensitivity for 10kb/s data rate and up to -40 dB signal-to-interferer ratio (SIR) with 171μW power consumption.

A 150 GHz Lens-Free Large FoV Regenerative 2 × 2 Transceiver Array With 31% DC-to-EIRP Efficiency and −70 dBm Sensitivity for a 70 cm Bidirectional Peer-to-Peer Link

This article presents a 150-GHz regenerative low-power miniature two-way radio integrated with on-chip antennas. The low-power radio is based on a reconfigurable fundamental oscillator array that can be used as a sub-terahertz (THz) source in the transmitter (Tx) mode and a sub-THz super-regenerative detector in the receiver (Rx) mode supporting ON–OFF keying (OOK) modulation. The oscillators are coupled through a low-loss integrated Marchand balun-based coupling network that guarantees far-field constructive interference at the Rx side. A 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 2 on-chip patch antenna array is designed with a new adaptive metal-fill placement methodology that largely reduces antenna losses and off-tuning present in sub-THz/THz frequency antenna designs without the need for bulky silicon lenses. Our proof-of-concept prototype achieves a maximum EIRP of 8.52 dBm at a frequency of 149 GHz, an Rx sensitivity of −70 dBm, and a dc-to-EIRP efficiency of 30.7% with no silicon lens, which is the highest efficiency reported of all the silicon-based sub-THz transceivers (TRxs) in the 150-GHz range. The moderate 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 2 array size with no silicon lens offers a large field of view (FoV) of ±40°, which eases node finding and link establishment in deployment. Our miniature low-power radio prototype consumes 11.6 mW in the Tx mode and 10 mW in the Rx mode after duty cycling. Wireless peer-to-peer network measurements with OOK modulation using a 10-Mb/s data rate demonstrate a chip-to-chip communication distance of 70 cm and BER <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\le $ </tex-math></inline-formula> 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-5}$ </tex-math></inline-formula> at/above −55-dBm received power and a BER of 6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-3}$ </tex-math></inline-formula> at −70-dBm received power. The prototype chip was designed using the GlobalFoundries 45-nm silicon-on-insulator (SOI) process, and it occupies a total chip area of 2.1 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 2.1 mm, including the antenna array, making it particularly apt for ultra-miniaturized, high-security, and stealth Internet-of-Things (IoT) nodes for intelligent edge networks and wearable devices.

A 0.4 V, 6.4 nW, −75 dBm Sensitivity Fully Differential Wake-Up Receiver for WSNs Applications

This paper presents a fully differential wake-up receiver (WuRX) with ultra-low power and high sensitivity. Implementing the fully differential framework achieves differential signal processing without an off-chip balun, which achieves noise suppression and sensitivity improvement. The low voltage baseband signal processing (LVBSP) is proposed to cut down the power consumption, which is achieved by the low-voltage fast-response differential amplifier (LFDA) and the time-domain signal processing circuit. Moreover, the periodic offset cancellation technique (POCT) in the baseband circuit is proposed to alleviate the offset and low-frequency noise impacts. This WuRX is implemented in the TSMC 65-nm CMOS process occupying an active area of 0.18 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . When operating at 434 MHz, the proposed WuRX has a −75-dBm sensitivity at 250 bps while consuming 6.4 nW from 0.4 V supply voltage.

A 1 V -21 dBm threshold voltage compensated rectifier for radio frequency energy harvesting

Due to the limitations of battery life and capacity, power supply has been the bottleneck for scaling of a wireless sensor network in thousands or millions of nodes. RF energy harvester (RFEH) is a promising solution to power up sensors and wireless devices due to increasing accessibility of RF energy sources, better silicon integration of the harvester circuit and compatibility with wireless networks. One of the significant limitations of RF energy harvester is low power efficiency rectifier where the main function of the micropower rectifier is to convert RF energy into DC energy. To achieve higher power conversion energy (PCE), this paper presents a five-stage charge pump rectifier, with implementation of diode-connected MOS transistors and an auxiliary circuit to produce compensation voltage to the charge pump to achieve higher efficiency over a wide input range. This work is designed and implemented using 130nm CMOS technology and achieved a wide input power range of 15 dBm with efficiency higher than 20%; and at -21 dBm sensitivity for 1V output is achieved while driving 1 MΩ load at 920MHz.

An Integrated RF-Powered Wake-Up Wireless Transceiver With –26 dBm Sensitivity

This article presents a fully RF-powered wireless transceiver integrating an efficient RF energy harvester (RFEH), a Wake-up Receiver (WuRx), and a Wake-up Transmitter (WuTx) on a single CMOS chip. The WuRx is designed to operate with supply voltages as low as 300 mV allowing to be entirely powered up by the RF energy at power levels as low as −26 dBm. The capability of the WuRx to operate without using a power management unit (PMU) enhances the sensitivity and overall conversion efficiency of the RFEH system. By utilizing an ultralow-power ultralow-voltage envelope detector to obtain the required signal levels, using passive amplification instead of an active low-noise amplifier, and eliminating the voltage regulator removing its power overhead, the transceiver’s input sensitivity has been improved at least by a factor 2 (3 dB) compared to the other previously reported RF-powered transceivers. The proposed transmitter consists of a fast start-up oscillator and an efficient class E power amplifier, which can be externally tuned for different output powers. Fabricated in the TSMC’s 130-nm CMOS process, the measurement results show that the proposed WuRx consuming only 5.7 nW works with input powers as low as −26 dBm, and the proposed transmitter can work with input powers as low as −23 dBm. The WuTx outputs −11 dBm with 51% efficiency at 2.45 GHz using high-Q off-chip components.

A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver

This article presents a highly integrated 2.4-GHz wake-up receiver (WuRX) achieving 91.5 dBm sensitivity with a state-of-the-art power and latency combination of 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> at 100 ms. The proposed within-packet duty-cycling method employs a carrier-sense mechanism to turn off the WuRX early under idle channel conditions, which reduces the dc-power compared with conventional asynchronous packet-level duty cycling by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9\times $ </tex-math></inline-formula> at 10 ms latency (21 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> ) and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> at 1 s latency (0.9 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> ) at the cost of 2 dB in sensitivity. The uncertain-IF topology with a phase-locked loop (PLL)-aided event-driven calibrated local-oscillator (LO) helps reduce the dc-power while maintaining a fast startup. The channel-embedded OOK scheme is used to create a deterministic IF to enable baseband (BB) channel selection and achieve continuous wave (CW) interference tolerance of −47 dB at 20 MHz offset. Fabricated in 65 nm CMOS, input matching and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> oscillator are all implemented on-chip, and operation is demonstrated with integrated low dropout regulators to capture the degradations in realistic system integration.

A 125 μm × 245 μm Mainly Digital UHF EPC Gen2 Compatible RFID Tag in 55 nm CMOS Process

This paper presents a compact and largely digital UHF EPC Gen2-compatible RFID implemented using digital IP blocks that are easily portable. This is the first demonstration of a digital Gen2-compatible RFID tag chip with an area of 125 μm and -2 dBm sensitivity operating in the 860-960MHz band. It is enabled by a) largely standard cell-based digital implementation using dual-phase RF-only logic approach, b) near-threshold voltage operation, and c) elimination of area intensive, complex, and less scalable rectifiers, storage capacitors, and power management units used in conventional RFID tags. In this demonstration, all but six cells were directly used from the standard cell library provided by the foundry. This makes it suitable for cost-sensitive applications, and as embedded RFIDs for tagging counterfeit Integrated Circuits (ICs).

A CMOS Adaptive 433/900 MHz Differential RF Power Harvester with Wide-Dynamic Range for Wireless Powering

A wide-dynamic range high-efficiency differential RF-to-DC power converter for wireless power transfer (WPT) applications is presented. The architecture offers high power conversion efficiency (PCE) over a wide range of input powers by employing cross-coupled high-threshold rectifying devices with stacking diodes. The proposed rectifier uses the adaptive biasing technique to control the rectifying devices’ conduction and minimizes the leakage current of the feedback diodes by utilizing the dynamic body biasing. Compared to the conventional cross-coupled rectifier, the proposed rectifier has a [Formula: see text] dynamic range. A prototype of the proposed rectifier is implemented in 65-nm CMOS technology and occupies an area of 0.0148[Formula: see text]mm2. The rectifier achieves [Formula: see text][Formula: see text]dBm sensitivity for 1[Formula: see text]V output and a 79.4% peak PCE. A dynamic range of 17.3[Formula: see text]dB is achieved at the 433[Formula: see text]MHz in the Industrial Scientific Medical band (ISM band) with a 100-K[Formula: see text] load. Furthermore, the proposed design offers a peak PCE of 62.6% and a wide dynamic range of 16.1[Formula: see text]dB at the UHF 900[Formula: see text]MHz band with a load resistance of 100-K[Formula: see text].