dBm RF Research Articles

Investigation of SIP Signaling Messages Servicing Time

SIP is most widely used signaling protocol in IP telephony for communication sessions conclusion. At time of providing voice services, this communications protocol messages fall to specialized network nodes. Service quality depends on their serving at nodes. To assess the temporal characteristics of services, it is necessary to know the signaling message average handling times values of possible deviations of distribution. In this work experimentally were determined statistical handling time characteristics of individual messages and total message flow traffic entering the SIP, PS, AS and DB MRF nodes. It was found that the service times of messages in the form of their distribution are close to normal. However, the hypothesis that the experimentally obtained distribution is normal was rejected by the 2criterion of verification. Therefore in the SIP signaling components analytical studies is proposed to use a general distribution. Ill. 4, bibl. 11, tabl. 3 (in English; abstracts in English and Lithuanian).http://dx.doi.org/10.5755/j01.eee.114.8.692

An Optical-to-Microwave Converter

By power combining of four photodetectors and impedance matching, we implemented an efficient optical-to-microwave converter capable of achieving 20 dBm RF power and an OIP3 of 35.1 dBm. The bandwidth of the converter is 150 MHz with a center frequency of 1 GHz.

3D Transmission Line Design for High Power RF Components in Laminates

High power (> 30 dBm) RF components such as switches, passives and RF MEMS can be embedded in an advanced 3D package in laminates. We report a novel transmission line and interconnection design for these embedded high power devices. Typical RF signal path consists of input signal lines (microstrip sand coplanar waveguides), interconnections between laminate layers, and RF devices. 3D configurations of multiple buried via holes are first simulated in the HFSS environment and then tested on laminate prototypes for optimized RF performance. Loss points are carefully identified and removed in the design by distributing RF current in a network of interconnections. Extra cooling considerations are included to significantly reduce thermal stress on the system as well as individual components. The final transmission line design can supply over 50 W of RF power into a 12 layer laminate system.

A Passive UHF RFID Demodulator With RF Overvoltage Protection and Automatic Weighted Threshold Adjustment

This paper presents a passive UHF RFID ASK demodulator that operates over a +24 dBm to -14 dBm RF input power range. The demodulator automatically adjusts between high sensitivity mode for weak RF signal power and overvoltage protection mode for high RF power. The input overvoltage protection circuit is designed to protect the IC from high input power while not impacting the sensitivity at weak input power. The demodulator is comprised of a RF rectifier, a variable gain attenuator with automatic threshold adjustment and a nano-power data slicer. The demodulator handles demodulating signals with a minimum to maximum envelope ratio of 0.8 over the entire input power range, and the data slicer consumes only 160 nA from a 0.9 to 1.25 V rectified supply. The RFID chip is fabricated in a 0.13 μm analog-CMOS technology and the entire chip occupies an area of 0.55 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A COMPACT RECTENNA DEVICE AT LOW POWER LEVEL

This article describes the design and performances of a rectenna that collects low incident power density levels, at a single ISM-band frequency (f0 = 2.45GHz). A new rectenna topology consisting only of an antenna, a matching circuit, a Schottky diode, and a DC filter has been modeled using a global simulation. A circular aperture coupled patch antenna is proposed to suppress the first filter in the rectenna device, and in addition, the losses associated with this filter. The harmonics rejection of the antenna is primarily used to reduce the rectenna size. The implementation of the filter in the antenna structure, combined with a reduction of the rectenna size, gives several advantages in several applications where the size and weight are critical criteria. The maximum energy conversion efficiency in this configuration is 34% and is reached for a load of 9.2 kΩ and a RF collected power of SRF = 17μW/cm2 (≈ −10 dBm RF incident upon the diode).

High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs

A high-efficiency CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. A differential-drive active gate bias mechanism simultaneously enables both low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency (PCE), especially under small RF input power conditions. A test circuit of the proposed differential-drive rectifier was fabricated with 0.18 mu m CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on the input RF signal frequency, output loading conditions and transistor sizing was also evaluated. At the single-stage configuration, 67.5% of PCE was achieved under conditions of 953 MHz, - 12.5 dBm RF input and 10 KOmega output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance. In addition, experimental results show the existence of an optimum transistor size in accordance with the output loading conditions. The multi-stage configuration for larger output DC voltage is also presented.

Self-Vth-Cancellation High-Efficiency CMOS Rectifier Circuit for UHF RFIDs

A high-efficiency CMOS rectifier circuit for UHF RFID applications was developed. The rectifier utilizes a self-Vth-cancellation (SVC) scheme in which the threshold voltage of MOSFETs is cancelled by applying gate bias voltage generated from the output voltage of the rectifier itself. A very simple circuit configuration and zero power dissipation characteristics in biasing enable excellent power conversion efficiency (PCE), especially under small RF input power conditions. At higher RF input power conditions, the PCE of the rectifier automatically decreases. This is the built-in self-power-regulation function. The proposed SVC CMOS rectifier was fabricated with a 0.35-µm CMOS process and the measured performance was compared with those of conventional nMOS, pMOS, and CMOS rectifiers and other types of Vth cancellation rectifiers as well. The SVC CMOS rectifier achieves 32% of PCE at the -10dBm RF input power condition. This PCE is larger than rectifiers reported to date under this condition.

A Low Power DVB-T/H Zero-IF Tuner IC Design in 0.25 $\mu{\hbox {m}}$ BiCMOS Technology for Mobile TV Reception

This paper describes fully integrated RF IC sub-system of a DVB-T/H receiver intended for Mobile TV reception. The architecture of the RF IC has been designed to be compliant with the category b2 & c of the MBRAIMoBile Radio Access Interface. specification developed for the introduction of TV into existing mobile phone. The coexistence with GSM transceivers has been taken into account to establish the complete link budget from UHF antenna down to the Digital Front-end. A broadband LNA has been designed for an overall IC noise figure of 3.9 dB. The IIP3 is -5 dBm while 25 dBm RF IIP2 has been measured. A 5th order low pass filter has been implemented for adjacent channel suppression. The total power consumption is 150 mW in continuous mode. Thanks to a new broadband synthesizer architecture using a single VCO, the occupied silicon area is 2.2 mm2 in a 0.25 mum BiCMOS technology

Thermal Analysis of High-Power InGaAs–InP Photodiodes

InGaAs-InP charge-compensated unitraveling-carrier photodiodes with thick depletion region are demonstrated. A 40-mum-diameter photodiode achieved 10-GHz bandwidth and 24.5dBm RF output power. A 100-mum-diameter photodiode achieved bandwidth of 2 GHz and 29 dBm RF output power. Simulation of the temperature distribution in devices is also presented

A 80–100 GHz image‐reject passive‐HEMT mixer

AbstractThis paper describes a single‐sideband, subharmonically pumped, passive‐HEMT integrated circuit mixer developed for use in transceivers for point‐to‐point telecommunications in the 83–87 GHz band. The gallium arsenide (GaAs) monolithic microwave integrated circuit (MMIC) can readily be fabricated using a standard commercial process. The mixer performs equally well for either up‐ or down‐ conversion. For RF signals in the range 80–100 GHz, the conversion loss is typically 20 dB with LO drive in the range 40–50 GHz. Under these conditions, high rejection of the undesired sideband (&gt;18 dB), relative to the desired signal, is achieved. For up‐conversion, 1 dB compression of the mixer gain typically occurs at −12 dBm RF output power. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 2429–2433, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21953

All-digital PLL and transmitter for mobile phones

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

Ultrastable millimetre-wave signal generationusing hybrid modelocking of a monolithic DBR laser

Very efficient ultrastable millimetre-wave signal generation using hybrid modelocking of a monolithic distributed Bragg reflector semiconductor laser is demonstrated for the first time. Unlike conventional hybrid modelocking methods, a low-power (–1 dBm) RF signal is applied to the saturable absorber section of the laser. The detected laser output gives a 34 GHz signal with phase noise &lt; –70 dBc/Hz at 5 kHz offset.

Study of a UHF Mobile Radio Receiver Using a Voltage-Controlled SAW Local Oscillator

Abswuct-Voice-grade signal-noise-distortion (SINAD) tests have been made on a 422 MHz mobile radio receiver incorporating a SAW delay-line local oscillator controlled by a digital phase-locked loop. Details are given of in-channel tests showing required 12 dB SINAD performance with -109 dBm RF input into the antenna, as well as adjacent channel selectivity tests yielding required 70 dB SINAD selectivity at 25 kHz frequency spacing. General details of the receiver circuitry are also given, including the SAW local oscillator with steppedfinger delay line operating in the fifth-harmonic mode. Stability performance tests made with an automated frequency stability analyzer and Hadamard variance techniques, yielded a phase noise < -1 15 dBc/ Hz at 10 kHz Fourier frequency offset, in accordance with expectations. Frequency drift in the IF stage of the stability analyzer was typically in the order of 0.15 Hz over the measurement sequence.