dBm Input IP3 Research Articles

V-band low-power Darlington-pair gate-pumped mixer with thin-film LC-hybrid linear combiner in 90 nm CMOS

Presented is a V-band low-power Darlington-pair double-balanced gate-pumped mixer with a thin-film (TF) LC-hybrid linear combiner in 90 nm CMOS technology. The compact TF LC-hybrid linear combiner is used to feed the differential RF and LO signals to a gate-pumped mixer. Meanwhile, it provides high port-to-port isolations of the mixer. The proposed gate-pumped mixer achieves a −0.76 dB conversion gain, a −7 dBm 1 dB compression point, and a +8.5 dBm input IP3 under a low LO power of −2 dBm. The core power consumption is only 2.8 mW from a 1 V supply. The chip size with all testing pads and dummy blocks is only 0.52 mm2.

A 60 dB Harmonic Rejection Mixer for Digital Terrestrial TV Tuner

A harmonic rejection mixer has been designed for DVB-T reception in VHFIII frequency band. It exhibits 21.3 dB noise figure, 29 dBm input IP3, and 67 dBm input IP2 over the 48-300 MHz frequency range. The third and fifth harmonics are suppressed by more than 60 dB thanks to phase error calibration.The 0.39 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active die is fabricated in 40-GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">τ</sub> Bi-CMOS process consuming 38 mA from a 3.3 V supply including the LO chain.

CMOS Direct-conversion Radio Transceiver Design for 5-GHz WLAN Applications

Direct-conversion radio transceiver chipsets for 5-GHz WLAN have been implemented in 0.18-/jm CMOS technology. The receiver front-end includes low flicker noise down-conversion mixers where the parasitic tail capacitances in the transconductance stage are resonated out at the operating frequency. To reduce the local oscillator pulling and leakage, an offset clock generator is implemented in which a voltage controlled oscillator operates at two-thirds of the operating frequency band. The transmitter front-end can drive up to 2 dBm output power at the driver amplifier. The receiver front-end has 6.5 dB noise figure, -13 dBm input IP3, and voltage gain of 20 dB. The overall receiver has voltage gain of 60 dB. The phase noise of the clock generator at 5 GHz frequency is -109 dBc/Hz at 1 MHz offset.

CMOS Direct-Conversion RF Front-End Design for 5-GHz WLAN

Direct-conversion RF front-end for 5-GHz WLAN is implemented in <TEX>$0.18-{\mu}m$</TEX> CMOS technology. The front-end consists of a low noise amplifier, and low flicker noise down-conversion mixers. For the mixer, an inductor is included to resonate out parasitic tail capacitances in the transconductance stage at the operating frequency, thereby improves the flicker noise performance of the mixer, and the overall noise performance of the front-end. The receiver RF front-end has 6.5 dB noise figure, - 13 dBm input IP3, and voltage conversion gain of 20 dB with the power consumption of 30 mW.

Low power HFET down converter MMIC's for wireless communication applications

An ultra low power GaAs HFET (heterojunction FET) amplifier/mixer MMIC was designed and characterized for portable communication applications in the 900 MHz band. A completely monolithic LNA (80 mil/spl times/42 mil) achieved 10 dB gain, 2.5 dB NF and -4 dBm input IP3 at an operating current of 0.5 mA @ 1.0 V. Receiver sensitivity of a front-end circuit consisting of the LNA and a dual gate FET mixer was characterized using the 12 dB SINAD method. The IC achieved -117 dBm receiver sensitivity in the 900 MHz cellular band. The total power consumption of this miniature down converter was about 2 mW. The HFET down converter IC achieved the same receiver sensitivity as a MESFET down converter at 1/5th of the power. The extremely low power dissipation, high third order intercept point, high level of integration, and very good RF performance of this monolithic IC make it an ideal candidate for wireless applications.