Gain flatness is an important technical indicator for ADC-Based SerDes in practical applications. Due to the serial interface's unknown channel characteristics, signal amplitudes at the SerDes receiver remain uncertain. Therefore, the I/O interface needs to cover a wide gain range to meet the system linearity and signal amplitude requirements. This research introduced an input-transistor switching technique for the programmable gain amplifier (PGA), which adjusts the gain by changing the input transistor's number and effective transconductance to avoid the gain-rising problem in the existing PGA structures at high frequency. The core circuit of this research adopts a inductorless structure that can save the die area. Simulation results have shown that under the TSMC CMOS 40 nm process, the use of source degeneration zero compensation technique can achieve 0–15 GHz bandwidth with +0.05 dB variation, −7.3-6.6 dB gain tuning range. The circuit voltage is 1.8V, and the power consumption is 8.208 mW.
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