dB FoM Research Articles

A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology

A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology

Analysis and design approach of wideband digital‐based feedforward ring oscillators

AbstractMulti‐protocol applications and complex systems‐on‐chip demand several clock sources to fulfill all data‐rate requirements. Among the different types of clock sources, LC oscillators dominate the high data‐rate communication standards where frequency stability is a major constraint. In contrast, ring oscillators are preferred for legacy support applications due to their wider tuning range and where stability is not a constraint. Since stability enhancement techniques have been already implemented to ring oscillators, increasing the tuning range of a single ring clock reference might fulfill a broad margin of data rates. This paper presents an analysis and a design approach of wideband digital‐based oscillators based on secondary feedforward paths to support most of the data‐rate requirements inside systems‐on‐chips. Here, we present the inclusion of these auxiliary loops as a tuning range enhancement technique to reduce the total number of required clock references. The presented analysis comprises piece‐wise functions able to accurately predict an FDRO oscillation frequency. Using the piece‐wise model, we present a 15,000 12‐track standard‐cell scalable feedforward oscillator. Auxiliary feedforward inverters allow a maximum 1.5 GHz frequency and a 3 tuning range enhancement while enabling a 100 kHz minimum oscillation frequency. The proposed oscillator occupies an area of 0.05 mm2 in a 180 nm CMOS pure digital node and achieves a 41 ps@1.25 GHz RMS jitter of and a −121 dB FOM.

A 2.4-GHz Sub-Sampling PLL With an Adaptive and No Power Contribution FLL Achieving 103.58 fs rms Jitter and −257.8 dB FOM

A sub-sampling PLL (SSPLL) employing an adaptive frequency-locked loop (FLL) without static power consumption is proposed in this letter. A new unlock detection mechanism and a configurable PFD are realized in the adaptive FLL. With the new unlock detection mechanism, while the FLL that contains phase detector, divider, and charge pump dissipates no power during the locked steady state, it automatically starts when external interferences disturb the locked state. The optimized dead zone in the configurable PFD ensures a rapid relocking operation. Based on the proposed adaptive FLL, the 2.4 GHz SSPLL is fabricated in a 40-nm CMOS process. It achieves −128.5 dBc/Hz at 1 MHz offset frequency and the rms jitter is 103.58 fs integrated from 10 k to 10 MHz. It consumes 1.55 mW at 1 V supply and achieves −257.8 dB FOM.

A 0.8 V, 5.3-5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and -251.6 dB FoM.

This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and dB FoM.

C3S–QVCO: A low phase noise low power super–harmonic coupling QVCO with cross–connected common–source nodes

In this paper, a novel passive super–harmonic coupling QVCO is presented. The coupling is achieved by Cross–Connecting the top and bottom Common–Source nodes in the complementary (current reuse) LC Cross–Coupled oscillator topology, and therefore, the circuit is named as C3S–QVCO. Unlike the transformer coupling QVCO (TC–QVCO), as the typical super–harmonic coupling technique, the die area is not increased. Also, in the proposed QVCO, neither additional power consumption nor additional noise generator component is required, for quadrature operation. Therefore, the proposed QVCO has a good power consumption performance. The proposed method is evaluated theoretically and analytically, and it is proved that the proposed method is capable of generating multi–phase outputs. The proposed QVCO is designed in a 0.18 ​μm RF–CMOS technology with a power supply of 1.8 ​V, the current consumption of 6.25 ​mA, and the tuning range of 3.75–3.95 ​GHz (5.3%). Post layout simulation result shows −129 ​dBc/Hz, and 190 ​dB phase noise and FOM for the proposed QVCO at 1 ​MHz offset from the 3.75 ​GHz frequency. The proposed QVCO presents 6 ​dB phase noise improvement compared to parallel (P)–QVCO and also demonstrates similar phase noise performance to that of the TC–QVCO, with the same power consumption. Maximum phase/amplitude errors of the proposed QVCO for a 1% mismatch in the oscillator’s tank capacitors are 0.72°/2 ​mV, in the whole tuning range. Those are 0.77°/7.3 ​mV for the P–QVCO and 1.3°/2.3 ​mV for the TC–QVCO.

A Four-Step Incremental ADC Based on Double Extended Binary Counting With Capacitive DAC

This brief proposes a discrete-time four-step reconfigurable incremental ADC (IADC) which consists of a first-step SAR conversion, a second-step IADC operation, and double extended binary counting (EBC). While coarse conversion with the 8b SAR ADC is preceded, instead of 8b DAC, 7b capacitive DAC based integrator operation in the IADC becomes available to reduce the chip area and power consumption of amplifier. Additional resolution is achieved by performing the EBC twice, where its conversion time is reduced by using the binary operation with a 7b capacitive DAC. The IADC and the EBC are reconfigured to utilize the same sub-blocks of one amplifier and one comparator, thus reducing silicon area and obtaining high linearity. A prototype ADC is fabricated in a 180-nm CMOS process, and it achieves 179.7 dB FoM and consumes 176 $\mu \text{W}$ .

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case fractional operation, achieving −246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with −40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities—DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity—are calibrated in the background while the system operates normally. This results in ~15 dB fractional spur improvement (from −41 dBc to −56.5 dBc) during synthesis and ~15 dB EVM improvement (from −25 dB to −40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.

A Fractional-<italic>N</italic> Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

A fractional- $N$ sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This technique can be used for designing a fractional- $N$ PLL with low in-band phase noise and low spurious tones with low power consumption. The short-current-free pipelined phase-interpolator used in this work is capable of achieving high-linearity with low-power while minimizing the intrinsic jitter. A number of other circuit techniques and layout techniques are also employed in this design for ensuring high-performance operation with minimal chip area and power consumption. The proposed fractional- $N$ PLL is implemented in standard 65 nm CMOS technology. The PLL has an operating range of 600 MHz from 4.34 GHz to 4.94 GHz. In fractional- $N$ mode, the proposed PLL achieves -249.5 dB FoM and less than -59 dBc fractional spurs.