Current-mode Mixer Research Articles

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.

A 76- to 81-GHz Multi-Channel Radar Transceiver

This paper presents a packaged 76- to 81-GHz transceiver chip implemented in SiGe BiCMOS for both long-range and short-range automotive radars. The chip contains a two-channel transmitter (TX), a six-channel receiver (RX), a local-oscillator (LO) chain, and built-in self-test (BIST) circuitry. Each transmit channel includes multiple variable-gain amplifiers and a two-stage power amplifier. Measured on-die output power per channel is +18 dBm at 25 °C, decreasing to +16 dBm at 125 °C. Each receive channel includes a current-mode mixer, followed by intermediate-frequency buffers. At 25 °C, measured on-die noise figure is 10–11 dB, conversion gain is 14–15 dB, and input 1-dB compression point exceeds +1 dBm. An integrated LO chain drives the transmit and receive chains and includes an 18.5- to 20.6-GHz voltage-controlled oscillator connected to cascaded frequency doublers and a divide-by-four prescaler. At 25 °C, measured phase noise is −100 dBc/Hz at 1-MHz offset from a 77-GHz carrier. Integrated BIST circuits enable the measurement of signal power, RX gain, channel-to-channel phase, and internal temperature. The chip is flip-chip packaged into a ball-grid array and extracted interconnect loss for the package is 1.5 to 2 dB. Total power consumption for the chip is 1.8 W from 3.3 V for a single-TX, six-RX mode.

All Current Mode RF Receiver Front End

In this paper, an all current mode RF receiver of direct conversion for 802.11b WLAN has been proposed. The front end of this receiver, containing a current mode LNA plus mixer (CLPM) circuit and a current mode quadrature ring oscillator (CQRO), has been designed and simulated in chartered 0.18 μm CMOS process. The proposed method features that the pseudo-cascode current mirrors of the current mode LNA have not been implemented in cascade, so we can decrease the supply voltage and increase the output impedance by adding a common-gate transistor. The current mode mixer has been composed by the four added common-gate transistors; this implementation makes the current mode mixer a two-layer structure that reduces the supply voltage. The current mode quadrature oscillator is a four current mode stage ring oscillator employing feed forward paths. The CLPM has a measured power conversion gain of 18.6 dB, an input referred third-order intercept point (IIP3) of −0.53 dBm. The total noise figure is 3.9 dB and the power is only 15 mW by post-simulations. The CQRO core current consumption is 24 mA with a 1 V supply. The phase noise results in −121.61, −148 dBc/Hz at 1 MHz, and 10 MHz from the carrier, respectively.

A 2.4 GHz High Linearity Subthreshold Current Mode Folded CMOS Mixer

In this paper, a new CMOS active mixer using a parallel-folded topology which can operate at sub-1 V supply voltage is proposed. Such current mode mixer requires less voltage headroom with good linearization. In the proposed circuit, LC resonators were adapted to replace a commonly used current source, and current mirrors replace the common load resistances to export currents, the core of mixer works in a subthreshold region. This paper analyzes the performance of the high-linearity current mode mixer, comparing with other current mode mixer; this circuit demonstrates competitive performance with a lower supply voltage, higher linearity. A layout was designed and simulated in the standard chartered 0.18 μm RF CMOS process with Spectre in Cadence Design Systems. Simulation results show a satisfied mixer performance at 2.4 GHz. The simulated 11P3 of 13.48 dBm, with a power gain of -0.21 dB is obtained. A low dissipation power of 5.3 mW at 1 V supply voltage is also achieved.

Software Radio용 전압제어 주파수가변 CMOS 전류모드 필터

In this paper, a voltage-controlled frequency tunable current-mode integrator and a 3rd-order current-mode Chebyshev filter in 1.8V- CMOS is realized for software radio applications in system-on-chips. This filter is used for reconstruction purposes between a current-steering DAC and a current-mode mixer. Power consumption of the designed filter can be reduced by using a current-mode small size integrator. And also, cutoff frequency of this filter is variable between 1.2MHz and 10.1MHz, the power consumption is 2.85mW. And the voltage bias compensated circuit is used to control the voltage variation.in the designed filter.

A low-voltage low-power CMOS transmitter front-end using current mode approach for 2.4 GHz wireless communications

This paper presents a low-voltage low-power transmitter front-end using current mode approach for 2.4GHz wireless communication applications, which is fabricated in a chartered 0.18μm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique, which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4GHz, the transmitter front-end provides 15.5dB of power conversion gain, output P−1dB of 3dBm, and the output-referred third-order intercept point (OIP3) of 13.8dBm, while drawing only 6mA from the transmitter front-end under a supply voltage of 1.2V. The chip area including the testing pads is only 0.9mm×1.1mm.

A differential low-voltage high gain current-mode integrated RF receiver front-end

A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (Gm-LNA) and a differential current-mode down converted mixer. The single terminal of the Gm-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, Cx1 and Cx2, can not only reduce the effects of gate-source Cgs on resonance frequency and input-matching impedance, but they also enable the gate inductance Lg1,2 to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 μm CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of −7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations.

A Low-Voltage CMOS Current Mode Integrated Transmitter Front-end for 2.4-GHz Wireless Communications

This paper presents a low-voltage low-power current mode transmitter front-end for 2.4 GHz wireless communication applications, which is fabricated in a chartered 0.18-mm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4GHz, the transmitter front-end provides 15.5dB of power conversion gain, output P-1dB of 3dBm, and the output-referred third-order intercept point (OIP3) of 13.8dBm, while drawing only 6 mA from the transmitter front-end under a supply voltage of 1.2 V. The chip area including testing pads is only 0.9 mm 1.1 mm. Index Terms –CMOS, up-conversion mixer, driver amplifier, transmitter, current mode, high linearity, low-power

A low voltage current mode CMOS integrated receiver front-end for GPS system

This paper presents a low voltage, 1.6 GHz integrated receiver front-end which is implemented by the standard 0.35 μm, 3M2P CMOS technology. The receiver consists of a transconductance low noise amplifier (Gm-LNA), a down conversion current mode mixer and a voltage-controlled oscillator using accumulation-mode MOS varactor (A-MOS VCO). A current mode mixer is used to reduce the supply voltage to 1 V. A specially designed Gm-LNA converts RF input voltage to RF input current for the current mode mixer. This could eliminate an unnecessary I---V, V---I conversion and reduce the non-linearity contribution. Moreover, a low voltage A-MOS VCO, with a good phase noise and wide tuning frequency range, is used to generate a required oscillating frequency for the receiver. The integrated receiver front-end has a measured power conversion gain of 11.4 dB, an input referred third-order intercept point (IIP3) of 6.1 dBm, and a noise figure of 5.87 dB. The measured total power consumption is 40.9 mW with 1 V supply.

The Design of Low LO-Power 60-GHz CMOS Quadrature-Balanced Self-Switching Current-Mode Mixer

This letter describes the analysis and measurement of a complementary metal-oxide semiconductor (CMOS) quadrature-balanced current-mode mixer with a 90 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> branch-line hybrid coupler and self-switching current-mode devices. The proposed mixer, using 0.13 mum 1P8M CMOS technology, can downconvert a 60 GHz RF signal to a 2 GHz intermediate frequency (IF) signal, with a local-oscillator power of 0 dBm at 58 GHz. In the design, the mixer had a single-end conversion gain of 1 dB and an input-referred 1 dB compression point of 2 dBm. The LO-RF isolation of the mixer can achieve -37 dB while using 3 mA from a supply voltage of 1.2 V.

A 3rd-order current-mode filter in 0.12 μm CMOS

Abstract. For software radio applications in system-on-chips, a 3rd-order current-mode Butterworth filter in 120 nm CMOS is realized. This filter is used for reconstruction purposes between a current-steering DAC and a current-mode mixer. Power can be reduced by using a current-mode architecture. The cut-off frequency of this filter is switchable between 1 MHz and 4 MHz, the current consumption is 4.5 mA at VDD=1.5 V, the inband noise density is 100 pA/√Hz and it has a dynamic range up to 65 dB.