Current-mode Amplifier Research Articles

A Comprehensive Harmonic Analysis of Current-Mode Power Amplifiers

This work presents a comprehensive theoretical analysis of current-mode power amplifiers as a function of input power for different biasing classes under the common simplifying assumption of constant transconductance and hard current cut-off/saturation. Typically, the theoretical analysis of power amplifier performance and behavior are carried out only at maximum output power. However, to achieve high data-rates, modern telecommunication systems adopt signals characterized by a very high peak-to-average power ratio, thus it is useful to analyze the power amplifier behavior as a function of power back-off. Moreover, in many cases, to enhance the efficiency and/or to apply harmonic shaping techniques, a clipped drain-source current, which approaches a square wave, is required. The classical analysis can be extended to low power levels only under the assumption of power-independent conduction angle, which is true only for class-A and class-B amplifiers, and does not take into account possible waveform clipping at maximum current. This work presents a complete theoretical Fourier analysis of FET-based power amplifiers as a function of quiescent drain-source current at any input power level and accounting for the clipped current case, up to the square-wave limit, reorganizing and completing the material that can be found in classical textbooks in the field.

A low-voltage gain boosting-based current mirror with high input/output dynamic range

This paper presents a bulk-driven current mirror circuit based on the gain-boosting technique to achieve high input/output dynamic range and high output resistance. The bulk-driven based diode-connected transistor at the input removes the threshold voltage limitation to provide low headroom voltage on the basic transistors. In addition, the auxiliary circuit used in the first gain-boosting structure is a current mode amplifier that is driven by draining current from the main circuit to remove threshold voltage limitation on the input/output swing. In order to achieve higher output resistance, the second gain-boosting structure includes a voltage mode amplifier without creating any limitation on the output swing. Simulation results in a 0.18 ​μm CMOS technology show a maximum output voltage swing of 0.9 ​V under a 1 ​V supply, while the input and output resistances are 68.3 ​Ω and 10.5 ​GΩ, respectively. The current transfer error also changes between −0.085% and +0.075% for an input current range of 1000 ​μA.

A Highly Digital ADC With Enhanced Accuracy Using a Simple Ripple-Transferring Replica Pseudo PLL Technique

We present a simple ripple-transferring replica pseudo phase-locked loop (PLL) technique for a highly digital ADC. The ADC is mainly constituted by main and replica pseudo PLLs. Compared with conventional techniques, this technique minimizes the main loop’s input ripple by means of inverting the replica loop’s input ripple and transferring it to the input of the main loop for the sum of the two ripples, so the accuracy of the ADC should be improved. To achieve the transfer function above, on the transferring path, a wide-band current mode amplifier is proposed. The proposed ADC is well suited for accuracy and power improved design. Fabricated with a 0.18- ${\mu }\text{m}$ CMOS process, the ADC achieves 65-dB SNDR while operating from a 1.2-V supply and using a 1-kHz input sine wave. Moreover, the power dissipation is only 11 ${\mu }\text{W}$ .

Effect of Shunt Capacitances on Performance of Current-Mode Class-DE Power Amplifier at Any Active Time

In this paper, a current-mode Class-DE (CMCDE) power amplifier is presented. The CMCDE with linear shunt capacitance under zero-current switching (ZCS) and zero current-derivative switching (ZCDS) conditions at any active time is analyzed, simulated, and fabricated. An analytical theory along with the design simulation and verification by experimental results at active time $\tau _{d}= \pi / 2$ are given. It was shown that the peak switch voltage can be adjusted with active time $\tau _{d}$ . The proposed amplifier offers several desirable features, such as simple structure and possibility to include the parasitic inductance and shunt capacitance of the mosfet into a load network, so that ZCS condition is maintained. The results show that the switch voltage and current obtained in CMCDE amplifier are inversed in comparison to the voltage-mode Class-DE (VMCDE) amplifier by using a simple output matching network and series inductance. Also, we could control the harmonics in one resonator in comparison to multiple resonators used in some high-efficiency power amplifiers. The measured maximum drain efficiency of 88% and power gain of 22 dB at 42-dBm output power was obtained at 4 MHz for CMCDE amplifier at active time $\tau _{d}= \pi / 2$ .

A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC

This paper presents a self-biased current-mode amplifier (CMAMP) suitable for a switched-capacitor circuit. The CMAMP uses a subthreshold-biased transimpedance stage as a current-sensing load, and minimizes static power dissipation by passing bias current only at the input stage. The first-order system behavior with single dominant pole gives stable phase margin without complicated frequency compensation. Self-biasing circuits automatically generate bias voltages to sustain performance over a wide range of supply voltage. The designed CMAMP is verified in a 10-bit pipeline analog-to-digital converter (ADC) fabricated in a 65-nm CMOS process. The ADC achieves a figure of merit of 14.3 fJ/c-s with a supply voltage of 0.6 V at 2.5 MS/s.

Improving Operational Performance of Magnetically Suspended Flywheel With PM-Biased Magnetic Bearings Using Adaptive Resonant Controller and Nonlinear Compensation Method

Permanent magnet-biased magnetic bearings (PBMBs) are widely used in flywheel energy storage systems because of their comprehensive advantage in power loss and controllability. However, there is a nonlinear relationship between magnetic force, control current, and eccentric displacement of the PBMB. When the system is required to be high performance, the nonlinear dynamics of the PBMB must be considered in a control design. Therefore, this paper proposes a novel nonlinear compensator based on the nonlinear model of the PBMB and it is applied to a magnetically suspended flywheel (MSF) with PBMBs. To implement the perfect nonlinear compensation, an adaptive resonant controller is also presented to compensate the dynamics of the current-mode amplifier. Finally, the proposed method is verified by experiments on the test rig of the MSF and can be used to improve the performance of the system.

Micropower CMOS lock‐in amplifier for portable applications

A new fully integrated micropower CMOS analogue lock-in amplifier (LIA) is presented. To achieve a compact architecture able to operate under low voltage with low-power consumption, it is based on a current-mode amplifier with embedded rectification within the transconductance stage. Post-layout results for a 0.18 µm CMOS implementation show a dynamic reserve of 51.2 dB, a power consumption of 482 µW and an integration area of 0.03 mm2. The frequency operation ranges from 450 Hz to 1.1 MHz, whereas the gain is programmable from 39 to 59 dB, providing the LIA with flexibility to match a wide range of applications.

Techniques for Power Dynamic Range and Back-Off Efficiency Improvement in CMOS Digitally Controlled Polar Transmitters

Techniques to extend the power dynamic range and to reduce the dc power consumption in back-off for a multiband CMOS digitally controlled polar transmitter are described. The techniques are applied to a transmitter comprising a digitally controlled buck converter and a current-mode class-D RF amplifier with digitally controlled unit cells. The power dynamic range is improved by using tri-state unit-cells (rather than the customary “on–off” controlled cells) to reduce the feed-through power. The measured overall power dynamic ranges are 91 and 85 dB, at 0.85 and 1.75 GHz, respectively. DC power consumption at low power was reduced by introducing a new charge-sampling mode of operation for the buck converter in addition to the customary pulse-width modulation operation. Experimental results showed dc power consumption reduced by 30% at low power.

Design and Analysis of Current Mode Amplifier as Drive Electronics for Linear Voice Coil Motor

Voice Coil Motor is a precise positioning and motion control device, the drive electronics must be of utmost accuracy such that it accounts for the exact requirements of the motor load. This work mainly focuses on the design and analysis of a current mode based operational amplifier, which is expected to generate the precise magnitudes of current. An improved Howland current pump, current drive based amplifier is theoretically analyzed and the analog simulation is performed. A novel hardware scheme is proposed which is suitable for VCM testing and the methodology to develop the hardware is also emphasized.

Fully-Integrated CMOS LDO Regulator Based on an Embedded Current-Mode Capacitor Multiplier

This article presents a fully-integrated CMOS output-capacitorless low-dropout voltage regulator (LDO). A capacitor multiplier based on a current-mode amplifier is embedded into the error amplifier of the aforementioned LDO to simultaneously enhance the dynamic specifications to load variations, stability by pole splitting, and power saving. The proposed LDO topology is designed and post simulated using a 0.35 μm CMOS process to deliver a load current between 0-100 mA. The dropout voltage of the LDO is set to 200 mV for 2-3.5 V input voltage. A final benchmark comparison considering all relevant performance metrics is presented.

Dual‐mode CMOS feed‐forward transimpedance amplifier for LADARs

A dual-mode transimpedance amplifier (TIA) is realised in a 0.18 μm CMOS technology for the applications of 1 Gbit/s laser detection and ranging (LADAR) systems. The proposed dual-mode CMOS feed-forward TIA consists of a voltage-mode inverter input stage with a feedback resistor, followed by a current-mode common-gate amplifier with a feed-forward technique applied at the gate so as to achieve low noise, low power consumption, high gain and wide bandwidth characteristics simultaneously. The measured results demonstrate 76 dBΩ transimpedance gain, 720 MHz bandwidth for 0.5 pF photodiode capacitance, −26.3 dBm sensitivity for 10−12 bit error rate and 20.7 mW power dissipation from a single 1.8 V supply.

Design of positive feedback driven current-mode amplifiers Z-Copy CDBA and CDTA, and filter applications

In this study, high-performance current-mode amplifiers Z-Copy current differencing buffered amplifier (ZC-CDBA) and current differencing trans-conductance amplifier (ZC-CDTA) are designed. In orde...

A High Performance Current-Mode Instrumentation Amplifier with Level Shifter for Single Power Biomedical Applications

In this paper, a high performance current-mode instrumentation amplifier has been proposed with low noise, low power and high CMRR features. The proposed design can adjust the gain with an external resistor for the processing of various biomedical signals. To reduce the noise of the amplifier, two design methods including PMOS input and lateral pnp BJT input have been implemented to improve the prior arts. To meet the single power supply need, a biomedical voltage level shifter is also proposed for low cost CMOS implementation. Based on the post-layout simulation results, the presented current-mode amplifier achieves high CMRR over 120 dB, power consumption of 61 uW at 1.8-V supply using standard 0.18-um CMOS technology.

On‐chip readout circuit for nanomagnetic logic

An interface for reading the output of nanomagnetic logic (NML) is indispensable in order for NML to interact with existing CMOS ICs. Two alternative designs readout interface circuit (RIC1 and RIC2) for NML RIC are proposed based on dual barriers magnetic tunnel junction (DBs-MTJ), which is composed of two fixed layers (with anti-parallel magnetisation state) and a common free layer. RIC1 utilises the same layer order of DB-MTJ to form an up–down structure, whereas RIC2 exploits the reversed layer order of DB-MTJ to form a left–right structure. They utilise the three-terminal approach to realise the self-reference readout scheme. The magnetisation state of the free layers in RIC1 and RIC2 are controlled by the fringing field from NML and biased by the designed on-chip clock field. The sensing circuits in RIC1 and RIC2 utilise dynamic current mode and pre-charge sense amplifier, respectively. The simulation results indicate that RIC1 and RIC2 can achieve comparable magnetoresistance values, and also realise the logical readout scheme by itself. The switching time in RIC1 is less than that in RIC2, whereas time delay for data transportation in RIC1 is more than that in RIC2. RIC2 is more amenable than RIC1 to the current fabrication process technology.

ACHIEVING A LINEAR DOSE RATE RESPONSE IN PULSE-MODE SILICON PHOTODIODE SCINTILLATION DETECTORS OVER A WIDE RANGE OF EXCITATIONS

We are developing a new dose calibrator for nuclear pharmacies that can measure radioactivity in a vial or syringe without handling it directly or removing it from its transport shield “pig”. The calibrator's detector comprises twin opposing scintillating crystals coupled to Si photodiodes and current-amplifying trans-resistance amplifiers. Such a scheme is inherently linear with respect to dose rate over a wide range of radiation intensities, but accuracy at low activity levels may be impaired, beyond the effects of meager photon statistics, by baseline fluctuation and drift inevitably present in high-gain, current-mode photodiode amplifiers. The work described here is motivated by our desire to enhance accuracy at low excitations while maintaining linearity at high excitations. Thus, we are also evaluating a novel “pulse-mode” analog signal processing scheme that employs a linear threshold discriminator to virtually eliminate baseline fluctuation and drift. We will show the results of a side-by-side comparison of current-mode versus pulse-mode signal processing schemes, including perturbing factors affecting linearity and accuracy at very low and very high excitations. Bench testing over a wide range of excitations is done using a Poisson random pulse generator plus an LED light source to simulate excitations up to ∼106 detected counts per second without the need to handle and store large amounts of radioactive material.

Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier

This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

A 2.24 mW 74 dBΩ-Gain, dc to 600 MHz-BW differential baseband amplifier for 60 GHz wireless applications

A low power, wideband and high linearity current-mode based differential baseband amplifier with a bandwidth from dc to 600 MHz applied for 60 GHz zero-IF RF receiver is presented. The wideband differential baseband amplifier is realized in a 90 nm CMOS process. A series-series feedback technique and a Q-enhanced active inductor are adopted in the current-mode baseband amplifier for achieving wideband and high linearity under a small current consumption. The measured maximum BW of 600 MHz, gain of 74 dBΩ and OIP3 of +12.5 dBV are realized with power consumption of only 2.24 mW under a supply voltage of 1.4 V. The measured performance shows the baseband amplifier fulfills the requirements for 60 GHz zero-IF RF transceivers.

채널 등화기를 내장한 2.0GS/s 5비트 전류 모드 ADC 기반 수신기

본 논문에서는 고속 직렬 링크에 사용할 수 있는 5비트 2.0GS/s 2-way time interleaved 파이프라인 ADC 기반의 수신기를 소개한다. 샘플링 주파수를 높이기 위해, ADC 각 단은 트랙킹과 증폭이 동시에 수행되는 전류 모드 구조를 사용하였다. 또한 ADC 각단에 1-tap FIR 등화기를 탑재하여 별도의 디지털 후처리 없이 채널의 ISI를 감소시켰다. 제안한 수신기는 110nm 공정을 사용하여 설계하였다. 메모리를 제외한 수신기는 <TEX>$0.58{\times}0.42mm^2$</TEX>의 크기를 갖고, 동작전압 1.2V에서 91mW의 전력을 소모한다. 시뮬레이션 결과 2.0GS/s 샘플링 주파수에서 20MHz의 입력 주파수와 Nyquist 주파수인 1.0GHz 입력신호에 대하여 동일하게 26.0dB의 SNDR과 4.0비트의 ENOB특성을 확보하였다. In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is <TEX>$0.58{\times}0.42mm^2$</TEX>. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.

A CMOS inverter-based class-AB pseudo-differential amplifier with current-mode common-mode feedback (CMFB)

This paper presents a CMOS inverter-based class-AB pseudo-differential amplifier comprising current-mode common-mode feedback (CMFB). The circuit employs two CMOS inverters and the complementary CMFB consisting of current-mode common-mode (CM) detector and transimpedance amplifier. The circuit has been designed using 0.18 μm CMOS technology and operates at 1 V supply. The simulation results demonstrate rail-to-rail operation with low CM gain (?15 dB). The power dissipation of the circuit is 102.5 μW.

Current Mode Programmable Analog Modules using Low voltage Digitally Controlled CMOS CCII

The current mode programmable analog modules are realized using digitally controlled low voltage CMOS current conveyors. These programmable modules include current mode amplifiers, integrators, differentiators, first order multifunctional filter and second order multifunctional filters. The realized current mode programmable analog modules can provide digital control to the parameters through an n-bit control word with high resolution capability and reconfigurability. These programmable analog modules are suitable for realizing current mode field programmable analog array. The realized programmable analog modules are designed and verified using PSPICE and the results thus obtained justify the theory.