Crosstalk Faults Research Articles

Crosstalk fault modeling in defective pair of interconnects

The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the deep sub-micron (DSM) chips. In this paper, we describe the line-defect-based crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model is very fast (at least 11 times faster than PSPICE model) and its accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor–victim the model accuracy differs marginally.

Crosstalk- and SEU-Aware Networks on Chips

On-chip routing elements are extensively used in complex NoC designs. Faulty operation of such elements due to crosstalk faults or soft errors can severely affect a device's functionality and performance. This article investigates the application of different hardware- and software-based approaches to improving these elements' dependability, and discusses the advantages and drawbacks of these approaches from an energy consumption perspective.

Efficient Interconnect Test Patterns for Crosstalk and Static Faults

This paper introduces effective test patterns for system-on-chip and board interconnects. Initially, “ <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6n$</tex> ” patterns are introduced to completely detect and diagnose both static and crosstalk faults, where “ <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$n$</tex> ” is the total number of interconnect nets. Then, more economic “ <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4n + 1$</tex> ” patterns are described to test the crosstalk faults for the interconnect nets separated within a certain distance.

On modeling crosstalk faults

Traditionally, digital testing of integrated semiconductor circuits has focused on manufacturing defects. There is another class of failures that happens due to circuit marginalities. Circuit-marginality failures are on the rise due to shrinking process geometries, diminishing supply voltage, sharper signal-transition rates, and aggressive styles in circuit design. There are many different marginality issues that may render a circuit nonoperational. Capacitive cross coupling between interconnects is known to be a leading cause for marginality-related failures. In this paper, we present novel techniques to model and prioritize capacitive crosstalk faults. Experimental results are provided to show effectiveness of the proposed modeling technique on large industrial designs.

Test cost reduction for logic circuits: Reduction of test data volume and test application time

AbstractWe believe that reduction of the testing cost is becoming increasingly important as the size of VLSIs becomes larger. Moreover, as the structure of VLSIs becomes more complicated, test compaction, test compression, and test application time reduction for non‐stuck‐at faults, such as delay faults, bridging faults, crosstalk faults, and open faults, must be considered. In addition, new methods of fault diagnosis and high‐level testing must be developed in order to reduce testing costs or diagnostic costs. In this paper we have surveyed recent research on the reduction of testing cost for logic circuits, including test compaction for combinational circuits and sequential circuits, test compaction under IDDQ testing, and test compression and test application time reduction for scan circuits. © 2005 Wiley Periodicals, Inc. Syst Comp Jpn, 36(6): 69–83, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.20240

Fault tolerant bus architecture for deep submicron based processors

In the Deep Submicron era testing of processors is gaining prominence due to the effect of many analog faults. These faults have a direct impact on the signal integrity in interconnects. In deep submicron based processors electromigration poses a major challenge for interconnect reliability. This is of major concern in processor bus architectures. Though a lot of research has been focused on fault tolerance at the module level, no effective research has been carried out to evolve fault tolerant interconnect structures. Faults due to electromigration give rise to weak ones and zeros, thus affecting the signal integrity. This paper presents a fault tolerant scheme for electromigration which also leads to unification of detection and correction of crosstalk faults and stuck-at faults. In the scheme presented, the signal is rerouted through adjacent spare interconnects. The spare interconnect also acts as a shield against crosstalk under fault free system operation. Moreover, the entire testing process is carried out concurrently with the processor instruction execution. The hardware overhead is also insignificant compared to the overall device count in a deep submicron based processor. To the best of our knowledge this is the first time a fault tolerant scheme for bus architectures is being presented.

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

We describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults.

Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults

Built-in self test (BIST) scheme simplifies the detection of crosstalk faults in deep-submicron VLSI circuits in the boundary scan environment. The scheme tests for crosstalk faults with a periodic square wave test signal under applied random patterns generated by a linear feedback shift register (LFSR), which is transconfigured from the embedded circuit's boundary scan cells. The scheme simplifies test generation and test application while obviating the fault occurrence timing issue. Experimental results show that coverage for the induced-glitch type of crosstalk fault for large benchmark circuits can easily exceed 90%.

High-Level Crosstalk Defect Simulation Methodology for System-on-Chip Interconnects

For system-on-chips (SoC) using nanometer technologies, buses and long interconnects are susceptible to crosstalk defects that may lead to functional and timing failures. Testing for crosstalk defects is becoming important to ensure error-free operation of an SoC. To efficiently evaluate crosstalk-defect coverage of existing tests and facilitate the development of new crosstalk test methodologies, effective crosstalk-defect coverage-analysis techniques are needed. In this paper, we present an efficient high-level crosstalk-defect simulation methodology for interconnects dominated by capacitive coupling effects. A novel coupling defect-simulation model was developed and implemented in hardware description languages. The high-level crosstalk-defect simulation methodology was examined by SPICE simulations. Experimental results show the crosstalk defect simulation methodology efficiently provides high-fidelity defect-coverage results. The proposed methodology enables fast exploration and evaluation of different tests, leading to high-quality, low-cost manufacturing tests for crosstalk-induced ac failures.

TMR Voting in the Presence of Crosstalk Faults at the Voter Inputs

In high reliability systems, the effectiveness of fault tolerant techniques, such as Triple-Modular-Redundancy (TMR), must be validated with respect to the faults that are likely in the current technology. In todays' Integrated Circuits (IC), this is the case of crosstalks, whose importance is growing because of device & interconnect scaling. This paper analyzes the problem of crosstalk faults at the inputs of voters in TMR systems. In particular, possible problems are illustrated, and it is shown that such crosstalk may invalidate the reliability of both voting, and diagnosing operations. The problem is analyzed from a probabilistic point of view. Its occurrence is estimated by using a set of TMR systems obtained with combinational benchmarks as functional modules. The possible problems of such operations are discussed in the presence of crosstalk faults. It is shown that crosstalk may invalidate the reliability of both voting, and diagnosis operations. A probabilistic model of the voting & diagnosis operations in the presence of crosstalk has been developed. Finally, such a model has been used to estimate the probability of voting & diagnosis failures in a set of TMR systems obtained by using combinational benchmarks as functional modules. We have shown that the presence of crosstalk faults at voter inputs may impair both the voting, and the diagnosis mechanisms. This problem has been quantified by applying a probabilistic model of crosstalk fault effects on voting and diagnosis to a set of benchmark circuits. Results show that crosstalk may create a reliability problem for TMR systems. Such a problem can be solved by using on-line testing or design for testability providing additional controllability & observability to the replicated functional units.

Crosstalk fault testing by the built‐in self‐test method with test points and phase shifters

AbstractWith the progressive decreases in size and increases in the speed of VLSI, guaranteeing signal integrity has become important. This paper focuses on crosstalk as a factor responsible for the violation of signal integrity and proposes a method of testing for crosstalk faults. The built‐in self‐test (BIST) method, which can detect crosstalk faults by using an M‐sequence of a linear feedback shift register (LFSR), has been proposed. But since the output of the LFSR is used unaltered as a random test pattern, an insufficient number of crosstalk pulses is excited and some faults escape detection. We therefore propose the use of a new testing circuit which increases the number of crosstalk pulses that are excited and makes possible the detection of faults that were previously undetectable. The new testing circuit uses test points and phase shifter circuits which can output sequences that have arbitrary delays from the M‐sequence. In addition, by changing the simulation method, it also becomes applicable to large‐scale circuits for which such simulations could not be used in the past. We evaluate the detection rate and area overhead for several benchmark circuits and show that the method is effective in detecting crosstalk faults. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 87(10): 54–65, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20108

Diagnosing crosstalk faults algorithm design and analysis in a class of dilated re-arrangeable photonic switching networks

Optical multistage interconnection networks (OMINs), based on 2 × 2 directional coupler photonic switches, play a significant role in all-optical lightwave networks. Space dilation reduces the native effect of switch crossover. This paper presents two types of dilated re-arrangeable networks extended from dilated blocking networks: a class of two cascaded dilated blocking networks, such as dilated_ blocking_ network-dilated_ blocking_ network architectures, and the other type can be extended from the dilated blocking networks, i.e. horizontal cascading (HC) or vertical stacking (VS). Optical crosstalk, an underestimated problem in OMINs, is the effect of undesirable coupling of signals between paths within a directional coupler due to its rapid aging. A switch is faulty if it causes excessive crosstalk in excess of a given threshold. Diagnosing faulty switch is essential issue in OMINs. Previous work [Inform. Sci.: Int. J. 124 (2000) 59] has developed the appropriate diagnostic algorithm for dilated blocking photonic networks. This paper devises diagnostic algorithms for dilated re-arrangeable networks, which benefits from [Inform. Sci.: Int. J. 124 (2000) 59]. The proposed algorithm is also verified in this paper.

Fault-coverage analysis techniques of crosstalk in chip interconnects

This paper addresses the problem of evaluating the effectiveness of test sets to detect crosstalk defects in system-level interconnects and buses of deep submicron (DSM) chips. The fast and accurate estimation technique will enable: 1) evaluation of different existing tests, like functional, scan, logic built-in self-test (BIST), and delay tests, for effective testing of crosstalk defects in core-to-core interconnects and 2) development of crosstalk tests if the existing tests are not sufficient, thereby minimizing the cost of interconnect testing. Based on a covering relationship we distinguish between transition tests in detecting crosstalk defects and develop an abstract crosstalk fault model for chip interconnects. With this fault model and the covering relationship, we develop a fast and efficient method to estimate the fault coverage of any general test set. We also develop a simulation-based technique to calculate the probability of occurrence of the defects corresponding to each fault, which enables the fault-coverage analysis technique to produce accurate estimates of the actual crosstalk defect coverage of a given test set. The crosstalk test and fault properties, as well as the accuracy of the proposed crosstalk coverage analysis techniques, have been validated through extensive simulation experiments. The experiments also demonstrate that the proposed crosstalk techniques are orders of magnitude faster than the alternative method of SPICE-level simulation. Finally, we demonstrate the practical applicability of the proposed fault-coverage analysis technique by using it to evaluate the crosstalk fault coverage of logic BIST tests for the system-level interconnects and buses in a digital signal processor core.

Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting

Three different techniques for simulating realistic faults generated from IC layout are discussed. Two of them deal with bridging faults, and the third one handles crosstalk faults. The simulation is performed on top of a commercial simulator and thus is very well applicable in an industrial environment. No change of the design database and only minimal changes of the test shell are required. Experimental results are reported for a library cell and a block from a full-custom design.

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects

For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to generate vectors which have high crosstalk defect coverage. However, these methods may have a prohibitively high area overhead. To reduce this overhead, existing logic BIST structures like LFSRs could be reused to deliver interconnect tests. But, as shown by our experiments, use of LFSR tests achieve poor crosstalk defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern. In this paper, we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing logic BIST structures but generates high-quality tests for interconnect crosstalk defects, while minimizing the area overhead and interconnect power consumption. The application of the LI-BIST methodology on example SoCs indicates that LI-BIST is a viable, low-cost, yet comprehensive solution for testing SoCs.

Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults

We propose a possible modification to the internal structure of scan flip-flops, which allows the online detection of delay and crosstalk faults affecting their input. Our solution allows to obtain, together with the flip-flop output datum, an indication denoting whether or not the provided datum is incorrect, because of an input crosstalk or delay fault. The proposed solution features self-checking ability with respect to a wide set of possible internal faults, including node stuck-ats, transistor stuck-ons and stuck-opens, resistive bridgings, delays, transient and crosstalk faults.

Built‐in Self‐Test for crosstalk faults in a digital VLSI

AbstractAccompanying high‐integration and high‐speed implementation of VLSI in recent years, new faults which cannot be classified in the category of conventional fault models have become a problem. Among these new faults, we will deal with crosstalk faults in this paper. Because of excitation and propagation of the crosstalk faults in the detection of these faults, two successive test vectors are required and thus their generation is difficult. Moreover, it is necessary in the sequential circuit to consider the problem of timing such as gate delay time and FF setup time in the circuit. For that reason, it has been difficult to realize a high fault coverage in the test vector generation methods proposed so far. To solve these problems, we will newly propose in this paper a Built‐In Self‐Test (BIST) method which can detect the crosstalk faults. This method can be realized by a relatively small area overhead; moreover, by adopting a circuit configuration during simulation which is different from the one during test, the simulation time is shortened. In this way, testing of large‐scale circuits has been made possible. We have performed an evaluation on the fault coverage for several benchmark circuits and shown that this method is effective for crosstalk faults. © 2002 Wiley Periodicals, Inc. Syst Comp Jpn, 33(13): 35–47, 2002; Published online in Wiley InterScience (www. interscience.wiley.com). DOI 10.1002/scj.1171

Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores

In deep-submicron technologies, long interconnects play an ever-important role in determining the performance and reliability of core-based system-on-chips (SoCs). Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive due to the need for high-speed testers. Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for system-on-chips (SoC) based on embedded processors. It enables an on-chip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC, thereby allowing at-speed testing of interconnect crosstalk defects, while eliminating the need for test overhead and the possibility of over-testing. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method.

Self-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines

We present a self-checking detection and diagnosis scheme for transient, delay, and crosstalk faults affecting bus lines of synchronous systems. Faults that are likely to result in the connected logic sampling incorrect bus data are on-line detected. The position of the affected line(s) within the considered bus is identified and properly encoded. The proposed scheme is self-checking with respect to a realistic set of possible internal faults, including node stuck-ats, transistor stuck-ons, transistor stuck-opens, resistive bridgings, transient faults, delays and crosstalks.

Diagnosing crosstalk faults in a class of dilated blocking optical multistage interconnection networks

Optical Multistage Interconnection Networks (OMINs), which are constructed by photonic switches, have been studied extensively as an important interconnecting scheme for communication and parallel computing systems. A basic element of photonic switching network is a 2×2 directional coupler with two inputs and two outputs. A crosstalk occurs, when two signal channels interact with each other, caused by the improper control of voltage, temperature and polarization along with the aging of the material. In this paper, we will focus on a specific architecture called the Dilated Blocking Networks. The characteristic of dilated blocking networks, such as Dilated Omega Network (DON), is that only one possible path can be established between any input-output pair. The two-level diagnosis algorithm is proposed to satisfy the need of this architecture. The first-order crosstalk will be detected and located in the first level. In addition, the number of unused photonic switches grows in Θ( N 2) as the size of network increases in N× N during the diagnosing crosstalk algorithm. By this property, we speed up the test by paralleling two first-order crosstalk faults at the first-level algorithm (we call it as disjoint faults). The second-level algorithm will diagnose the second- or higher-order crosstalk as well as all crosstalks will be diagnosed. Finally, we apply the diagnosing algorithm to other dilated photonic isomorphic topologies, say, Dilated Baseline Network and Dilated Banyan Network.