Crosstalk Faults Research Articles

디지털트윈을 이용한 LCD제품의 CTQ선정 및 Crosstalk 불량예측

Purpose: This paper proposes a defect prediction method using digital twins that may overcome the defect detection limitations arising from model-based and data-driven approaches.BRMethods: To apply the digital twin concept to LCD products, we propose a procedure for the fabrication and validation of digital twins. The crosstalk defect, which is one of the major LCD defects, can be predicted using the developed digital twin. Virtual experimentation conducted based on that were carried out to identify and validate the control parameters.BRResults: Using the digital twin of LCD products, it was possible to review the process’ CTQ selection adequacy and control specifications. Additionally, by applying the CTQ data of the process to the digital twin, the occurrence of crosstalk defects became predictable.BRConclusion: It has been confirmed through case studies that the defect prediction method using digital twins can be effectively applied to the manufacturing industry. Further research on the diversification of defect prediction, digital twin production tools simplification, and real-time connection system of process CTQ data may be conducted.

UP-Down OLC: New One-Lambda Crosstalk Avoidance Code Design Based on 5-Wire Model

Crosstalk fault avoidance codings (CACs) is extensively utilized. Among promising existing CACs methods, the one which has attracted much attention due to worst-case crosstalk fault delay prevention is One-Lambda Codes (OLCs). Unfortunately, two challenging issues are coming their way: 1- Exact model is required to estimate an exact delay of wires to provide accurate OLCs. 2- OLCs codec suffers from high energy consumption and overhead caused by critical path and area occupation. In this research, an accurate probability model is introduced to overcome these problems by Accurate Crosstalk Model (ACM) prediction. If crosstalk faults show up, ACM can estimate the communication channels delay by using 5- wire delay. It can help to improve the recently proposed analytical model that suffers from a lack of accuracy. Next, we present an accurate UP-Down OLC (UD-OLC) based on the numeral system and can eliminate transition patterns, including OLC-induced patterns, completely. In comparison with the other state-of-the-art OLCs, the UD-OLC mapping algorithm effectively alleviates wires energy consumption and average latency by up to 61% and 27%. Experimental results also reveal that this an overhead efficient numeral-based method benefits from the overhead degradation in terms of dynamic power, area, and critical path by up to 52%, 45%, and 20%, respectively when we compared it to the others.

JCI-CAC: An Efficient Crosstalk Avoidance Code Considering Joint Capacitive and Inductive Effects

Capacitive coupling and inductive coupling are the two main factors in the occurrence of crosstalk fault in the communication bus. Among the various methods for reducing crosstalk fault, Crosstalk Avoidance Codes (CAC) codes are effective. However, with technology scaling, CACs are not able to prevent inductive effects. The proposed CACs methods are mainly based on capacitive coupling and do not consider inductive effects. To overcome this issue, a coding method is presented to avoid crosstalk fault called Joint Capacitive and Inductive CAC (JCI-CAC). The JCI-CAC coding reduces crosstalk faults by removing patterns of inductive coupling as ’11111’ and ’00000’ and capacitive coupling as ’10101’ and ’01010’. The JCI-CAC offers a new method to generate a new numerical system for data encoding that has a low computational overhead so that it can be used for any desired width of the communication bus. The simulation results of the proposed JCI-CAC mechanism are investigated in different criteria of delay, power consumption and area overhead. The simulation results provide less power consumption in JCI-CAC than other recent approaches. There have also been improvements in overhead area and critical paths in JCI-CAC coding. The main novelty of this paper is to provide a new numerical system and a new coding algorithm with minimum cell area overhead and power consumption, considering inductance coupling in addition to capacitive coupling. Based on simulation results, power consumption of JCI-CAC in the 8-bit and 16-bit bus is reduced by up to 20% compared to SOTA and FPF (PS-Fibo, S2AP, Improved Fibo-CAC, Fibo-CAC) codings. Also, cell area overhead in JCI-CAC compared to SOTA coding in an 8-bit bus is reduced by 4.8%.

ST-CAC: a low-cost crosstalk avoidance coding mechanism based on three-valued numerical system

Appearances of specific transition patterns during data transfer in bus lines of modern high-performance computing systems, such as communicating structures of accelerators for deep convolutional neural networks, commercial Network on Chips, and memories, can lead to crosstalk faults. With the shrinkage of technology size, crosstalk faults occurrence boosts and leads to degradation of reliability and performance, as well as the increasing power consumption of lines. One effective way to alleviate crosstalk faults is to avoid the appearance of these specific transition patterns by using numerical-based crosstalk avoidance codes (CACs). However, a serious problem with numerical-based CACs is their overheads in terms of required additional bus lines for representing code words. To solve this problem, in this paper we present a novel CAC that is based on the use of three symbols (three-value) to represent the code words in the bus lines, rather than classical binary CACs based on binary, i.e., 0 and 1 symbols. Our proposed CAC, named summation-based tri-value crosstalk avoidance code (ST-CAC), reduces the worst-case delay in bus lines with respect to binary CACs, and it can efficiently be applied to any arbitrary channel width of lines. The use of three symbols to represent code words in ST-CAC enables to increase the number of code words of a numerical system without increasing the number of required bus lines significantly. The experimental results show that CACs based on the use of three symbols can reduce the number of additional lines compared to binary CACs by 33%. Moreover, we show in the paper, that the delay of wires in the presence our ST-CAC can reduce by 33% with respect to state-of-the-art binary value CACs.

On-Fly-TOD: an efficient mechanism for crosstalk fault reduction in WNoC

Hierarchical architecture of Wireless Network on Chips (WNoCs) composes of wired level and wireless level. In this architecture, subnetworks in wired level are connected by wireless. One of the main reliability challenges in the wired level of WNoC architecture is the crosstalk fault. Crosstalk fault occurs among the long and adjacent wires of wired level of WNoC due to tandem data traversal. Triple Opposite Directions (TODs) patterns are the worst data traversal patterns that impose the highest intensity effects on wires. To solve this problem, this paper presents a mechanism called On-Fly-TOD. In the architecture of the proposed mechanism, subnetworks are not only connected by a wireless level, but also by wired levels. In other words, this architecture uses the inherent characteristic of WNoCs by sending packets with TOD patterns by the wireless level. In this mechanism, tandem flits are counted and flits with high amounts of TODs are sent using wireless level. Simulations show that On-Fly-TOD mechanism provides a trade-off between performance, power consumption and reliability issues. In addition, this architecture suitably scales with the ever-increasing number of on-chip processing elements (PEs) which guarantees a minimum number of hop counts between any source and destination without using long wires as the number of on-chip PEs increases.

Design of Test Pattern Generator for Testing Crosstalk Faults in TSVs

Design of Test pattern generator to test crosstalk faults in Through Silicon Vias (TSV) in three dimensional integrated circuits presented in this paper. A well-known test pattern generation model for testing crosstalk called as Maximum aggressor fault model is adopted in the design. The finite state machine diagram for design of TPG presented in reference [1] is modified and the complete design of TPG is discussed in this paper. Verilog HDL Simulation and synthesis results of the proposed Test pattern generator is discussed.

AM3D: An accurate crosstalk probability modeling to predict channel delay in 3D ICs

Migration from Two Dimensional Integrated Circuits (2D ICs) to Three Dimensional Integrated Circuits (3D ICs) reduces the delay due to the shorter wire length between sender and receiver. However, Through-Silicon-Vias (TSVs) that connect layers in the structure of 3D ICs can seriously increase the delay due to capacitance coupling between TSVs and lead to crosstalk fault. The severity of crosstalk faults depends on transitions appearing on TSVs that is called transition patterns. To propose an efficient crosstalk tackling mechanisms in 3D ICs, an accurate probability analytical model is required to predict the delay caused by TSVs (3D ICs) in the attendance of these transition patterns. In this regard, this paper proposes an accurate crosstalk probability model for 3D ICs called AM3D that estimates the latency of communication channels of 3D ICs in the attendance of crosstalk faults. The model is applicable for both non-protected TSVs and TSVs which are protected by crosstalk mitigation mechanisms. In order to accredit our proposed model, various SPICE simulations are conducted and obtained outcomes in different benchmarks are compared with extracted results from AM3D. Comparisons present an average of 1.81% discrepancies between the time delay obtained from SPICE simulations and time delay calculated by our proposed model.

OP-Fibo: An efficient Forbidden Pattern Free CAC design

Occurring crosstalk fault between wires is among the significant reliability challenges in transferring data between Processing Elements (PEs). Crosstalk fault occurs due to inter-wire coupling capacitances based on the appeared transition patterns on the channel. Among these transition patterns, Triplet Opposite Direction (TOD) causes the worst crosstalk effects on the transferred flits in the channels of NoCs. Forbidden Pattern Free Crosstalk Avoidance Codes (FPF-CACs) can efficiently omit TODs. However, state-of-the-art FPF-CAC has ambiguity in its mapping algorithm. This problem leads to generating more than one code word for some data words. To solve this problem, this paper aims to reduce crosstalk fault by proposing a FPF-CAC called Omissive Penultimate-Fibo (OP-Fibo). OP-Fibo benefits ambiguity-free numerical system and mapping algorithm that can generate unique code words for all of the data words and can save additional wires. Evaluations indicate that the proposed numerical system can be utilized in wires with any arbitrary channel width and also, can significantly improve the reliability with better overheads with respect to recently proposed FPF-CAC.

An efficient and low power one-lambda crosstalk avoidance code design for network on chips

Crosstalk faults occurring in wires of Networks on Chip (NoCs) can seriously threaten the reliability of data transfer. One efficient way to tackle crosstalk faults is numeral-based Crosstalk Avoidance Codes (CACs). Numeral-based CACs reduce crosstalk faults by preventing specific transition patterns to occur. One-Lambda Codes (OLCs) are the most efficient types of CACs. However, the codec of OLCs imposes overheads including power consumption, critical path and area occupation to the routers of NoCs. To find overhead-efficient OLCs, this paper proposes an Algorithm for Generating OLC Numeral systems (AGON). AGON provides a tradeoff for designers in selecting overhead-efficient OLCs. Using AGON, an efficient numeral-based OLC called Subtraction-based-Numeral (Sub-Num) is proposed that benefits the Numeral system that can omit OLC-induced transition patterns completely. In addition, the mapping algorithm of Sub-Num can reduce the overheads of codec more efficiently than the other state-of-the art OLCs. Evaluation results using SPICE and VHDL simulations show that Sub-Num reduces power consumption and average delay of wires by 10% and 9%, and also overheads of codecs including dynamic power consumption, critical path and area occupation by 52%, 51% and 21%, respectively as compared to the state-of-the-art numeral-based OLC.

Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges

Through silicon vias (TSVs) play an important role in 3-D chip integration. Effective and efficient testing for correct operation of TSVs is essential for 3-D integrated circuit design. This paper addresses the post-bond test and diagnosis of crosstalk faults among TSVs considering different impact ranges, and proposes a TSV grouping method for rectangular and hexagonal TSV placements such that as many TSVs as possible are tested simultaneously. Based on the results of the TSV grouping, we implement a high-efficiency, low-area-overhead TSV test architecture that reuses the existing boundary scan or IEEE 1500 wrapper cells typically present for prebond testing. Experimental results show the short test and diagnosis time as well as the low area overhead of the proposed test architecture.

An efficient numerical-based crosstalk avoidance codec design for NoCs

With technology scaling, crosstalk fault has become a serious problem in reliable data transfer through Network on Chip (NoC) channels. The effects of crosstalk fault depend on transition patterns appearing on the wires of NoC channels. Among these patterns, Triplet Opposite Direction (TOD) imposes the worst crosstalk effects. Crosstalk Avoidance Codes (CACs) are the overhead-efficient mechanisms to tackle TODs. The main problem of CACs is their high imposed overheads to NoC routers. To solve this problem, this paper proposes an overhead-efficient coding mechanism called Penultimate-Subtracted Fibonacci (PS-Fibo) to alleviate crosstalk faults in NoC wires. PS-Fibo coding mechanism benefits the novel numerical system that not only completely removes TODs but also, is applicable to a wide range of NoC channel widths. The PS-Fibo coding mechanism is evaluated using BookSim-2 and VHDL-based simulations in the terms of codec efficiency on the crosstalk fault reduction, codec power consumption, codec area occupation and network performance. Evaluation results, carried out for a wide range of NoC channel widths indicate that PS-Fibo can improve power consumption and area occupations of codec and NoC performance with respect to the other state-of-the-art coding mechanisms.

On designing an efficient numerical-based forbidden pattern free crosstalk avoidance codec for reliable data transfer of NoCs

Inter-wire coupling capacitances can lead to crosstalk fault that is strongly dependent on the transition patterns appearing on the wires. These transition patterns can cause mutual influences between adjacent wires of NoCs and as a result threaten the reliability of data transfer seriously. To increase the reliability of NoCs against the crosstalk fault, Forbidden Pattern Free (FPFs) codes are used. To generate FPF codes, numerical systems are among the overhead-efficient mechanisms. The algorithms of numerical systems have direct effect on the amounts of the codec overheads including power consumption, area occupation and performance of NoCs. To find an overhead-efficient numerical system, this paper proposes an Algorithm for Generating FPF Numerical systems (AGFN). AGFN can provide a tradeoff for designers in selecting overhead-efficient FPF numerical systems. Using this algorithm, collection of Fibonacci-based and non-Fibonacci-based numerical systems can be generated. Then, using AGFN, non-Fibonacci-based FPF numerical system called Summation-based-Subtracted-Added-Penultimate (S2AP) is generated. Experimental results indicate that S2AP not only reduces the worst crosstalk effects by completely removing the Triplet Opposite Direction (TOD) transitions, but also it can significantly improve power consumption, area occupation and critical path overheads of codec with respect to the other state-of-the-art FPF codes.

Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim

With the shrinking feature size and increasing aspect ratios of interconnects in DSM chips, the coupling noise between adjacent interconnects has become a major signal integrity (SI) issue, giving rise to crosstalk failures. In older technologies, SI issues have been ignored because of high noise immunity of the CMOS circuits and the process technology. However, as CMOS technologies lower down the supply voltage as well as the threshold voltage of a transistor, digital designs are more and more susceptible to noise because of the reduction of noise margin. The genetic algorithms (GAs) have been applied earlier in different engineering disciplines as potentially good optimization tools and for various applications in VLSI design, layout, EDIF digital system testing and also for test automation, particularly for stuck-at-faults and crosstalk-induced delay faults. In this paper, an elitist GA has been developed that can be used as an ATPG tool for generating the test patterns for crosstalk-induced faults between on-chip aggressor and victim and as well as for stuck-at-faults. It has been observed that the elitist GA, when the fitness function is properly defined, has immense potential in extracting the suitable test vectors quickly from randomly generated initial patterns.

TEST GENERATION AND SIMULATION FOR CROSSTALK FAULTS

The main models of crosstalk faults are defined: 1) induced positive and negative pulses, 2) induced delays. The purpose of the work is to increase the effectiveness of the methods of constructing checking tests for digital systems based on an evolutionary approach and models of non-const fault. Formalized statement of the problem of test generation for a single crosstalk faults-induced pulses and delays. It is shown that this problem is reduced to solving a system of logic equations in the multi-valued alphabet. The 8-valued alphabet and multivalued functions for basic gates are defined. Simulation method was developed in the 8-valued alphabet for crosstalk faults. On this basis, the genetic algorithm is proposed for test generation of single cross-faults. The test generation problem for fault-induced delay is formalized A genetic algorithm of test generation for fault-induced is proposed. Developed algorithms and software for test generation for crosstalk faults, which improve the quality of test generation by using evolutionary techniques. The approbation of the developed methods is implemented at circuits of international catalogs ISCAS85, ISCAS89, which showed an increase in the completeness of tests by 15%.

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

Abstract The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built-in blocks within a System-on-Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of the previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitive nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence

An Efficient Methodology for Multiple Fault Diagnosis Including Crosstalk Defects Using Multi-Objective Particle Swarm Optimizer

Fault diagnosis plays an important role in improving yield of the VLSI IC manufacturing process. In this paper, we propose a multiple-fault-diagnosis methodology based on the analysis of failing primary outputs and the structure of the circuit under diagnosis. This work analyzes multiple faults simultaneously based on multiple fault simulation in a particle swarm optimization environment. Here, particle swarm optimization is proposed as a multi-objective optimization algorithm by considering crosstalk effect also. Experimental results show that our technique is highly efficient and effective in terms of diagnosability and diagnostic resolution. This approach does not put any restriction on the number of simultaneous faults and has approximately linear time complexity for multiple faults.

A Test Method and Test Codes Generator for Improved HT Fault Model Based on NoC

NoC is a expand for SoC.The architecture of NoC is huge and complex,it leads to the crosstalk fault between internal transmission of NoC increasingly serious. Crosstalk serious impact on the signal integrity of on-chip system.A new test codes generator was designed by PSpice simulation software based on improved HT model. The generator was composed of a 16-bit counter and a 16-bit data selector.The generator was tested by PSpice software,the result showed that it satisfied the test requirements and had the advantage of portable. A crossstalk test method was proposed in this paper,we used this method on a test circuit,the result showed that the method could reduce the number of tests and save resource effectively.

Detection of Crosstalk Faults in Field Programmable Gate Arrays (FPGA)

In this work, a Built-in-Self-Test (BIST) technique has been proposed to detect crosstalk faults in FPGA and run time congestion and to provide the crosstalk aware router for FPGA. The proposed BIST circuits require less overhead as compared to earlier techniques. The proposed detector can detect any logic hazard or delay due to crosstalk. A technique has also been proposed to avoid the crosstalk by routing the path in such a way that no interference occurs between the interconnects. The proposed router has achieved better utilization of routing resource to determine the net as compared to the earlier works. The proposed scheme is simulated in MATLAB and verified using Xilinx ISE tools and Modelsim 6.0. The router is implemented by using class provided by JBits for Xilinx, Vertex-II FPGA. It has been found that the results are quite encouraging.

A single-photon fault-detection method for nanocircuits that use GaN material

As the complexity of nanocircuits continues to increase, developing tests for them becomes more difficult. Failure analysis and the localization of internal test points within nanocircuits are already more difficult than for conventional integrated circuits. In this paper, a new method of testing for faults in nanocircuits is presented that uses single-photon detection to locate failed components (or failed signal lines) by utilizing the infrared photon emission characteristics of circuits. The emitted photons, which can carry information about circuit structure, can aid the understanding of circuit properties and locating faults. In this paper, in order to enhance the strength of emitted photons from circuit components, test vectors are designed for circuits’ components or signal lines. These test vectors can cause components to produce signal transitions or switching behaviors according to their positions, thereby increasing the strength of the emitted photons. A multiple-valued decision diagram (MDD), in the form of a directed acrylic graph, is used to produce the test vectors. After an MDD corresponding to a circuit is constructed, the test vectors are generated by searching for specific paths in the MDD of that circuit. Experimental results show that many types of faults such as stuck-at faults, bridging faults, crosstalk faults, and others, can be detected with this method.

Study on crosstalk fault model and testing for SoC inter-core interconnects

Signal integrity testing for inter-cores in SoC has become an important issue within DSM manufacturing technology and GHz working frequency of VLSI. A new testing method for SoC inter-core interconnects is presented in this paper. Properties and principles are obtained based on analysis of crosstalk characteristics for tri-state and bi-directional interconnects. The reduction algorithm of tri-state and bi-direction interconnect is proposed with the properties and principles above. Primary and secondary factors of crosstalk are analysed based on orthogonal design, and then test vectors for interconnects are generated gradually. Finally experiments are implemented, and simulation results show the effectiveness of this method.