Crosstalk Avoidance Code Research Articles

Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array

The through silicon via (TSV) is one of the important enabling technologies of stacked 3D ICs. However, the crosstalk is generated when signals are transmitted through the closely clustered TSVs due to the coupling effect. The crosstalk avoidance code (CAC) techniques have attracted great concerns in recent years, for the TSV-to-TSV crosstalk deteriorates the signal integrity. Nevertheless, the CAC techniques usually require specific shape of TSV array, e.g. 3×N array. This work proposes a crosstalk suppression scheme combining the CAC method and the static shielding technique, named as Mosaic-3C1S. The proposed scheme is able to be applied to arbitrary rectangular TSV arrays. In the proposed scheme, the 2×2 TSV sub-array which contains three signal TSVs and one shielding TSV, is used as the basic unit to tile the rectangular TSV array. The CAC method is applied to the signal TSVs in the 2×2 sub-arrays, and the raw data are transmitted by the rest boundary TSVs, if any. In order to further reduce the bit overhead, a triangular numeral system based CAC, named as TNS-CAC, is proposed and applied. The simulation results show that the proposed TNS-CAC has advantages on bit overhead and codec area. And the proposed Mosaic-3C1S scheme with TNS-CAC is able to suppress the crosstalk between TSVs to 6C level. The bit overhead of the proposed scheme is between 25% 45%, which is lower than that of the previous CAC methods for TSV arrays for the most cases.

JCI-CAC: An Efficient Crosstalk Avoidance Code Considering Joint Capacitive and Inductive Effects

Capacitive coupling and inductive coupling are the two main factors in the occurrence of crosstalk fault in the communication bus. Among the various methods for reducing crosstalk fault, Crosstalk Avoidance Codes (CAC) codes are effective. However, with technology scaling, CACs are not able to prevent inductive effects. The proposed CACs methods are mainly based on capacitive coupling and do not consider inductive effects. To overcome this issue, a coding method is presented to avoid crosstalk fault called Joint Capacitive and Inductive CAC (JCI-CAC). The JCI-CAC coding reduces crosstalk faults by removing patterns of inductive coupling as ’11111’ and ’00000’ and capacitive coupling as ’10101’ and ’01010’. The JCI-CAC offers a new method to generate a new numerical system for data encoding that has a low computational overhead so that it can be used for any desired width of the communication bus. The simulation results of the proposed JCI-CAC mechanism are investigated in different criteria of delay, power consumption and area overhead. The simulation results provide less power consumption in JCI-CAC than other recent approaches. There have also been improvements in overhead area and critical paths in JCI-CAC coding. The main novelty of this paper is to provide a new numerical system and a new coding algorithm with minimum cell area overhead and power consumption, considering inductance coupling in addition to capacitive coupling. Based on simulation results, power consumption of JCI-CAC in the 8-bit and 16-bit bus is reduced by up to 20% compared to SOTA and FPF (PS-Fibo, S2AP, Improved Fibo-CAC, Fibo-CAC) codings. Also, cell area overhead in JCI-CAC compared to SOTA coding in an 8-bit bus is reduced by 4.8%.

UP-Down OLC: New One-Lambda Crosstalk Avoidance Code Design Based on 5-Wire Model

Crosstalk fault avoidance codings (CACs) is extensively utilized. Among promising existing CACs methods, the one which has attracted much attention due to worst-case crosstalk fault delay prevention is One-Lambda Codes (OLCs). Unfortunately, two challenging issues are coming their way: 1- Exact model is required to estimate an exact delay of wires to provide accurate OLCs. 2- OLCs codec suffers from high energy consumption and overhead caused by critical path and area occupation. In this research, an accurate probability model is introduced to overcome these problems by Accurate Crosstalk Model (ACM) prediction. If crosstalk faults show up, ACM can estimate the communication channels delay by using 5- wire delay. It can help to improve the recently proposed analytical model that suffers from a lack of accuracy. Next, we present an accurate UP-Down OLC (UD-OLC) based on the numeral system and can eliminate transition patterns, including OLC-induced patterns, completely. In comparison with the other state-of-the-art OLCs, the UD-OLC mapping algorithm effectively alleviates wires energy consumption and average latency by up to 61% and 27%. Experimental results also reveal that this an overhead efficient numeral-based method benefits from the overhead degradation in terms of dynamic power, area, and critical path by up to 52%, 45%, and 20%, respectively when we compared it to the others.

A Numeral System Based Framework for Improved One-Lambda Crosstalk Avoidance Code Using Recursive Symmetry Formula

A Numeral System Based Framework for Improved One-Lambda Crosstalk Avoidance Code Using Recursive Symmetry Formula

ST-CAC: a low-cost crosstalk avoidance coding mechanism based on three-valued numerical system

Appearances of specific transition patterns during data transfer in bus lines of modern high-performance computing systems, such as communicating structures of accelerators for deep convolutional neural networks, commercial Network on Chips, and memories, can lead to crosstalk faults. With the shrinkage of technology size, crosstalk faults occurrence boosts and leads to degradation of reliability and performance, as well as the increasing power consumption of lines. One effective way to alleviate crosstalk faults is to avoid the appearance of these specific transition patterns by using numerical-based crosstalk avoidance codes (CACs). However, a serious problem with numerical-based CACs is their overheads in terms of required additional bus lines for representing code words. To solve this problem, in this paper we present a novel CAC that is based on the use of three symbols (three-value) to represent the code words in the bus lines, rather than classical binary CACs based on binary, i.e., 0 and 1 symbols. Our proposed CAC, named summation-based tri-value crosstalk avoidance code (ST-CAC), reduces the worst-case delay in bus lines with respect to binary CACs, and it can efficiently be applied to any arbitrary channel width of lines. The use of three symbols to represent code words in ST-CAC enables to increase the number of code words of a numerical system without increasing the number of required bus lines significantly. The experimental results show that CACs based on the use of three symbols can reduce the number of additional lines compared to binary CACs by 33%. Moreover, we show in the paper, that the delay of wires in the presence our ST-CAC can reduce by 33% with respect to state-of-the-art binary value CACs.

An efficient and low power one-lambda crosstalk avoidance code design for network on chips

Crosstalk faults occurring in wires of Networks on Chip (NoCs) can seriously threaten the reliability of data transfer. One efficient way to tackle crosstalk faults is numeral-based Crosstalk Avoidance Codes (CACs). Numeral-based CACs reduce crosstalk faults by preventing specific transition patterns to occur. One-Lambda Codes (OLCs) are the most efficient types of CACs. However, the codec of OLCs imposes overheads including power consumption, critical path and area occupation to the routers of NoCs. To find overhead-efficient OLCs, this paper proposes an Algorithm for Generating OLC Numeral systems (AGON). AGON provides a tradeoff for designers in selecting overhead-efficient OLCs. Using AGON, an efficient numeral-based OLC called Subtraction-based-Numeral (Sub-Num) is proposed that benefits the Numeral system that can omit OLC-induced transition patterns completely. In addition, the mapping algorithm of Sub-Num can reduce the overheads of codec more efficiently than the other state-of-the art OLCs. Evaluation results using SPICE and VHDL simulations show that Sub-Num reduces power consumption and average delay of wires by 10% and 9%, and also overheads of codecs including dynamic power consumption, critical path and area occupation by 52%, 51% and 21%, respectively as compared to the state-of-the-art numeral-based OLC.

Reduction of Power Consumption using Joint Low Power Code with Crosstalk Avoidance Code in Case of Crosstalk and Random Burst Errors

When technology is scaling down, reliability and power issues are arise in the intercommunication of System on Chip (SoC). The intercommunication links are suffers with various noise sources like crosstalk, temperature variation and voltage deflection which lead to communication link failure. To get reliable system, the strong error detection and correction codes are required. In this proposed work, Crosstalk avoidance code detects and corrects of one bit error, two bit error and some of three bit errors. The Hybrid Automatic Re-transmission Request is also used when the CAC detects the burst error of three. Apart from this, the Low Power Codes are used to get low power consumption using Bus Invert (BI) technique in proposed work. The LPC code reduces the power consumption of interconnection wires using reducing switching activity. The performance of proposed work evaluated in Xilinx 14.7 in Vertex-6 Field Programmable Gated Array (FPGA) device. The proposed work is calculated of power consumption of codec module and interconnection wire, delay of CAC and LPC code and link swing voltage. This work provides 11.7% improvement in power consumption and presents high reliability than JTEC. The energy dissipation of wires in the proposed work is decreased 23.5% than un-coded schemes.

Modified weighted code with bit invert approach to minimize crosstalk in network on chip links

In this paper, an efficient CODEC design is proposed for generating forbidden pattern free crosstalk avoidance code. The proposed modified weighted code with bit invert (MW-BI) approach minimize the worst case cross talk delay by avoiding the triplet opposite direction (TOD) transition entirely in the Network on chip links. The MW-BI CODEC is implemented using synopsys design compiler tool and mapped on SAED 90 nm technology library. The implementation results show that the proposed MW-BI CODEC method decreases the Total Area by 30.05, 41.48 and 34.71% compared to already existing FIBO, IMP FIBO and S2AP CODEC respectively, and also achieves less Total Dynamic Power of 43.40, 53.72 and 50.92% than others. And also the proposed technique reduces the Cell Leakage Power by 16.33, 17.23 and 29.39% when compared to other cross talk avoidance coding methods.

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias

Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk noise between the neighboring TSVs, and result in the extra delay and the deterioration of signal integrity. For a 3 × 3 TSV array, the severity of crosstalk noise in the center victim TSV is classified into 11 levels, which is defined as 0C to 10C from low noise to high noise, depending on the combinations of the digital patterns applied to the TSV array. An enhanced code based on the Fibonacci number system (FNS) to suppress the crosstalk noise below 6C level is proposed, in which both the redundancy of numbers and the nonuniqueness of Fibonacci-based binary codeword are utilized to search the proper codeword. Experimental results show that the proposed technique decreases about 22% latency of TSVs comparing with the worst crosstalk cases. This technique is applicable in the large-scale TSV array for it has a quasi-linear hardware overhead, and its system overhead is less than that of the 3-D 4-LAT counterpart if the data width is greater than 18, and it has good usability for it consumes less power per TSV and achieves lower bit error rate at the interested frequency range comparing with that of the original FNS coding technique.

Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link

As the technology scales down, shrinking geometry and layout dimension, on- chip interconnects are exposed to different noise sources such as crosstalk coupling, supply voltage fluctuation and temperature variation that cause random and burst errors. These errors affect the reliability of the on-chip interconnects. Hence, error correction codes integrated with noise reduction techniques are incorporated to make the on-chip interconnects robust against errors. The proposed error correction code uses triplication error correction scheme as crosstalk avoidance code (CAC) and a parity bit is added to it to enhance the error correction capability. The proposed error correction code corrects all the error patterns of one bit error, two bit errors. The proposed code also corrects 7 out of 10 possible three bit error patterns and detects burst errors of three. Hybrid Automatic Repeat Request (HARQ) system is employed when burst errors of three occurs. The performance of the proposed codec is evaluated for residual flit error rate, codec area, power, delay, average flit latency and link energy consumption. The proposed codec achieves four magnitude order of low residual flit error rate and link energy minimization of over 53 % compared to other existing error correction schemes. Besides the low residual flit error rate, and link energy minimization, the proposed codec also achieves up to 4.2 % less area and up to 6 % less codec power consumption compared to other error correction codes. The less codec area, codec power consumption, low link energy and low residual flit error rate make the proposed code appropriate for on chip interconnection link.

A Novel Encoding Scheme for Cross-Talk Effect Minimization Using Error Detecting and Correcting Codes

In this paper a new bus encoding method presented for reducing crosstalk effects, which can avoid crosstalk and provide error- correcting as well. This method find a subset from cross talk avoidance code (CAC) to provide error correction which allows to reduce the crosstalk- induced delay with buses implementing an error detecting/correcting code. Here we propose Fibonacci representation of single error correcting codes using Hamming code to avoid crosstalk induced delay. Extra wires for checking bus are never required in the proposed method and it can also improve bus performance and reduce power dissipation. We give algorithms for obtaining optimal encodings and present a particular class of error free codes. Conversely other bus encoding techniques have been used to prevent crosstalk but don't correct error. 

Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects

With the shrink of technology to the nanometer scale, network-on-chip (NOC) has become a reasonable solution for connecting many cores on a single chip. It suffers however from increasingly serious interconnect crosstalk effects, which constrain the overall performance of NOC systems. In this paper, a crosstalk tolerance method is proposed for reducing bus delay on NOC interconnects. Crosstalk-induced latency is predicted by analyzing the possible crosstalk effects of adjacent patterns stored in an NOC router. Transition times of selected bits are then adjusted to relieve these predicted crosstalk-induced effects. Experimental results on interconnects show that the proposed method can achieve the same bus delay reduction as the insertion of extra shielding wires into two adjacent wires, while the proposed method requires no extra wires. Compared with previous methods using a dual rail code, a crosstalk avoidance code, and/or a variable clock, the proposed approach provides a larger reduction of bus delay with less area overhead.

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

With the shrink of the technology into nanometer scale, network-on-chip (NOC) has become a reasonable solution for connecting plenty of IP blocks on a single chip. But it suffers from both crosstalk effects and single event upset (SEU), especially crosstalk-induced delay, which may constrain the overall performance of NOC. In this paper, we introduce a reliable NOC design using a code with the capability of both crosstalk avoidance and single error correction. Such a code, named selected crosstalk avoidance code (SCAC) in our previous work, joins crosstalk avoidance code (CAC) and error correction code (ECC) together through codeword selection from an original CAC codeword set. It can handle possible error caused by either crosstalk effects or SEU. When designing a reliable NOC, data are encoded to SCAC codewords and can be transmitted rapidly and reliably across NOC. Experimental results show that the NOC design with SCAC achieves higher performance and is reliable to tolerate single errors. Compared with previous crosstalk avoidance methods, SCAC reduces wire overhead, power dissipation and the total delay. When SCAC is used in NOC, it can save 20% area overhead and reduce 49% power dissipation.

Efficient On-Chip Crosstalk Avoidance CODEC Design

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Interconnect delay has become a limiting factor for circuit performance in deep sub-micrometer designs. As the crosstalk in an on-chip bus is highly dependent on the data patterns transmitted on the bus, different crosstalk avoidance coding schemes have been proposed to boost the bus speed and/or reduce the overall energy consumption. Despite the availability of the codes, no systematic mapping of datawords to codewords has been proposed for CODEC design. This is mainly due to the nonlinear nature of the crosstalk avoidance codes (CAC). The lack of practical CODEC construction schemes has hampered the use of such codes in practical designs. This work presents guidelines for the CODEC design of the “forbidden pattern free crosstalk avoidance code” (FPF-CAC). We analyze the properties of the FPF-CAC and show that mathematically, a mapping scheme exists based on the representation of numbers in the Fibonacci numeral system. Our first proposed CODEC design offers a near-optimal area overhead performance. An improved version of the CODEC is then presented, which achieves theoretical optimal performance. We also investigate the implementation details of the CODECs, including design complexity and the speed. Optimization schemes are provided to reduce the size of the CODEC and improve its speed. </para>