NMOS Cross-coupled Pair Research Articles

Low Phase Noise Oscillator Design Using Degenerate Band Edge Ladder Architectures

A new approach based on a strong degeneracy state to design oscillators that exhibit low phase noise and low power consumption is presented. A 100-MHz oscillator is designed using a periodic structure based on a degenerate band edge that is augmented with an NMOS cross-coupled pair. The analysis and simulation results show 16 dB phase noise improvement compared to oscillators based on a conventional single-ladder periodic structure. It is also shown that this oscillator dissipates less power than a conventional LC oscillator that requires a buffer to drive a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50\Omega $ </tex-math></inline-formula> load.

A Dual-Band Transformer-Coupled Notch Filter Mixer for 2.45-/5.2-GHz WLAN Application

This paper presents a dual-band down-conversion mixer with image rejection feature using transformer-coupled notch filter for 2.45-/5.2-GHz WLAN application. A single center-tapped transformer is integrated to form two differential series inductor–capacitor (LC) resonators as a filter circuit to create attenuation at the image frequencies in eliminating the signal distortion caused by the image signals. Furthermore, an NMOS cross-coupled pair was adopted in the notch filter to improve the image rejection capability due to the presence of negative resistance. Simulated on a standard 130nm CMOS process, the proposed transformer-coupled notch filter mixer achieves a conversion gain of 15.3/10.7 dB, input-referred third-order interception point (IIP3) of − 6.8/− 2.0 dBm and a noise figure of 8.8/14.8 dB for an input RF of 2.45/5.2 GHz with an IF of 500 MHz. The notch filter mixer consumes 5.5 mW of power from a supply voltage of 1.2 V.

High performance 9T adiabatic SRAM and novel stability characterization using pole zero placement

Stability of memory cells always considered as a most significant figure for defining the logic data at output terminals. And the value of logic data is influenced due to the dominance of leakage component at deep submicron technology. Stability analysis and leakage issues of new 9T adiabatic static random access memory (SRAM) cells is presented using the technique of pole zero concept. With the help of flow graph characteristic of memory cell is modeled and validated using MATLAB tool. The elementary cell of proposed SRAM resembles behavior of 4T-SRAM consisting of two high load resistors constructed of PMOS and cross-coupled NMOS pair. NMOS switch is used to restrict short circuit current and two gradually rising and falling wave pulses with controlled switching current flow. The simulation is carried out at 180 nm technology and it has been found that the average power dissipation of the proposed SRAM reduces by a factor of 41 with no performance degradation and energy is efficiently recovered using adiabatic and body biasing technique.

Wideband Divide-by-4 Injection-Locked Frequency Divider Using Harmonic Mixer

This letter presents a wide locking range divide-by-4 LC injection-locked frequency divider (ILFD) implemented in the TSMC 0.18- $\mu \text{m}$ 1P6M CMOS process. The single-stage divide-by-4 ILFD uses harmonic mixer and overlapped locking ranges to emulate a wide locking range. At the drain–source bias of 0.8 V, the ILFD-core power consumption is 7.09 mW. At the incident power of 0 dBm, the maximum locking range of the divide-by-4 ILFD is 6 GHz (37.5%) from 13 to 19 GHz. The ILFD comprises a capacitive cross-coupled nMOS pair and two shunt fourth-order RLC resonators. The die area is $1.008\times1.182$ mm $^{{{2}}}$ .

Divide-by-2 injection-locked frequency divider implemented with two shunt 4th-order LC resonators

A triple-band divide-by-2 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt 4th order LC resonators to form a 6th order resonator with three resonant frequencies. Measured data has shown that the ILFD has three locking ranges at fixed bias condition or by varactor bias switching.

A Triple-Band Voltage-Controlled Oscillator Using Two Shunt Right-Handed 4th-Order Resonators

A triple-band (TB) oscillator was implemented in the TSMC 0.18 ㎛ 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt 4SUPth/SUP order LC resonators to form a 6SUPth/SUP order resonator with three resonant frequencies. The oscillator uses the varactors for band switching and frequency tuning. The core current and power consumption of the high (middle, low)- band core oscillator are 3.59(3.42, 3.4) ㎃ and 2.4(2.29, 2.28) ㎽, respectively at the dc drain-source bias of 0.67V. The oscillator can generate differential signals in the frequency range of 8.04-8.68 ㎓, 5.82-6.15 ㎓, and 3.68-4.08 ㎓. The die area of the triple-band oscillator is 0.835 × 1.103 ㎟.

Wide-Locking Range Divide-by-3 Injection-Locked Frequency Divider Using Sixth-Order &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$RLC$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Resonator

A wide-locking range divide-by- $3~LC$ injection-locked frequency divider (ILFD) is proposed and implemented in the TSMC 0.18- $\mu \text{m}$ 1P6M CMOS process. The divide-by-3 ILFD uses a cross-coupled nMOS pair, an injection MOSFET pair, and a sixth-order $RLC$ resonator. The divide-by-3 ILFD has three oscillation frequency bands and three locking ranges. At the drain-source bias $V_{\mathbf {DD}}$ of 0.9 V and at the incident power of 0 dBm, by switching a varactor bias, the high-band, middle-band, and low-band locking ranges of the ILFD are, respectively, given by 3.47 GHz (33.87%) from 8.51 to 11.98 GHz, 3.72 GHz (54.86%) from 4.92 to 8.64 GHz, and 1.05 GHz (19.76%) from 4.88 to 5.93 GHz. The operation range is 7.1 GHz (84.2%) from 4.88 to 11.98 GHz. The ILFD-core power consumption is 6.759 mW. A wider locking range of 4.43 GHz (67.07%) from 4.39 to 8.82 GHz is obtained by overlapping the three locking ranges at a fixed bias condition. The die area is $0.991 \times 1.04$ mm2.

Design and simulation of pulse generator for UWB based on LC-tank differential oscillators topology

This paper presents a detailed analysis, design and simulation of pulse generator for Ultra-Wideband (UWB) based on LC-tank differential oscillators topology. The differential oscillators with a cross-coupled NMOS pair and a tail current source are used to achieve more positive gain and generate negative resistance to the LC-tank. Besides, this oscillator is suitable for UWB high frequency and low power applications. The UWB pulse generator is composed of a simple on-off keying (OOK) modulated and LC-tank differential oscillators. The circuit of UWB pulse generator designed and simulated in 0.13 um CMOS technology. The UWB pulse generator generates a pulse for the 6 - 10 GHz UWB transmitter. Simulation results show a pulse width of 586 ps, a peak to peak amplitude pulse of 88.6 mV from the 1.2 V power supply and the die area of 0.22 mm2. The average power consumption of approximately 0.55 mW and an energy consumption of 1.1 pJ/pulse at 500 MHz pulse repetition rate (PRR) are observed.

2.4-GHz Band Ultra-Low-Voltage LC-VCO IC in 130-nm CMOS

An ultra-low-voltage LC-VCO IC has been demonstrated using 130nm CMOS technology. The LCVCO IC includes a cross-coupled NMOS pair, a single symmetric inductor, AMOS varactors with capacitor ac coupling and a buffer amplifier. The LCVCO IC is designed, fabricated and fully evaluated on wafer. The VCO IC exhibits measured frequency tuning range of 17.4% and phase noise of -137 dBc/Hz at 1 MHz oset from the 2.2 GHz carrier at a supply voltage of only 0.5 V.

Low Voltage Low Power Quadrature LC Oscillator Based on Back-gate Superharmonic Capacitive Coupling

This work introduces a new low voltage low power superharmonic capacitive coupling quadrature LC oscillator (QLCO) made by coupling two identical cross-connected LC oscillators without tail transistor. In each of the core oscillators, the back-gate nodes of the cross-coupled NMOS pair and PMOS pair, acting as common mode nodes, have been connected directly. Then the core oscillators are coupled together via capacitive coupling of the PMOS common mode node in one of the core oscillators to the NMOS common mode node in the other core oscillator, and vice versa. Only capacitors are used for coupling of the two core oscillators and therefore no extra noise sources are imposed on the circuit. Operation of the proposed QLCO was investigated with simulation using a commercial 0.18 µm RF CMOS technology: it shows a power dissipation of 5.2 mW from a 0.6 V supply voltage. Since the proposed core oscillator has Complementary NMOS and PMOS cross coupled pairs, and capacitive coupling method will not introduce extra phase noise, so this circuit can operate with a low phase noise as low as −126.8 dBc/Hz at 1 MHz offset from center oscillation frequency of 2.4 GHz, as confirmed with simulation.

Design and Analysis of a 0.4V 1.08mW 12GHz High-Performance VCO in 0.18μm CMOS (Invited Paper)

This paper presents the design and analysis of a high-performance fully-integrated 0.18μm CMOS voltage-controlled oscillator (VCO) with low supply voltage and low dc power consumption. To enhance the transconductance (gm) of MOSFETs and negative conductance (-Gm) of a cross-coupled pair, the device size of the nMOS cross-coupled pair is enlarged. For reducing the supply voltage and minimizing the dc power consumption, forward-body biased technique is utilized in this VCO, leading to the threshold voltage (Vt) reduction. Moreover, process variations are taken into accounted at low supply voltage, and the Monte-Carlo analysis is used to analyze the VCO phase noise and output power. At 0.4V low supply voltage, the fabricated 0.18μm CMOS VCO consumes 1.08mW low core power. At this bias condition, the measured phase noise at 1MHz offset from 12.77GHz carrier is -110.2 dBc/Hz, and the measured tuning range is 5.75%. Compared to recently published 0.18μm X-band CMOS VCOs, this work demonstrates the low supply voltage, low dc power dissipation, superior figure-of-merit (FOM), and better figure-of-merit including the tuning range (FOMT).

Experimental evaluation of hot electron reliability on differential Clapp-VCO

This paper studies the hot-carrier stressed property of a series-tuned all-n core voltage controlled oscillator (VCO). A differential Clapp-VCO has been successfully implemented in the 0.13m CMOS process and it uses a series-tuned resonator. Two single ended nMOS-core Clapp-VCOs are used to form a differential VCO by the aid of a cross-coupled nMOS pair and a transformer. The measured results show that the fresh Clapp-VCO operates from 18.8 to 22.2GHz and hot-carrier stressed experimental data indicate that the damage increases the oscillation frequency and degrades the phase noise of oscillator. Mixed-mode simulation results are used to show the hot-carrier physics to the circuit.

24GHz CMOS Frequency Source with Differential Colpitts Structure-Based Complementary VCO for Low Phase Noise

In this paper, a 24GHz frequency source for low phase noise is presented in a 0.18µm CMOS process. The 24GHz frequency source chip is composed of a 12GHz voltage controlled oscillator (VCO) and a 24GHz balanced frequency doubler with class B gate bias. Compared to a conventional complementary VCO, the proposed 12GHz VCO has phase noise improvement by using resistor current sources and substituting the nMOS cross-coupled pair in the conventional complementary VCO for a gm-boosted nMOS differential Colpitts pair. The measured phase noise and fundamental frequency suppression are -107.17dBc/Hz at a 1MHz offset frequency and -20.95dB at 23.19GHz frequency, respectively. The measured frequency tuning range is from 23.19GHz to 24.76GHz drawing 2.72mA at a supply voltage of 1.8V not including an output buffer.

A K-band differential Colpitts cross-coupled VCO in 0.13 μm CMOS

A K-band differential Colpitts voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 μm CMOS 1P8M process. The designed circuit topology consists of two single-ended Colpitts LC-tank VCOs, and the differential VCO is obtained by using a cross-coupled nMOS pair and a transformer. At the supply voltage of 1.2 V, the output phase noise of the VCO is −113.08 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 20.78 GHz, and the figure of merit is −191.49 dBc/Hz. Total power consumption is 6.24 mW. Tuning range is about 980 MHz, from 19.84 to 20.82 GHz, while the control voltage was tuned from 0 V to 1.2 V.

Low Power and High Efficiency VCO and Quadrature VCO Circuits Constructed with Transconductance-Enhanced Colpitts Oscillator Feature

This work presents a technique to enhance the performance of the conventional PMOS Colpitts VCO circuit. This technique is accomplished by adding an NMOS cross-coupled pair under the traditional differential Colpitts VCO to enhance the oscillator startup condition and its efficiency. The analytics also support this viewpoint and present a devicechoosing method to optimize the output power and phase noise. This new VCO can also be applied to realize the QVCO circuit, because the coupling transistors can be placed in parallel, connecting with the transistors in the NMOS cross-coupled pair, to achieve the proper coupling between individual VCOs. To verify the proposed design concept, two prototypes, which are VCO and QVCO operated at 2.4GHz and fabricated in CMOS 0.25-μm technology, are designed and tested. The measurement results show that the performance of VCO demonstrates a FOM of about 180dBC/Hz, and the phase noise of QVCO is-116dBc/Hz at the 1MHz offset from oscillation frequency.

CMOS Active Bandpass Filter Using Compacted Synthetic Quasi-TEM Lines at $C$-Band

This paper presents a fully monolithic transmission-line-based active bandpass filter (BPF) fabricated in a 0.18-mum standard complementary metal-oxide-semiconductor (CMOS) technology. The half-wavelength resonators are realized by synthetic quasi-TEM complementary conducting-strip transmission lines (CCS TLs). To lower the insertion loss of the BPF, the differential nMOS cross-coupled pairs are combined with the parallel resonators. Besides, the active devices and CCS TLs are vertically integrated on the standard CMOS substrate. The Q-enhanced resonator, which is comprised of a CCS TL and an nMOS cross-coupled pair, is theoretically investigated. Simulation results indicate that the Q factor of the resonator can be increased from 3.4 to 84.0 at 6.53 GHz. Additionally, the prototype of the second-order BPF occupies an area of 1230 mumtimes880 mum, and the measured results demonstrate that the center frequency is 6.02 GHz with a bandwidth of 1.14 GHz. The P1dB and insertion loss are -15.2dBm and 2.2 dB, respectively, when the BPF consumes 3.0 mA from a 1.8-V supply. A two-port noisy network is also reported to examine the noise figure (NF) of the proposed BPF. Theoretical results reveal that the NF is 11.38 dB at 6.0 GHz, with a difference of less than 7.2% among the measured data

Charge-and-split sense amplifier for multilevelnonvolatile memories

A low-voltage sense amplifier for multilevel (ML) nonvolatile memories is presented. It consists of a fully-differential current-to-voltage (I-V) converter followed by a differential amplifier. A crosscoupled NMOS pair is included to prevent simultaneous saturation of the two outputs of the I-V converter, thereby relaxing the timing requirements for output data latching. Experimental evaluations of a memory test chip demonstrated the high suitability of the amplifier for ML sensing.