High-Level Synthesis (HLS) Design Space Exploration (DSE) is essential for generating hardware designs that balance performance, power, and area (PPA). To optimize this process, existing works often employs message-passing neural networks (MPNNs) to predict quality of results (QoR). These predictors serve as evaluators in the DSE process, effectively bypassing the time-consuming estimations traditionally required by HLS tools. However, existing models based on MPNNs struggle with over-smoothing and limited expressiveness. Additionally, while meta-heuristic algorithms are widely used in DSE, they typically require extensive domain-specific knowledge to design operators and time-consuming tuning. To address these limitations, we propose ECoGNNs-LLMMHs, a framework that integrates graph neural networks with task-adaptive message passing and large language model-enhanced meta-heuristic algorithms. Compared with state-of-the-art works, ECoGNN exhibits lower prediction error in the post-HLS prediction task, with the error reduced by 57.27%. For post-implementation prediction tasks, ECoGNN demonstrates the lowest prediction errors, with average reductions of 17.6% for flip-flop (FF) usage, 33.7% for critical path (CP) delay, 26.3% for power consumption, 38.3% for digital signal processor (DSP) utilization, and 40.8% for BRAM usage. LLMMH variants can generate superior Pareto fronts compared to meta-heuristic algorithms in terms of average distance from the reference set (ADRS) with average improvements of 87.77%, respectively. Compared with the SOTA DSE approaches GNN-DSE and IRONMAN-PRO, LLMMH can reduce the ADRS by 68.17% and 61.53% respectively. Code and models are available at https://github.com/wslcccc/CoGNNs_LLMMH.

Multiplication is a fundamental mathematical operation that finds extensive applications across various disciplines, particularly in computation-intensive and error-resilient applications, such as image processing. As hardware circuits become more complex, there is a growing demand for approximation circuit methods. Implementation of approximate multipliers has the potential to yield substantial reductions in hardware costs while maintaining acceptable performance levels. Most current designs for approximate multipliers are optimized for ASIC-based circuits, which may not produce similar performance improvements when adapted for FPGA-based circuits. Additionally, many of these existing multiplier designs are limited to unsigned numbers. This paper proposes a novel approach for designing signed approximate multipliers tailored specifically for FPGAs. Two efficient architectures are introduced that efficiently utilize key FPGA components, such as LUTs and Carry4 primitives, by designing the optimal LUT-Carry4 netlists. A Pareto-based analysis is also performed to balance trade-offs and achieve a low mean error distance (MED). Simulation results confirm that the proposed architectures offer superior performance compared to existing signed approximate multipliers, delivering improved power efficiency, reduced resource usage, shorter critical path delay (CPD), and enhanced computational accuracy. The practical applicability of these approximate multipliers is further validated through their use in image processing applications.

Efficient multiplication and addition of floating-point numbers play a crucial role in digital signal processing applications. To achieve high computational performance with minimal resource utilization, an optimized multiplication approach is essential. Vedic mathematics encompasses the utilization of 16 sutras or algorithms. This paper presents a double-precision floating-point multiplier of 53-bit mantissa based on Vedic mathematics. The proposed architecture performs multiplication in three stages: sign generation, exponent generation, and mantissa multiplication. The Urdhva Tiryakbhyam sutra is employed for mantissa computation owing to its high efficiency and reduced hardware complexity compared to conventional techniques. The proposed multiplier design is implemented using Verilog HDL on Vivado 2022.2. Experimental results demonstrate a significant reduction in critical path delay and logic utilization compared to existing floating-point and Vedic-based multipliers, while maintaining a favorable power consumption trend. The CNN implementation employing the proposed Vedic double-precision floating-point multiplier achieves the lowest inference latency and power consumption while maintaining identical classification accuracy compared to conventional IEEE-754 and existing Vedic-based multiplier designs. Hardware realization on a Zynq FPGA device further confirms the superiority of the proposed architecture in terms of power, delay and on-board component utilization.

Abstract This paper proposes a high-performance, low-power Multiply-Accumulate (MAC) architecture leveraging a Dynamic Reconfiguration with Parallel Partial Evaluation (DRPPE) framework integrated with a 16×16 Vedic multiplier and a flag-driven Selective Partial Sum (SPS) adder. The design addresses the critical need for speed, area efficiency, and dynamic power reduction in digital signal processing (DSP), artificial intelligence (AI), and FPGA-based systems. By incorporating Urdhva-Tiryakbhyam Sutra-based Vedic multiplication, the architecture enables fast partial product generation and low-depth logic realization. The novel flag control mechanism intelligently suppresses redundant carry propagation during accumulation, thereby minimizing switching activity and improving energy efficiency. The proposed design was implemented in Verilog HDL and synthesized on a Virtex-5 FPGA using Xilinx ISE 14.7. Simulation results demonstrate a critical path delay of 2.05 ns, maximum operating frequency of 465.1 MHz, and total power consumption of 52.5 mW, significantly outperforming conventional MAC units in speed and resource utilization. Comparative analysis with recent literature confirms the design's effectiveness in delivering accuracy, configurability, and high-throughput performance suitable for next-generation embedded computing platforms.

The escalating complexity of modern integrated circuit design demands innovative approaches to address timing optimization challenges in advanced technology nodes. Graph Neural Networks (GNNs) have emerged as a transformative paradigm for modeling circuit representations and optimizing placement decisions. This paper presents a comprehensive investigation of GNN applications in timing-driven placement optimization for sub-10nm process technologies. We propose a novel framework that leverages GNN architectures to encode circuit connectivity patterns, predict timing metrics, and guide placement algorithms toward solutions that minimize critical path delays while maintaining acceptable wirelength overhead. Our methodology employs a two-stage GNN model integrating global placement refinement with local timing optimization subroutines. The framework captures spatial dependencies between circuit components through message passing mechanisms while incorporating timing constraints directly into the optimization objective. Experimental evaluations on industry benchmark circuits demonstrate that GNN-based timing optimization achieves 18-24% reduction in worst negative slack compared to conventional analytical placement methods, with runtime improvements of 3-5x over traditional static timing analysis iterations. The proposed approach maintains placement quality metrics including wirelength increase below 7% and demonstrates robust convergence across diverse circuit topologies ranging from processor cores to memory controllers. This research establishes GNNs as viable alternatives to conventional timing-driven placement algorithms and opens new directions for machine learning integration in electronic design automation workflows.

ABSTRACT In digital signal processing, specifically focusing on Finite Impulse Response (FIR) filters and their application in Wireless Sensor Networks (WSN) for IoT. FIR filters are essential components in signal processing systems, used for tasks such as noise reduction, signal enhancement and data analysis. Optimising FIR filter designs becomes essential in WSNs, where energy efficiency, precision and real-time processing are important. In this paper, design of an adaptive finite impulse response filter using low error efficient approximate adder and two-stage operand trimming approximate logarithmic multiplier for WSN in IoT environment (FIR-LEAA-TOTAM-WSN) is proposed. The FIR filter leverages Low Error Efficient Approximate Adder (LEAA) to significantly reduce critical path delay compared to traditional 1-bit full adders. This design effectively reduces noise and interference affecting WSNs, thereby reducing energy consumption, increasing the operational lifespan of WSNs used in IoT applications. The implementation of this design is carried out using Verilog, followed by synthesis through the Xilinx ISE suite with FPGA synthesis performed by Xilinx tools. The experimental outcomes show that the performance of HDP-FIR-LEAA-TOTAM-WSN approach attains low delay, higher dynamic power and low energy consumption when compared with existing methods, respectively.

The designs of lossless data compression architectures create a natural trade-off between throughput, power consumption, and compression efficiency, making it difficult for designers to identify an optimal configuration that satisfies all three criteria. This paper proposes a Configurable Dual-Path Huffman/Arithmetic Encoder (CDP-HAE), which offers an architecture that supports the use of shared preprocessing, parallel path encoding using Huffman and Arithmetic, as well as selectable output. The CDP-HAE’s design prevents the waste of excess bandwidth by sending only one selected bit stream at a time. This also enables adaptation to the dynamically changing statistical characteristics of the input data. CDP-HAE’s architecture underwent ASIC synthesis in 90 nm CMOS technology and is implemented on an Artix-7 (A7-100T) using the Vivado EDA tool, confirming the scalability of the architecture to both devices. Synthesis results show that CDP-HAE improves operating frequency by 28.6% and reduces critical path delay by 27.2% compared to reference designs. Additionally, the dual-path design has a slight increase in area; the area utilization remains within reasonable limits. Power analysis indicates that optimizing logic sharing and minimizing switching activity reduces total power consumption by 34.4%. Compression tests show that the CDP-HAE delivers performance comparable to that of a conventional Huffman Encoder using application-specific datasets. Furthermore, the proposed CDP-HAE achieves performance comparable to conventional Huffman encoders on application-specific datasets, while providing up to 10% improvement in compression ratio over Huffman-only encoding.

Timing optimization during global placement is critical for achieving optimal circuit performance and remains a key challenge in modern Field Programmable Gate Array (FPGA) design. As FPGA designs scale and heterogeneous resources increase, dense interconnects introduce significant resistive and capacitive effects, making timing closure increasingly difficult. Existing methods face challenges in constructing accurate timing models due to multi-factor nonlinear constraints as well as load and crosstalk coupling effects arising in multi-pin driving scenarios. To address these challenges, we propose TD-Placer, a critical path aware, timing-driven global placement framework. It leverages graph-based representations to capture global net interactions and employs a nonlinear model to integrate diverse timing-related features for precise delay prediction, thereby improving the overall placement quality for FPGAs. TD-Placer adopts a quadratic placement objective that minimizes wirelength while incorporating a timing term constructed by a lightweight algorithm, enabling efficient and high-quality timing optimization. Regarding net-level timing contention, it also employs a finer-grained weighting scheme to facilitate smooth reduction of the Critical Path Delay (CPD). Extensive experiments were carried out on seven real-world open-source FPGA projects with LUT counts ranging from 60K to 400K. The results demonstrate that TD-Placer achieves an average ∼10% improvement in Worst Negative Slack (WNS) and a ∼5% reduction in CPD compared to the state-of-the-art method, with an average CPD comparable (×1.01) to the commercial AMD Vivado across five versions (2020.2–2024.2). Its code and dataset are publicly available<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>.

Accurate critical path delay estimation plays a vital role in reducing unnecessary routing iterations and identifying potentially unsuccessful design runs early in the flow. This study proposes an architecture that integrates graph representations derived from digital complex functional blocks netlist and design constraints, leveraging a Multi-head cross-attention mechanism. This architecture significantly improves the accuracy of critical path delay estimation compared to standard tools provided by the OpenROAD EDA. The mean absolute percentage error (MAPE) of the OpenRoad standard tool—openSTA is 12.60%, whereas our algorithm achieves a substantially lower error of 7.57%. A comparison of various architectures was conducted, along with an investigation into the impact of incorporating netlist-derived information.

Aimed at the problems of high delay and low resource allocation efficiency of multi-source heterogeneous data task scheduling in 5G edge computing environment, this paper designs a multi-source data scheduling algorithm framework for low-latency optimization. An end-edge-cloud cooperative system model is constructed, and a set of dynamic priority scheduling strategies is proposed based on the task’s directed acyclic graph (DAG) graph to express the inter-task data dependency relationships, and the task scheduling order is adjusted in real time by fusing the task tightness urgency, the resource pressure and the network state changes. In order to improve the stability of the system under high load, a multi-dimensional load evaluation mechanism and a granularity-adaptive task partitioning and merging method are introduced, and a cache hit-aware resource allocation function and an edge node cache replacement strategy are designed. In addition, a QoS guarantee mechanism and a network state-aware feedback module are constructed to realize dynamic correction of task scheduling accuracy under delay constraints. Multiple rounds of comparison experiments are carried out in the simulation platform, and the results show that this paper’s algorithm can control the average task completion delay within 45 ms under medium-high load conditions, significantly reducing the critical path delay, stabilizing the QoS compliance rate to more than 94%, increasing the resource utilization rate to 87.5%, and achieving a scheduling hit rate of 92.4%. The above results verify the algorithm’s low latency control capability and system resource synergy in dynamic task environments, with good engineering adaptability, suitable for edge intelligent application deployment with high real-time requirements in 5G scenarios.

Approximate computing comes to the fore as an alternative paradigm to enhance efficiency in computing systems by trading off the system’s accuracy for better performance. This paper seeks to leverage the principles of approximate computing to design efficient multiplier architectures for FPGA platforms. Specifically, this work presents FPGA implementations of one accurate and two approximate multiplier units based on the Dadda algorithm. The multipliers employ a novel partial product reduction technique that minimizes the utilized resources and the critical path delay, offering a more resource-efficient alternative than traditional multipliers. Our accurate and best-performing approximate 8 × 8 multiplier shows an improvement of 28% and 37% in PDAP over the Xilinx exact multiplier and the most performance-efficient existing approximate multiplier, respectively. Further evaluation based on the processing of images with different modalities shows a substantial improvement in PSNR over the existing approximate multipliers, especially in the healthcare domain, thereby highlighting the possible application of the proposed multipliers in error-resilient medical imaging tasks.

Coarse-grained reconfigurable architectures (CGRAs) are increasingly employed as domain-specific accelerators due to their efficiency and flexibility. However, the existing CGRA architectures suffer from low hardware resource utilization and performance due to the limitations of the scheduling scheme. In this article, an adaptive scheduler (denoted as DPTM) for concurrent and multi-task interleaved pipelining-oriented CGRA is introduced, which exploits timeslot matching and release methods to avoid the pipeline conflicts and improve the scheduling performance. The characteristics of task scheduling based on directed acyclic graph (DAG) are analyzed, and several performance-influencing factors are extracted to build a scheduling performance model for reducing the time cost of scheduling and guiding the design of scheduling schemes. Moreover, the scoreboard method of dynamic instruction schedulers is optimized to control the entry time of multiple tasks into the pipeline, and then a timeslot matching method is proposed to provide non-conflict pipelining for the multiple tasks. Further, a timeslot release method is presented to release the timeslots for unscheduled sub-tasks dynamically, which can adapt the parallel processing of multiple tasks and decrease the scheduling time. Then, an adaptive scheduling scheme combines the dynamic priority-based task assignment method, timeslot matching method, and timeslot release method to schedule massive tasks for CGRA. Finally, the overall architecture of DPTM is introduced and designed to validate the efficacy of the proposed scheduling scheme. Experimental results show that the proposed timeslot matching/release approach reduces 84% total scheduling time and decreases 40% average scheduling time at most compared to the non-timeslot-matching scheduling schemes, the proposed task assignment approach decreases 8% total scheduling time and lowers 3% average scheduling time compared to the existing approaches, and the proposed scheduler decreases 51% critical path delay, lowers 35% area overhead, and reduces 12% power consumption at most compared with the existing schedulers.

Semiconductor memories are the basic storage elements for advanced FPGAs. However, with technology scaling due to high packing densities, the temperature of the device rises drastically, creating temporary or permanent faults that manifest as errors in the stored data. Permanent errors cannot be corrected, but temporary errors can. If the data in the memory is critical, such as data used during satellite or missile launch, patient data, etc., there is a need for Error-Detecting and Correcting (EDAC) code. Memories are represented as a matrix that stores data in rows. EDAC codes correct random (errors at various distributed locations) and burst errors (a sequence of erroneous bits within a row). The Hamming code represents the basis for any EDAC code. This work focuses on a single code used to identify 8-bit erroneous data and correct for 6 and 7 random bit errors and 8 burst errors. The matrix code utilizes a memory representation and Hamming code to detect and correct errors, taking care to increase the code rate with less area and delay. In addition, a pipelining technique is used to reduce power dissipation, which also helps to increase the speed of the design. The codes were modeled in Verilog HDL and verified for the Zynq 7000 series FPGA using Xilinx Vivado 2023.2. The results were verified for technological parameters, such as area in terms of LUTs, critical path delay, power dissipation, etc., and for non-technological parameters such as code rate, bit overhead, detection capability, correction capability, etc. The proposed pipelined matrix code was better in most aspects compared to existing designs.

Abstract Approximate computing represents a computational paradigm that trades off a slight reduction in accuracy for significant performance improvements. One of the fundamental operations that can leverage approximate techniques is multiplication, which is used substantially in applications like image/video processing and machine learning. This work proposes an approximate 8-bit multiplier design for FPGA-based circuits. This multiplier, by exploiting the FPGA primitives, demonstrates excellent performance regarding error metrics, critical path delay, and power dissipation with minimal LUT utilization. More precisely, the proposed design reduces LUT usage by 43% and PDP by 59% compared to the exact multiplier while incurring a mean error distance of only 102.57. The proposed approximate multiplier is used in two image processing applications to assess the actual advantages in real-world applications. The proposed design achieves a reasonable PSNR in the image processing flow, demonstrating high-quality results with a low error rate.

Finite impulse response (FIR) filters are widely utilized in several applications in digital signal processing, including data transmission, photography, digital audio, and biomedicine. It is necessary to use high sample rates for FIR filters, while moderate sample rates are needed for low-power circuits. To solve these problems, a Booth multiplier based on three-four inexact adder-based multiplication (TFIE-BM) was proposed. The goal of the proposed TFIE-based FIR Booth multiplier is to lower area usage, latency, and power consumption. The proposed method utilizes the spotted hyena optimizer (SHO) to find the optimal filter coefficient (FC) by minimizing the pass power consumption and Transition bandwidth. Moreover, a high-performance three-four inexact adder (TIFE adder) has been introduced, which uses fewer XOR gates for sum and carry generation, indicating that the logic has been simplified to reduce hardware complexity. By increasing speed and decreasing the FIR filter's critical path delay, a modified Booth multiplier that uses a 5:2 compressor is introduced. The overall delay of the proposed approach is 23.4%, 18.7%, 12.3%, and 5.7% lower than that of the Radix-4 Booth multiplier, CSA Booth multiplier, hybrid multiplier, and traditional Booth multiplier, respectively.

As technology scaling exacerbates interconnect resistance in advanced nodes, FPGA architectures demand enhanced programmable logic blocks (PLBs) to minimize global metal routing. However, it is expensive to raise the functionality of LUTs due to exponential area growth with the number of inputs, resulting in poor scalability. Moreover, LUTs are redundant since practical functions in real-world benchmarks only account for an extremely small proportion of all the functions. For example, only 16424 out of more than 100 trillion NPN classes of 6-input functions are used in the mapped netlists of the VTR8 and KOIOS benchmarks. Therefore, we propose a reduced LUT architecture, named RLUT, to efficiently implement most of the frequent functions. The compact structure of the MUX tree in LUTs is preserved and reduced, while the reduced programmable bits are connected to the MUX tree according to the bit assignment generated automatically by the proposed algorithms. Results of evaluations by a full EDA flow show that, compared with the modified Stratix10 baseline, the proposed 8-input PLB with 75 SRAM bits, named Dual-RLUT6, reduces the maximum logic levels significantly by 20.85%, while the critical path delay is improved by 10.11% at the cost of 4.65% area overhead.

The Number Theoretic Transform (NTT) is a cornerstone for efficient polynomial multiplication, which is fundamental to lattice-based cryptographic algorithms such as CRYSTALS-Kyber—a leading candidate in post-quantum cryptography (PQC). However, existing NTT accelerators often rely on integer multiplier-based modular reduction techniques, such as Barrett or Montgomery reduction, which introduce significant computational overhead and hardware resource consumption. These accelerators also lack optimization in unified architectures for forward (FNTT) and inverse (INTT) transformations. Addressing these research gaps, this paper introduces a novel, high-speed NTT accelerator tailored specifically for CRYSTALS-Kyber. The proposed design employs an innovative shift-add modular reduction mechanism, eliminating the need for integer multipliers, thereby reducing critical path delay and enhancing circuit frequency. A unified pipelined butterfly unit, capable of performing FNTT and INTT operations through Cooley–Tukey and Gentleman–Sande configurations, is integrated into the architecture. Additionally, a highly efficient data handling mechanism based on Register banks supports seamless memory access, ensuring continuous and parallel processing. The complete architecture, implemented in Verilog HDL, has been evaluated on FPGA platforms (Virtex-5, Virtex-6, and Virtex-7). Post place-and-route results demonstrate a maximum operating frequency of 261 MHz on Virtex-7, achieving a throughput of 290.69 Kbps—1.45× and 1.24× higher than its performance on Virtex-5 and Virtex-6, respectively. Furthermore, the design boasts an impressive throughput-per-slice metric of 111.63, underscoring its resource efficiency. With a 1.27× reduction in computation time compared to state-of-the-art single butterfly unit-based NTT accelerators, this work establishes a new benchmark in advancing secure and scalable cryptographic hardware solutions.

The next crucial step in artificial intelligence involves integrating neural network models into embedded and mobile systems. This requires designing compact and energy-efficient neural network models in silicon for optimized performance. This article introduces a unified approach for enhancing the architectural efficiency of long short-term memory (LSTM) recurrent neural networks (RNNs). Precisely, two new structures (I and II) based on the two's complement (TC) digit-serial distributed arithmetic (DSDA) technique are presented. The block-circulant matrix-vector multiplications (MVMs) and element-wise multiplications (EWMs) are formulated using TC DSDA. In addition, a fixed-point (FxP) training procedure for quantized LSTM RNNs is considered and validated for speech recognition tasks. Both structures leverage the circular rotation of weights and generate partial products with input digit slices. A new partial-product generator (PPG) and partial-product selector (PPS) designed to work with both unsigned and signed digits is introduced. In Structure I, a nonpipelined MVM is realized with a few PPGs and PPSs, followed by a shift-accumulate unit (SAU). Conversely, in Structure II, a suitably chosen depth-pipelined MVM is achieved with multiple PPGs and PPSs, followed by a shift-to-add tree (SAT). A critical path delay (CPD) analysis for both the proposed structures is also presented. Compared with previous works, post-synthesis results on 28-nm fully depleted silicon-on-insulator (FDSOI) technology reveal that for a model size of $128 \times 128$ , Structures I and II provide 39.87%, 95.63%, and 30.95%, 91.18% more area and energy efficiencies, respectively.

In this article, an area-efficient VLSI architecture scheme for high-throughput computation of the 2-D discrete wavelet transform (DWT) is proposed, effectively applied in the context of aircraft cargo hold scenes. The proposed architecture aims to reduce computation and storage resources while maintaining the DWT-IDWT reconstructed image quality for the 9/7 discrete wavelet. The hardware implementation formulae based on the flipping architecture have been modified to reduce RAM storage bit width. By transforming the coefficients of the formula into hardware-friendly values, the required multiplication operations are split into two stages of addition. On this basis, a pipelined architecture is constructed to set the critical path delay (CPD) of the architecture to be close to the delay of a single adder, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{a}$ </tex-math></inline-formula>, thereby achieving a high throughput. Compared to existing architectures in the research field, the proposed single-level 2-D DWT architecture achieves resource savings on the field-programmable gate array (FPGA) platform while ensuring good image reconstruction quality. The advantages of the multilevel 2-D DWT are even more pronounced. In the simulation results on the application-specific integrated circuit (ASIC) platform, the proposed architecture reduces computation time by at least 35.54% while achieving a higher level of decomposition, decreases the area-delay product (ADP) by at least 25.41%, and saves a significant amount of energy per image (EPI). Furthermore, the proposed folded architecture achieves close to 100% hardware utilization efficiency (HUE) in multilevel 2-D DWT computations.

Sustainability in in-vehicle communication comprises the integration of wireless technology for faster and more reliable connectivity. Driverless vehicles need to schedule various tasks on a priority basis. The first-in-first-out (FIFO) data structure is critical for handling sensor data and communication information, and a memory queue is important for controlling data flow through organized read and write processes. This study focuses on the design, verification and synthesis of a FIFO with a size of 4k bytes. By operating on a single clock signal, synchronous FIFO enables smooth data transmission between a source and destination within the same clock domain. The designed FIFO resulted in an area of 41.401[Formula: see text]mm2, a power dissipation of 0.506[Formula: see text]mW and a critical path delay of 0.03[Formula: see text]ps when a 15[Formula: see text]nm open-cell library from Nangate was used. The design is also implemented using an Arria II field programmable gate array (FPGA), which results in a maximum clock frequency of 33.33[Formula: see text]GHz.