Test Generation Cost Research Articles

Generating and selecting resilient and maintainable locators for Web automated testing

SummaryWeb user interface (UI) test automation strategies have been dominated by programmable and record–playback approaches. Of these, record–playback allows creating automation tests easily and reduces the cost of test generation. However, this approach increases the cost of test maintenance due to its unstable generated locators for identifying UI objects during playback. In this paper, we propose a new approach to generating and selecting resilient and maintainable locators. Our approach consists of two parts, a new XPath construction method and selecting the best XPath to locate the target element. Our XPath construction method relies on semantic structures of Web pages to locate the target element using its neighbors. We conducted an experiment on 15 popular websites. The results show that our approach outperforms the state‐of‐the‐practice/art Selenium IDE and Robula+ in locating target elements by effectively avoiding wrong locators. It also produces more readable XPaths (hence more maintainable tests) than do these approaches.

An Empirical Comparison of Combinatorial Testing, Random Testing and Adaptive Random Testing

We present an empirical comparison of three test generation techniques, namely, Combinatorial Testing (CT), Random Testing (RT) and Adaptive Random Testing (ART), under different test scenarios. This is the first study in the literature to account for the (more realistic) testing setting in which the tester may not have complete information about the parameters and constraints that pertain to the system, and to account for the challenge posed by faults (in terms of failure rate). Our study was conducted on nine real-world programs under a total of 1683 test scenarios (combinations of available parameter and constraint information and failure rate). The results show significant differences in the techniques’ fault detection ability when faults are hard to detect (failure rates are relatively low). CT performs best overall; no worse than any other in 98 percent of scenarios studied. ART enhances RT, and is comparable to CT in 96 percent of scenarios, but its computational cost can be up to 3.5 times higher than CT when the program is highly constrained. Additionally, when constraint information is unavailable for a highly-constrained program, a large random test suite is as effective as CT or ART, yet its computational cost of test generation is significantly lower than that of other techniques.

A Novel Trust Evaluation Method for Logic Circuits in IoT Applications Based on the E-PTM Model

The increase in the reliability requirements of integrated circuits applied in diverse smart sensing devices and the increase in the cost of test generation and fault simulation have expanded the need for new approaches to estimate signal reliability in logic circuits, which will help trust management of Internet of Things smart systems. This paper presents a novel method for reliability analysis in logic circuits with unreliable devices for application in trust-driven design. Based on the extended probabilistic transfer matrix model with binary-decimal coding allocation, by using the technologies of state-vector expansion and matrix reconstruction, the proposed method evaluates the quality of a reliability improvement for trust-driven design applications, while maintaining high computational accuracy, in early stages of circuit design. This efficiency is possible, because the proposed method is always computed in units of basic gates and the reliability can be output by an observable matrix with hybrid coding. Simulation results on benchmark circuits show that the proposed method is an accurate and fast method with less complexity and will contribute to the dynamic analysis of circuit reliability in circuit design.

Test Generation for Programs with Binary Tree Structure as Input

Test data generation is a process of creating program inputs that satisfy specific testing criteria. Many works have been focused on test generation with respect to numeric and string data. Dynamic data structures, such as trees and linked lists, have been widely used in modern programming, but on which there are few studies presented. In general, generating a dynamic data structure is associated with a proper shape and valid values generation. It would be difficult to generate such dynamic data structures, as both shapes and values are necessary to be valid simultaneously. This paper focuses on binary tree structures and proposes a novel test generation approach that combines search based testing with constraint solving techniques. The approach creates the shapes of binary tree structures by using GA, and generates the values in their data fields by using constraint solving techniques. The experimental results show that the presented approach is promising and effective. Moreover, the studies investigate factors affecting the performance of the approach, and arrive at a conclusion that the test generation cost is cubic growing as the number of pointer constraints increases.

PASE-scan design: A new full-scan structure to reduce test application time

Serial scan approaches lead to a considerable reduction in the test generation cost for sequential circuits. However, they do present some drawbacks, such as area overhead I/O pin overhead and high test application time. A new full-scan approach is described named design, capable of substantially reducing the test application time. The paper focuses particularly on the case of single PASE-scan structures. An heuristic procedure is proposed to establish the configuration of the single PASE-scan structure and the placing of its memory elements. The experiments carried out with a set of ISCAS89 circuits show reductions in test length, with respect to the full single serial scan-path case, of up to 91% and 87%, depending on the compaction (low or normal) of the applied test set, and average reductions of 62% and 55%, respectively.

ATPG for heat dissipation minimization during test application

A automatic test pattern generator (ATPG) algorithm is proposed that reduces switching activity (between successive test vectors) during test application. The main objective is to permit safe and inexpensive testing of low power circuits and bare die that might otherwise require expensive heat removal equipment for testing at high speeds, Three new cost functions, namely transition controllability, observability, and test generation costs, have been defined. It has been shown, for a fanout free circuit under test, that the transition test generation cost for a fault is the minimum number of transitions required to test a given stuck-at fault. The proposed algorithm has been implemented and the generated tests are compared with those generated by a standard PODEM implementation for the larger ISCAS85 benchmark circuits. The results clearly demonstrate that the tests generated using the proposed ATPG can decrease the average number of (weighted) transitions between successive test vectors by a factor of 2 to 23.

Partial scan design of register-transfer level circuits

Register-transfer level designs that are derived from high-level synthesis systems generally consist of functional blocks and registers that are interconnected by multiplexers and buses to maximize resource sharing These multiplexer and bus structures have the unique ability to behave asswitches, i.e., to logically partition the circuit when their control inputs are manipulated in different ways. The presence of switches, the selection of scan registers can be influenced. This leads to an efficient partial scan methodology presented in this paper. Second, switches help set up data transfer paths calledI-paths. By employingI-paths to transport test data, the functional logic in the circuit can be separated from the switching logic for the purpose of test generation. This can lead to a reduction in test generation costs for a partial scan design. Thus the techniques presented in this paper help to minimize both testability overhead and test generation cost in bus-based circuits. This methodology is implemented in the SIESTA system for serial scan design.

Testability implications of performance driven logic synthesis

Retiming improves performance but also increases test generation time and decreases fault coverage. Research conducted at Carnegie Mellon and McGill Universities attempts to explain the impact of retiming on the testability of sequential logic circuits. A novel test preservation theorem suggests a powerful way to decrease the test generation cost of retimed circuits. The authors also discuss a recently recognized circuit attribute that better explains the complexity of structural, sequential automatic test pattern generation. >

Built‐in current testing for CMOS logic circuits using random patterns

AbstractWith respect to CMOS logic circuits, it is reported that a fault can occur cannot be covered by conventional classical fault model, and the current testing is considered to be interesting as a testing method to detect such a fault.This paper proposes a fault‐detection method for the CMOS logic circuit which can detect the stuck‐at fault and the stuck‐open fault based on the dynamic power supply current observed when a pseudorandom pattern is applied as the input. A built‐in testing circuit for realizing the principle is shown. The feature of the current testing is that the fault can be detected by observing the power supply current as long as the fault in the circuit is activated, and it is not required to propagate the fault information to the output. Based on that property, a random pattern with a small test generation cost is used as the test pattern.As the test pattern, the pseudorandom pattern is generated autonomously by utilizing the output signal of the circuit under test. The fault detection is made easier by this pattern generation since the effect of the fault on the power supply current is enhanced. In determining whether or not the power supply current is that of the normal circuit, a method based on the time‐course of the power supply current is used, with the power supply currents for various test patterns as the feature parameter. The proposed procedure is evaluated by a simulation, and the usefulness of the proposed method is demonstrated.

Parity-scan design to reduce the cost of test application

Points out that scan design approach is representative of those techniques that can reduce the cost of test generation for sequential circuits. However, the length of a test sequence for the scan design approach can grow quite large due to the scan operation shifting the values into the scan chain, which makes the cost of test application large. A design-for-testability approach called parity-scan design which can reduce the cost of test application as well as the cost of test generation for sequential circuits is discussed. The parity-scan design approach is a combination of scan technique and parity testing. Two types of parity-scan designs, preparity and postparity scan design, are presented. Experiments on ISCAS89 circuits show that as high as 91.2% (91.1%) test length reduction and 32.4% (27.0%) average reduction can be obtained for preparity (postparity) scan design under the single scan chain approach. More reduction can be achieved by applying a multiple scan chain technique.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An approach to testability analysis and improvement for VLSI systems

This paper presents a method for including design for testability in architectural synthesis systems. It concentrates first on the subject of testability analysis with a definition of testability measures that capture the cost of test generation, fault coverage, testing time and untestable faults. An algorithm for testability analysis is then described, which takes a design representation and calculates testability measures for every line in the data path. Methods for testability improvement based on design transformations are consequently discussed. Finally, a systematic strategy to integrate design for testability into a synthesis system is presented.

Constrained parity testing

A generalized testing technique called constrained parity testing is presented for detecting multiple stuck-at faults in any single-output irredundant combinational network by verifying the subparities of the network. Implementation independent testability conditions are established for single- and multiple-input stuck-at faults. A spanning parity signature (SPS) is introduced to detect vacuous faults, which include all the input stuck-at faults and a majority of all other multiple stuck-at faults. The SPS is considered for testing all stuck-at faults in networks with small numbers of fanout lines, and a method of deriving tests for nonvacuous faults is proposed. For networks with large fanouts, a hybrid scheme by combining with syndrome testing is suggested to eliminate or reduce the need for expensive fault simulation. The proposed technique is a theoretical generalization of many existing methods and offers advantages such as versatility, flexibility, low test volume, low test time, high fault coverage, and reduced fault simulation and test generation costs.

On-chip testing of embedded p.l.a.s

Rising test generation costs, compounded by the problem of module inaccessibility, have led to a surge of interest in self-testing methods for p.l.a.s. This paper considers the problems associated with the on-chip testing of p.l.a.s deeply embedded in v.l.s.i. systems and presents a method of on-chip testing which uses the input/output registers of the p.l.a. as test aids. An 8-input ×45 product term ×6-output built-in testable p.l.a., which has been implemented in n.m.o.s., is described.