Correction Codes Research Articles

Performance of entanglement-assisted quantum codes with noisy ebits over asymmetric and memory channels

Entanglement-assisted quantum error correction codes (EAQECCs) play an important role in quantum communications with noise. Such a scheme can use arbitrary classical linear code to transmit qubits over noisy quantum channels by consuming some ebits between the sender (Alice) and the receiver (Bob). It is usually assumed that the preshared ebits of Bob are error free. However, noise on these ebits is unavoidable in many cases. In this work, we evaluate the performance of EAQECCs with noisy ebits over asymmetric quantum channels and quantum channels with memory by computing the exact entanglement fidelity of several EAQECCs. We consider asymmetric errors in both qubits and ebits and show that the performance of EAQECCs in entanglement fidelity gets improved for qubits and ebits over asymmetric channels. In quantum memory channels, we compute the entanglement fidelity of several EAQECCs over Markovian quantum memory channels and show that the performance of EAQECCs is lowered down by the channel memory. Furthermore, we show that the performance of EAQECCs is diverse when the error probabilities of qubits and ebits are different. In both asymmetric and memory quantum channels, we show that the performance of EAQECCs is improved largely when the error probability of ebits is reasonably smaller than that of qubits.

Low-Power Very-Large-Scale Integration Implementation of Fault-Tolerant Parallel Real Fast Fourier Transform Architectures Using Error Correction Codes and Algorithm-Based Fault-Tolerant Techniques

As technology advances, electronic circuits are more vulnerable to errors. Soft errors are one among them that causes the degradation of a circuit’s reliability. In many applications, protecting critical modules is of main concern. One such module is Fast Fourier Transform (FFT). Real FFT (RFFT) is a memory-based FFT architecture. RFFT architecture can be optimized by its processing element through employing several types of adder and multipliers and an optimized memory usage. It has been seen that various blocks operate simultaneously in many applications. For the protection of parallel FFTs using conventional Error Correction Codes (ECCs), algorithmic-based fault tolerance (ABFT) techniques like Parseval checks and its combination are seen. In this brief, the protection schemes are applied to the single RAM-based parallel RFFTs and dual RAM-based parallel RFFTs. This work is implemented on platforms such as field programmable gate arrays (FPGAs) using Verilog HDL and on application-specific integrated circuit (ASIC) using a cadence encounter digital IC implementation tool. The synthesis results, including LUTs, slices registers, LUT–Flip-Flop pairs, and the frequency of two types of protected parallel RFFTs, are analyzed, along with the existing FFTs. The two proposed architectures with the combined protection scheme Parity-SOS-ECC present an 88% and 33% reduction in area overhead when compared to the existing parallel RFFTs. The performance metrics like area, power, delay, and power delay product (PDP) in an ASIC of 45 nm and 90 nm technology are evaluated, and the proposed single RAM-based parallel RFFTs architecture presents a 62.93% and 57.56% improvement of PDP in 45 nm technology and a 67.20% and 60.31% improvement of PDP in 90 nm technology compared to the dual RAM-based parallel RFFTs and the existing architecture, respectively.

Performance Analysis of Successive Cancellation Decoder for Polar Codes with Two Stage Channel Estimator

Nowadays polar codes are becoming one of the most favorable capacity achieving Error Correction Codes (ECC) for their simple low encoding and decoding complexity, have received much attention in recent years; they probably achieve the theoretical capacity of discrete memoryless channels using the low complexity successive cancellation (SC) decoding algorithm. However, among the very few prior successive cancellation polar decoder designs, the required long code length makes the decoding latency high. As a new polar decoder, referred to as 2b-SC-Precomputation decoder, reduce the latency from (2n-1) to ((3n/4)-1) without performance loss, which can reduce the hardware complexity by two stage channel estimators. Furthermore, in our method, the decoding latency decreases rapidly with increasing throughput. Significant latency and throughput reductions are shown by simulation results and report synthesis results for ASIC.

Application of the method of equivalent message encoding structures to simplify coding complexity

Formulation of the problem. Modern telecommunication technologies make it possible to transmit data over long distances with limitations in the form of low power consumption and low error rate using error correction codes. The use of such codes plays an important role and is necessary to detect and correct errors caused by signal distortion and noise in the communication channel. According to Shannon's channel coding theorem, the probability of error can be arbitrarily small or close to zero if the encoding rate of transmission R is less than or equal to the bandwidth of channel C. Assuming that the bandwidth C is achievable, we can calculate the minimum signal-to-noise power ratio (SNR) to achieve zero error, or an arbitrarily small error called the Shannon limit, while maintaining R ≤ C. This article discusses a method of applying equivalent message encoding structures to construct low-density parity-checking (LDPC) codes. Low-density parity-checking (LDPC) codes are a class of linear block codes in which the complexity of iterative decoding increases linearly with increasing block length. Standard LDPC codes without modifications are considered to demonstrate the effectiveness of the proposed method, which is expected to provide high encoding speed when transmitting messages with a short block length. The method of obtaining equivalent structures allows: to reduce the computational complexity of encoding and decoding; to provide the possibility of finding a new encoding scheme and evaluating its effectiveness. The validity of the method for obtaining equivalent message encoding structures is evaluated by modeling the bit error rate (BER) of LDPC codes. Purpose. to show the effectiveness of the use of equivalent structures for various methods of compression of transmitted information, to minimize the complexity of encoding, while maintaining energy efficiency, correcting ability and data transfer rate. Results. A method is considered for obtaining equivalent message element encoding structures that can be used to create more LDPC codes for data transmission applications with a short block length. The cascade principle of constructing an equivalent generator and a parity check matrix was analyzed, which also leads to minimizing the computational complexity of the encoder and decoder. An equivalent structure G can be obtained from cascading two (or more) matrices by modifying the second matrix so that it has a unit matrix with the size of the parity check length and a shift to the right by k bits. On the other hand, the equivalent structure H can be obtained by simply cascading directly the second matrix and shifting to the right by k bits. According to the simulation results, the proposed method is adequate, since LDPC codes have the same BER characteristics as codes based on the low density generator matrix (LDGM). During the simulation, it was concluded that the SPC codes (single parity check (single parity check (SPC)) are the most efficient codes (for a given block length), since SPC codes have the smallest interval up to the Shannon limit. Practical significance. The results presented in this article will give a new insight into the development of simple channel coding of LDPC codes of short block length with high encoding speed for future applications with lower power consumption.

Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures

In harsh environments, such as space, radiation, and charged particles cause single-event effects (SEEs), faults occurring randomly on any electronic component. These must be mitigated to ensure device functionality. Modern mitigation methods, such as triple modular redundancy (TMR), are very effective against single-event transients (SETs) but incur a minimum of 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> cost in the area. Single-event upsets (SEUs) affect sequential elements and are regularly repaired using memory scrubbing. Scrubbing is a slow serial process going through every memory word, looking for errors to repair. Scrubbing involves a nonnegligible amount of time before an error is detected, during which other events can occur and compromise the system. Field-programmable gate arrays (FPGAs) rely heavily on sequential elements to store their configuration; thus, FPGA’s SEU detection time is critical to ensuring design sustainability in harsh conditions. In this article, we propose an alternative mitigation method based on sensor integration and FPGA architecture modification, called smart-redundancy with in-memory error correction code checking (SRIMECCC). The sensors allow asynchronous SEU detection, reducing the time to detect by 57 250 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> on average and enabling local reconfiguration. Our method includes built-in dual redundancy that reduces the power consumption by 87% on average, benefiting embedded systems. SRIMECCC is also an area-efficient technique that saves 28% of total effective area compared to TMRed designs implemented in FPGAs.

Crypto coding system based on the turbo codes with secret keys

In 1997, the US National Science Foundation recognized the need to unite research communities together to solve mutual problems, overcome challenges, future development and practical applications of cryptography and error correction coding. Recent works in this area are connected with turbo codes, which have a special ability to provide error correction characteristics of the information transmission close to theoretically obtained values. Besides, they are used for television (DVB-RCS, DVB-RCT), wireless local networks (WiMAX), software-defined radio systems, mobile (3G, 4G, Inmarsat) and space (CCSDS) communications etc. In this article is presented the crypto coding system based on turbo codes with secret keys used by interleavers. All calculations are performed during data encoding, which reduces the computational complexity of data pre-encryption. The necessary mathematical apparatus was presented, the security level of the communication system was estimated, a simulation of the error correction characteristics was performed, and multimedia information was processed. The working characteristics of the classical and proposed turbo codecs do not differ statistically. The results can be used in communication systems for various functional purposes.

Adaptive surface code for quantum error correction in the presence of temporary or permanent defects

Whether it is at the fabrication stage or during the course of the quantum computation, e.g. because of high-energy events like cosmic rays, the qubits constituting an error correcting code may be rendered inoperable. Such defects may correspond to individual qubits or to clusters and could potentially disrupt the code sufficiently to generate logical errors. In this paper, we explore a novel adaptive approach for surface code quantum error correction on a defective lattice. We show that combining an appropriate defect detection algorithm and a quarantine of the identified zone allows one to preserve the advantage of quantum error correction at finite code sizes, at the cost of a qubit overhead that scales with the size of the defect. Our numerics indicate that the code's threshold need not be significantly affected; for example, for a certain scenario where small defects repeatedly arise in each logical qubit, the noise threshold is 2.7&amp;#x0025; (versus the defect-free case of 2.9&amp;#x0025;). These results pave the way to the experimental implementation of large-scale quantum computers where defects will be inevitable.

A Hybrid Scheme Combining Duplications and LDPC Decoding to Reduce NAND Flash

Abstract With the development of NAND flash, the storage density has become larger and larger, but the reliability has become lower and lower. To address this problem, stronger error correction codes, low-density parity-check (LDPC) codes, are widely used in flash memory. However, the direct use of LDPC codes for error correction has a great impact on the read and write performance of SSDs. Given this, this paper proposes a new mentality that combines replica and LDPC decoding methods to improve the read performance of solid state drives (SSDs). Considering the characteristics of the quantization level of LDPC soft-decision decoding, this paper proposes the IDSD (LDPC soft-decision decoding and duplication method) and IDHSD (a method combining duplication and LDPC hybrid decoding)schemes. These schemes are mainly for hot data. When reading the data, the IDSD scheme needs to first judge whether it is soft-decision decoding. Then, according to the number of quantization levels recorded, it needs to select whether to use duplication or soft-decision decoding to correct the error data. The IDHSD scheme does not need to judge the soft-decision decoding but directly uses the duplication after the hard-decision decoding fails. Both schemes reduce the average response time to a certain extent and optimize the read performance of the SSD. The experimental results show that compared with the Native Scheme, the average response delay time of the IDSD scheme decreases by 5–30% and the IDHSD scheme slashes by 5–38%. Compared with the Traditional Refresh Scheme, the average response delay time of the IDSD scheme cuts down by 1–30% and the IDHSD scheme lowers by 1–29%.

Automated Door Locking System using IOT

As technology advances and expands on a daily basis, safety becomes increasingly essential in all disciplines. Everyone desires a private place where no one can enter without their permission, thus we need to secure our room, office, locker, etc. that preserve our valuable accessories, documents, data, and jewelry, and for that purpose, the proposed work has developed a "Password based door lock system by using Arduino.". This device is a digital door lock with a password or pin code. Which prevents the user from opening the door unless they input the correct password or pin code. Key Words:

EuDiS - A comprehensive database of the seed dispersal syndromes of the European flora.

Seed dispersal is a critical process in plant colonisation and demography. Fruits and seeds can be transported by several vectors (typically animals, wind and water), which may have exerted strong selective pressures on plant's morphological traits. The set of traits that favour dispersal by a specific vector have been historically considered as seed dispersal syndromes. As seed dispersal syndromes have a great potential to predict how seeds move (i.e. the relative importance of the standard mechanisms of seed dispersal), they have attracted the attention of naturalists and researchers for centuries. However, given that observations of actual dispersal events and colonisation are seldom reported, there is still much confusion in current studies failing to properly discriminate between seed dispersal syndromes (i.e. sets of traits that favour a particular mechanism) and actual seed dispersal (i.e. the vector that moves a given seed in one dispersal event). This distinction is important because the presence of any seed dispersal syndrome does not preclude the seed being occasionally dispersed by other non-standard mechanisms (i.e. different from the one predicted). Similarly, the absence of seed dispersal syndromes does not prevent seeds from being dispersed. The correct coding of seed dispersal syndromes thus requires a systematic and evolutive, rather than a phenomenological approach. Unfortunately, such approach has rarely been implemented at a community-level and no comprehensive datasets of seed dispersal syndromes are yet available for any entire flora. This database contains categorisation of the native European flora into eight seed dispersal syndromes. Information for a total of 9,874 species retrieved from the volumes of Flora Europaea were analysed. Earlier versions of this database, which only coded for the presence of four long-distance dispersal syndromes (endozoochorous, epizoochorous, thalassochorous and anemochorous diaspores), were used in four previous studies. Here, we present a fully revised and expanded database, including the presence of four additional short-distance dispersal syndromes (myrmecochorous, vertebrate hoarding, freshwater hydrochorous and ballochorous diaspores), a nomenclatural update for all species and the codification of 416 additional species.Roughly half (51.3%) of the native European flora produce diaspores without traits clearly associated with facilitating seed dispersal. The other half (48.7%) of the European plant species produces diaspores with some specialised traits associated with seed dispersal, most of which (79.9%) with a potential to facilitate long-distance dispersal events. The most common diaspores are those with anemochorous (23.5%), epizoochorous (8.0%), endozoochorous (7.8%), myrmecochorous (7.2%), thalassochorous (2.3%), freshwater dispersal (2.1%), ballochorous (4.6%) and vertebrate hoarding associated traits (0.2%). Two-thirds (66.3%) of the European shrub and tree species have diaspores with some specialisation for biotic seed dispersal.

A Remote Quantum Error-Correcting Code Preparation Protocol on Cluster States

The blind quantum computation (BQC) protocol allows for privacy-preserving remote quantum computations. In this paper, we introduce a remote quantum error correction code preparation protocol for BQC using a cluster state and analyze its blindness in the measurement-based quantum computation model. Our protocol requires fewer quantum resources than previous methods, as it only needs weak coherent pulses, eliminating the need for quantum memory and limited quantum computing. The results of our theoretical analysis and simulations show that our protocol requires fewer quantum resources compared to non-coding methods with the same qubit error rate.

Reconfigurable linear feedback shift register for wireless communication and coding

&lt;p&gt;Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.&lt;/p&gt;

Locksynth: Deriving Synchronization Code for Concurrent Data Structures with ASP

AbstractWe present Locksynth, a tool that automatically derives synchronization needed for destructive updates to concurrent data structures that involve a constant number of shared heap memory write operations. Locksynth serves as the implementation of our prior work on deriving abstract synchronization code. Designing concurrent data structures involves inferring correct synchronization code starting with a prior understanding of the sequential data structure’s operations. Further, an understanding of shared memory model and the synchronization primitives is also required. The reasoning involved transforming a sequential data structure into its concurrent version can be performed using Answer Set Programming, and we mechanized our approach in previous work. The reasoning involves deduction and abduction that can be succinctly modeled in ASP. We assume that the abstract sequential code of the data structure’s operations is provided, alongside axioms that describe concurrent behavior. This information is used to automatically derive concurrent code for that data structure, such as dictionary operations for linked lists and binary search trees that involve a constant number of destructive update operations. We also are able to infer the correct set of locks (but not code synthesis) for external height-balanced binary search trees that involve left/right tree rotations. Locksynth performs the analyses required to infer correct sets of locks and as a final step, also derives the C++ synchronization code for the synthesized data structures. We also provide a performance analysis of the C++ code synthesized by Locksynth with the hand-crafted versions available from the Synchrobench microbenchmark suite. To the best of our knowledge, our tool is the first to employ ASP as a backend reasoner to perform concurrent data structure synthesis.

The Generalized Integrated Interleaved Zipper Codes With Anchor Decoding

Constructions of high-performance hard-decision decodable error correction codes are important for high-speed communication systems. In this paper, we present the generalized integrated interleaved (GII) zipper codes, in which multiple zipper codes are coupled together by the constraint of the GII code. The resulting codes are referred to as GII-zipper codes. Firstly, since the performances of GII-zipper codes are sensible to miscorrections, we propose an enhanced anchor decoder (AD) which uses the hard-decision results during the GII decoding to assign anchor reliability to reduce miscorrections. We then analyze the size and multiplicity of the minimum-sized stall patterns (MSSPs) of the GII-zipper codes. The analytical results show that the size of the MSSPs of the GII-zipper codes is larger that of the zipper codes. Finally, we present extensive simulation results to show the performance advantages of the GII-zipper codes. The results show that, when decoded with the original AD, the GII-zipper codes perform better than the comparable zipper codes and we can obtain further performance gain by the enhanced AD. Particularly, a GII-staircase code with a rate of 0.846 can achieve 0.74 dB from capacity at a bit error rate (BER) of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-15</sup> .

3GPP 5G V2X Error Correction Coding for Various Propagation Environments: A QoS Approach

Vehicle-to-everything (V2X) communications is an emerging branch of wireless communications and has recently gained a lot of interest not only from academia but also from the automotive and telecommunications industry. An important feature of V2X telecommunication systems is that the communication quality varies quickly in time due to the high mobility of the transceivers and due to the rapid change in the fading characteristics of the communication medium. For this reason, it is vital to maintain tolerable quality of service (QoS) in a V2X communication environment, in terms of communication reliability, power, end-to-end latency, data rate, communication range, throughput and vehicle density. A significant impact on the quality parameters of the system has been the coding scheme used by the V2X telecommunication system. For this purpose, we examine the effect that popular coding schemes have on the QoS of a V2X communication system. More specifically, the impact of fourth-generation long-term evolution (4G-LTE) turbo codes, fifth-generation new radio (5G-NR) polar codes and 5G-NR low-density parity-check codes (LDPC) on the QoS parameters of a V2X communication system is researched. Το this end, we employ stochastic V2X propagation models that simulate every possible V2X channel state and traffic environment, based on the third-generation partnership project (3GPP) Release 16 specifications. These propagation models form the basis of our study, since through them, at a first level, we analyze the frame error rate (FER) performance for different levels of signal-to-noise ratios (SNRs) for all the aforementioned coding schemes and 128-bit V2X-compatible data frames, and, at a second level, we investigate the impact of these propagation models and coding schemes on the V2X QoS parameters. Our analysis shows that turbo-based coding schemes satisfy all the QoS parameters and achieve overall communication quality comparable to polar and better than LDPC, making them suitable for small-frame 5G V2X services.

Research and Application of Several Error Correction Codes in Communication

Error correction code is an important part of contemporary communication engineering, first proposed by Shannon, and has become mature nowadays. This paper analyzes and compares the error correction capabilities of BCH code, cyclic code, and Hamming code using BPSK modulation in AWGN channels. It unfolds in chronological order, introducing the popular codewords of various eras of the last century in turn. Moreover, it introduces the communication process of BPSK modulation and its addition of three codes and compares the bit error rates of the output signals of them when the input signal is a Bernoulli binary sequence. After simulation, it is found that there is a strong correlation between the number of bit errors in BPSK modulation and the code used and its length At low SNR (signal-to-noise ratio),the error rate error of using codewords or not is minimal. Most digital devices exhibit advantages when the SNR exceeds 4 dB. Under the equivalent SNR, the longer the codeword, the lower the error rate, and the best error correction ability of BCH code (31,11,5). This article only discusses the error correction ability of BPSK under modulation, laying a foundation for comparing the error correction ability of higher order PSK modulation and other code words in the future.

Performance Enhancement of Chaotic Error Correction Coding Using Consecutive Sequences

The use of chaotic dynamics for error correction is the subject of extensive research, as the approach allows to avoid the use of redundant data. This work proposes a new technique for non-coherent chaos communications for modifying error-correction depending on chaotic dynamics. In the proposed system, there are two consecutive sequences created from a comparable chaotic map, with the second series being created as the latest value of the initial one. Generation of a sequential chaotic sequence with a comparable chaotic dynamic delivers additional information to the receiver, allowing it to appropriately recover information and, hence, facilitate the receiver’s bit-error performance. For error correction and for detecting the symbol that is transmitted, a suboptimal technique based on the nearest distance between chaotic map trajectories over the n-dimensional sequence received is utilized. Simulation results show that the proposed error correction approach improves Eb/N0 as the dimension of the trajectory map increases, indicating that the method improves overall error correction performance. With the dimension of 4, a gain of 0.8 dB in Eb/N0 is achieved compared with an approach without any error-correcting schemes, at the bit-error probability of 10−3.

Computational category-theoretic rewriting

We demonstrate how category theory provides specifications that can efficiently be implemented via imperative algorithms and apply this to the field of graph transformation. By examples, we show how this paradigm of software development makes it easy to quickly write correct and performant code. We provide a modern implementation of graph rewriting techniques at the level of abstraction of finitely-presented C-sets and clarify the connections between C-sets and the typed graphs supported in existing rewriting software. We emphasize that our open-source library is extensible: by taking new categorical constructions (such as slice categories, structured cospans, and distributed graphs) and relating their limits and colimits to those of their underlying categories, users inherit efficient algorithms for pushout complements and (final) pullback complements. This allows one to perform double-, single-, and sesqui-pushout rewriting over a broad class of data structures. Graph transformation researchers, scientists, and engineers can then use this library to computationally manipulate rewriting systems and apply them to their domains of interest.

Channel Modeling and Quantization Design for 3D NAND Flash Memory.

As the technology scales down, two-dimensional (2D) NAND flash memory has reached its bottleneck. Three-dimensional (3D) NAND flash memory was proposed to further increase the storage capacity by vertically stacking multiple layers. However, the new architecture of 3D flash memory leads to new sources of errors, which severely affects the reliability of the system. In this paper, for the first time, we derive the channel probability density function of 3D NAND flash memory by taking major sources of errors. Based on the derived channel probability density function, the mutual information (MI) for 3D flash memory with multiple layers is derived and used as a metric to design the quantization. Specifically, we propose a dynamic programming algorithm to jointly optimize read-voltage thresholds for all layers by maximizing the MI (MMI). To further reduce the complexity, we develop an MI derivative (MID)-based method to obtain read-voltage thresholds for hard-decision decoding (HDD) of error correction codes (ECCs). Simulation results show that the performance with jointly optimized read-voltage thresholds can closely approach that with read-voltage thresholds optimized for each layer, with much less read latency. Moreover, the MID-based MMI quantizer almost achieves the optimal performance for HDD of ECCs.

Soviet criminal-executing system as a tool of totalitarianism

Purpose. The purpose of the study is to reveal the legal foundations of the formation of the Soviet criminal-executive system and its qualification as a tool of totalitarianism. Methods. The article uses a set of principles and methods of scientific knowledge, in particular the principles of objectivity and historicism, as well as methods of analysis and synthesis, generalization, legal, formal-legal, system-historical, retrospective analysis, dialectical, phenomenological, hermeneutic and systemic. A theoretical analysis of the concepts of «totalitarianism» and «criminal-executive system» was carried out, approaches to understanding their content among Ukrainian and foreign scientists were considered. Results. The author's understanding of the concept of the criminal-executive system was formed as a set of authorities that were responsible for the execution of criminal punishments and probation and implemented not only an educational and correctional function, but they were a tool of the political regime in the fight against internal opposition. The Soviet criminal-executive system was directly involved in the implementation of the so-called «great terror», and until the 1960s it had a distinct correctional and labor character. Confirmation of the totalitarian character of the criminal-executive system of the Soviet era are the very norms of law that regulated its formation and development. Thus, the ideologues of Bolshevism immediately pointed out the punitive nature of criminal legislation. In the 1930s, in the context of the adoption of emergency legislation and, in particular, the adoption of a number of amendments to the Criminal and Criminal Procedure Codes, the Correctional Labor Code of 1925 lost legal force, and correctional legislation was regulated by the norms of emergency law. The system of execution of punishments was finally regulated only with the adoption of the Correctional and Labor Code of the Ukrainian SSR in 1970. The latter approved a harsh, inhumane system, which focused its attention on the complete exploitation of persons serving sentences. A conclusion has been made about the perspective of studying the Soviet criminal-executive system, in particular in terms of fixing numerous crimes against persons who were serving sentences, rehabilitation of victims of totalitarianism, as well as improvement of the current legislation of Ukraine. Originality. The regularities of the formation and evolution of the criminal-executive system of the Ukrainian SSR have been established, and the signs that allow it to be qualified as totalitarian have been determined. Practical significance. The results of the research can be used in the process of historical and legal research, preparation of special courses.