SoC Cores Research Articles

공원녹지기본계획을 위한 공원결핍지수 적용방안 - 서산시를 중심으로 -

Globally, international organizations such as OCED and the UN are raising inclusive growth and inclusive city issues to resolve inequality, and accordingly, the Korean government is trying to establish a core SOC by 2022 by announcing the "Three-Year Living SOC Plan." In order to resolve inequality and imbalance, measures are being taken to change inclusive growth, inclusive city issues, and policies on park green areas. The purpose of this study is to suggest a plan to select areas with relatively high park policy needs by applying indicators that derive objective results when creating and planning parks among the basic park green areas using alternative indicators. As a research method, concepts were established through existing related literature, and the park deficiency index was derived through expert surveys of 34 related public officials, researchers, and industry workers who are landscape experts. Although this study derived the park deficiency index, it is necessary to conduct a study to verify its effectiveness through the creation of parks reflecting the park deficiency index and the implementation of policy projects in order to apply it to the park green policy.

High Priority Arbitration for Less Burst Data Transactions for Improved Average Waiting Time of Multi-Processor Cores

The multi-processor cores in SoC which have high burst data transactions can play a critical role while accessing the shared resources such as the off-chip memory. These processor cores can starve other processor cores that have less burst data transactions while accessing the same shared resources. The starving issue of other processor cores leads to degrade the entire system performance of the SoC. However, the arbiter architecture in the SoC design plays the best solution to manage different processor core requests and granting one of them to access the shared resources according to different scheduling algorithms. In this paper, we have designed AXI interconnect, which includes arbiter architecture to connect four processor cores represented by the AXI masters and the off-chip memory represented by the salve. Each processor core (AXI Master) uses the AXI4 interface protocol to improve the system performance and the arbiter based on the static fixed-priority algorithm to improve the average waiting time for all the processor cores. The SoC design architecture is modeled in System Verilog HDL; simulation and synthesis are done by using the Vivado tool and FPGA ZYNQ-7 ZC702 Evaluation Board (xc7z020clg484-1).

DESIGN OF FIR FILTER ALGORITHM FOR NOISE REMOVAL IN ECG SIGNAL USING OPEN CORE SoC

The emerging technology in computer architecture has led to the development of various ISAs depending on the needs of the desired technology, architectures, and processor cores. Instruction Set Architectures (ISAs) for processors from Intel, AMD, Intel, RISC-V, etc. This has provided the path to implement various functions on an open core SoC Platform. Among the many DSP applications, the FIR filter has been implemented on an open core SoC platform that uses RISCV. Here specifically filtering of noise from ECG signal. The performance cycle count has been obtained for the same and compared with its counterpart ARM M7 on the Keil platform.

Applying Genetic Algorithm to Solve Partitioning and Mapping Problem for Mesh Network-on-Chip Systems

This paper presents a genetic based approach to the partitioning and mapping of multicore SoC cores over a NoC system that uses mesh topology. The proposed algorithm performs the partitioning and mapping by reducing communication cost and minimizing power consumption by placing those intercommunicated cores as close as possible together. A program developed in C++ in which the provided specification of the multicore MPSoC system captures all data dependencies before any start of the design process. Experimental results of several multimedia benchmarks demonstrates that the genetic-based approach able to find different satisfied implementations to the problem of partitioning and mapping of MPSoC cores over mesh-based NoC system that satisfies design goals.

Applying Genetic Algorithm to Solve Partitioning and Mapping Problem for Mesh Network-on-Chip Systems

This paper presents a genetic based approach to the partitioning and mapping of multicore SoC cores over a NoC system that uses mesh topology. The proposed algorithm performs the partitioning and mapping by reducing communication cost and minimizing power consumption by placing those intercommunicated cores as close as possible together. A program developed in C++ in which the provided specification of the multicore MPSoC system captures all data dependencies before any start of the design process. Experimental results of several multimedia benchmarks demonstrates that the genetic-based approach able to find different satisfied implementations to the problem of partitioning and mapping of MPSoC cores over mesh-based NoC system that satisfies design goals.

同步TP RAM的低功耗设计方法

针对SoC中同步TP RAM的功耗较大问题，提出一种设计方法。通过将SoC中的同步TP RAM替换成SP RAM，在SP RAM外围增加读写接口转换逻辑，使替换后的RAM实现原TP RAM的功能，保持对外接口不变。为了进一步降低功耗，对地址总线进行格雷编码，采用动态电压调整技术及合理的电源分区策略。将文中方法应用于一款多核SoC芯片，经TSMC 28 nm HPC工艺实现。仿真结果表明：优化后的RAM面积减少了24.76%，功耗降低了44.89%。 As the power consumption of synchronous TP RAM in SoC is large, a new design method of opti-mization is proposed. In order to achieve the function of the original TP RAM and keep the exter-nal interface unchanged, TP RAM is replaced with SP RAM, and read-write interface logics of con-version are added around SP RAM. For less power, address bus is encoded through Gray code; dynamic voltage regulation and reasonable power partition strategy are used. The method discussed in this paper is used in the multi core SoC chip which has been implemented in TSMC 28nm HPC process. The simulation results indicate that the area of optimized RAMs is reduced by 24.76%, and the power saving is reduced by 44.89%.

TP RAM的低功耗设计及应用

针对SoC中TP RAM的面积及功耗较大问题，提出一种优化设计方法。通过将SoC中的TP RAM替换成SP RAM，并在SP RAM外围增加读写接口转换逻辑，使替换后的RAM实现原TP RAM的功能，保持对外接口不变。将文中方法应用于一款多核SoC芯片，该芯片经TSMC 28 nm HPM工艺成功流片，die size为10.7 mm × 11.9 mm，功耗为19.8 W。测试结果表明：优化后的RAM面积减少了24.5%，功耗降低了45.16%。 As the area and power consumption of TP RAM in SoC are large, a new design method of optimization is proposed. In order to achieve the function of the original TP RAM and keep the external interface unchanged, TP RAM is replaced with SP RAM, and read-write interface logics of conversion are added around SP RAM. The method discussed in this paper is used in the multi core SoC chip which has been successfully taped out in TSMC 28 nm HPM process. The chip occupies 10.7 mm × 11.9 mm of die area and consumes 19.8 W. The testing results indicate that the area of optimized RAM is reduced by 24.5%, and the power saving is 45.16%.

Implementation of SOC Core for IOT Engine

Implementation of SOC Core for IOT Engine

SOC Test Compression Scheme Sharing Free Variables in Embedded Deterministic Test Environment

This paper presents a new SOC test compression scheme in Embedded Deterministic Test (EDT) compression environment. Compressed test data is brought over the TAM from the tester to the cores in SOC and decompressed in the cores. The proposed scheme allows cores tested at the same time to share some test channels. By sharing free variables in these channels across test cubes of different cores decompressed at the same time, high encoding efficiency is achieved. Moreover, no excess control data is required in this scheme. The ability to reuse excess free variables eliminates the need for high precision in matching the number of test channels with the number of care bits for every core. Experimental results obtained for some SOC designs illustrate effectiveness of the proposed test application scheme.

Reconfigurable wrapper architecture for UART CORE testing using FSM approach

The UART is a device used for communication of data either in asynchronous or synchronous mode. Nowadays, more number of designers introduces UART as a system on chip for various purposes. These UART SoC cores are to be checked on the basis of its compatibility and performance and a complete study is advisable. For this purpose, a reusable and reconfigurable wrapper architecture is designed, which is based on a finite machine called the wrapper finite state machine WFSM in Verilog and its baud rate as well as frame bit rate is computed. This WFSM monitors and verifies bit rate, packet transmission with single stop bit and two stop bits, with and without parity bits, distance coverage, frame transmission time, junk handling, utilisation of CUP, utilisation of power by UART with wrapper in FPGA are studied at different baud rates. It is designed and implemented in Quarters II in CyclonII DEI FPGA with the help of Zero-Plus logic analyzer.

Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding

Growing test data volume and excessive test application time are two serious concerns in scan-based testing for SoCs. This paper presents an efficient test-independent compression technique based on block merging and eight coding (BM-8C) to reduce the test data volume and test application time. Test compression is achieved by encoding the merged blocks after merging consecutive compatible blocks with exact eight codewords. The proposed scheme compresses the pre-computed test data without requiring any structural information of the circuit under test. Therefore, it is applicable for IP cores in SoCs. Experimental results demonstrate that the BM-8C technique can achieve an average compression ratio up to 68.14 % with significant low test application time.

A Fault Analysis Perspective for Testing of Secured SoC Cores

Can the inputs of a cryptocore be stressed to leak the secret key? This article demonstrates such a vulnerability challenging secure integration of these cores in a system-on-chip design.

Thermal-aware test scheduling using network-on-chip under multiple clock rates

The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an optimal integer linear programming (ILP) formulation and a simulated annealing (SA) solution to thermal and power-aware test scheduling of cores in an NoC-based SoC using multiple clock rates. The methods have been implemented and results on various benchmarks are presented.

On-Chip Interconnect mechanism based on CDMA

The integration of complete Network-on-chip (NoC) designs consisting of large number of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically feasible. But, the communication between the IP Cores is the main issue in recent years. This paper presents an On-Chip interconnect mechanism as a component of Code Division Multiple Access (CDMA) for shared bus architecture to communicate between IP cores in SoC. In the proposal, only bus lines that carry address and data signals are CDMA coded. CDMA technology has better channel isolation, channel continuity, data integrity and also reduces the number of lines in the shared bus for transmitting the data from master to slave

An Automatic SoC Design Methodology for Integration and Verification

The increasing complexity of current SoC design brings a great challenge to SoC designer for fast SoC RTL integration and effective verification. In this paper, an automatic SoC integration methodology based on IP-XACT standard is proposed as a complete and effective solution for low-level RTL simulation, FPGA emulation and ASIC implementation. A bottom-up approach is adopted for design integration and verification from component level, to SoC core level, and then to final chip level. The three-core MPSoC case study not only gives the detailed usage and analysis on the proposed methodology, but also shows its efficiency to integrate a complex SoC design and its feasibility for correct SoC implementation.

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.

Optimal Test Time for System-on-Chip Designs using Fuzzy Logic and Process Algebra

Problem statement: Test scheduling is crucially important for optimal SoC test automation to allocate the limited available test resources. In this study we introduced a fuzzy based engine to allocate test resources. The minimized test application time can be achieved by test pipelining. However the test power consumption incurred during test procedure must be controlled in order not to offend the allowed maximal power dissipation thus avoiding damaging the system under test. Approach: Process algebra is the adept to deal with concurrent behaviors, based on this, the test scheduling scheme for SoC cores concurrent test is outlined by mapping the parallel test actions into concurrent processes. The algorithm for SoC test scheduling based on process algebra under multiple constraints (test power dissipation, test resources and test priorities) and apply a fuzzy based optimum search for a solution to the scheduling problem. Results: The test application time was calculated for three ITC-02 SOC benchmark circuits and the results were compared with other approaches. Conclusion: The results showed for ITC-02 benchmarks circuits prove the effectiveness of our proposed method.

Split variable-length input Huffman code with application to test data compression for embedded cores in SOCs

In this article, a run length encoding-based test data compression technique has been addressed. The scheme performs Huffman coding on different parts of the test data file separately. It has been observed that up to a 6% improvement in compression ratio and a 29% improvement in test application time can be achieved sacrificing only about 6.5% of the decoder area. We have compared our results with the other contemporary works reported in the literature. It has been observed that for most of the cases, our scheme produces a better compression ratio and that the area requirements are much less.

Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip

A system-on-a-chip (SoC) built with embedded intellectual property (IP) cores offers attractive methodology design reuse, reconfigurability, and customizability. However, the integration of the design-for-testability (DfT) structures of the IP cores in these complex SoCs presents daunting challenges to designers and ultimately affects the time-to-market goals. In this paper, we introduce a design methodology to reduce the time to market by taking core test data from the design environment and automatically generating DfT structures that can easily be integrated into the SoC. A novel automated synthesis methodology to generate an SoC built-in self-test (BIST) to test the IP and custom logic cores is proposed. The proposed technique, i.e., NonExclusive Xor Test of 2D linear feedback shift register (NEXT 2D LFSR), is modeled after the principle of configurable 2D LFSR design, which generates a deterministic sequence of test vectors for random-vector-resistant faults and then random test vectors for random-vector-detectable faults. The basis of this method is to explore the design solution space for optimal 2D LFSR while embedding the test patterns by nonexclusively considering xor gates as the conventional LFSR does but including a simple logic solution for minimal hardware optimization. Moreover, the proposed approach is capable of optimizing the 2D LFSRs with consideration of the don't-care bits in the incompletely specified test patterns.

HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit media embedded processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb system-in-silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 mum CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 mm2 die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.