Copy Operations Research Articles

Dynamic garbage collection scheme based on past update times for NAND flash-based consumer electronics

NAND flash memory has become the dominant storage device for consumer electronics such as smart phones, portable personal computers, and digital cameras. Because NAND flash memory often introduces an out-of-place update scheme to solve its erase-before-write hardware constraint, these consumer electronics devices should perform garbage collection to reclaim garbage and obtain free space. However, existing garbage collection schemes usually suffer from the high garbage collection overhead and the high degree of wear leveling. In this paper, a dynamic garbage collection scheme based on past update times is proposed for NAND flash-based consumer electronics. The proposed scheme can achieve a balance between the garbage collection overhead and the degree of wear leveling. Experimental results show that the proposed scheme is better than existing garbage collection schemes in terms of the number of copy operations, the number of erase operations, the energy consumption, and the degree of wear leveling.

All Spin Logic: A Micromagnetic Perspective

Most investigations of all spin logic (ASL) have been based on the monodomain approximation of magnetization switching. The sensitive and stochastic nature of spin transfer torque (STT) switching creates pressing requirements for analyzing ASL from a micromagnetic perspective also. Hence, in this paper, ASL is studied from a micromagnetic perspective by developing a simulation framework that can capture diffusive spin transport. The spin transport model is calibrated from the existing experimental results on nonlocal spin valve measurements. Then, using this framework, STT switching is studied for input–output nanomagnets with in-plane and perpendicular magnetic anisotropy for ASL devices (ASLDs). Precisely defined architecture and design constraints for such input–output nanomagnets are presented. Further, a previously proposed switching mechanism by driving the nanomagnet into a metastable state is also incorporated into micromagnetic framework. Using the aforementioned mechanism, the critical current required for STT switching can be reduced to as low as 20 $\mu $ A. Moreover, the graphene channel ASLD using tunnel contact at the injector is demonstrated for copy and invert logic operations.

Novel Buffered Magnetic Logic Gate Grid

After many decades of steep progress in semiconductor industry the performance gain due to CMOS scaling will stop in the foreseeable future. This stems from the sharp risein factory costs and the growing severeness of physical limits. Power dissipation caused by leakage especially in mobile devices becomes a critical burden nowadays. A simple way to reduce power dissipation and the total power consumption is to shut downidle circuit parts. However, when these circuits are activated their previous state mustbe recovered. In order to avoid energy and time consuming recovery cycles non-volatile elements must be added to realize the desired instant ON capability. Here, spintronics is very appealing due to its non-volatility, fast switching, and high endurance.Even though some feasible solutions are already available and competitive with respect to energy consumption and speed, e.g. magnetic tunnel junction (MTJ) MRAM [1] and non-volatile CMOS MTJ hybrid circuits [2], they are still not able to challenge pure CMOS with regard to integration density. The reason is that the spintronic elements (commonly MTJs) are introduced as mere memory, while the actual computation is carried out by CMOS transistors. Therefore, additional transistors are required to read and write the MTJs, which rather leads to a decrease in integration density and power increase. Therefore, we propose a magnetic non-volatile flip flop [3] anda magnetic non-volatile shift register [4], which perform the actual computation also in the magnetic domain, thus, reducing complexity and allowing extremely small foot prints.In this work we present an extension of our idea for sequential logic towards a novel non-volatile magnetic logic gate grid facilitating non-volatile magnetic flip flops as bufferas well as shared memory. The magnetic logic gate grid comprises spin transfer torque (STT) majority gates and thenon-volatile flip flops and are positioned at two different levels. The STT majority gates are structurally and operationally compatible with the non-volatile flip flops [5].The majority gates are arranged in an array and linked to their respective neighbors by the non-volatile magnetic flip flops (see Fig. 1). This arrangement holds the benefits of a very dense layout, a highly regular structure, allows parallel execution of operations on the logic gates, and minimizes theenergy and time spend for information transport. It also supports the shift away from the Von Neumann architecture and its currently performance limiting continuous information flow between physically separated memory and computation units. Even more, the generic layout of the structure not only eases manufacturing, but also enables, together with the majority gates, highly reconfigureable logic and flexible allocation of employed resources like the number of used gates and buffers depending on the requirements of the task at hand. In order to illustrate the idea, consider a practical example like a full adder implemented in such a structure. A 1-bit full adder has three inputs A,B,Cin and two outputs Sum and Cout. The carry bit Cout is defined as Majority(A,B,Cin) and the Sum as A XOR B XOR Cin. In a first step Majority(A,B,Cin) is calculated and copied into a first flip flop FF1. Then Majority(A,B,NOT(Cin)) is calculated and copied into a second flip flop FF2. Finally Majority(NOT(FF1)),FF2,Cin) is calculated by using the results from the previous steps stored in FF1 and FF2 to calculate the Sum, which again is stored in a third flip flop FF3.One has to note that for a functional complete system negation must be available. This is realized by inverting the polarity of the applied pulse. Thus, Cout and Sum are calculated via a well defined set of subsequent majority and copy operations in the magnetic domain only. Since Cout and Sum are stored in the flip flops FF1 and FF3 and these are also accessible by neighboring gates their informationcan be used for futher processing elsewhere. This research is supported by the European Research Council through the Grant #247056 MOSILSPIN.

Impact of Developer Choices on Energy Consumption of Software on Servers

The power cost of running a data center is a significant portion of its total annual operating budget. With the aim of reducing power bills of data centers, “Green Computing” has emerged with the primary goal of making software more energy efficient without compromising the performance. Developers play an important role in controlling the energy cost of data center software while writing code. In this paper, we show how software developers can contribute to energy efficiency of servers by choosing energy efficient APIs (Application Programming Interface) with the optimal choice of parameters while implementing file reading, file copy, file compression and file decompression operations in Java; that are performed extensively on large scale servers in data centers. We performed extensive measurements of energy cost of those operations on a Dell Power Edge 2950 machine running Linux and Windows servers. Measurement results show that energy costs of various APIs for those operations are sensitive to the bu ff er size selection. The choice of a particular Java API for file reading with different buffer sizes has significant impact on the energy cost, giving an opportunity to save up to 76%. To save energy while copying files, it is important to use APIs with tunable buffer sizes, rather than APIs using fixed size buffers. In addition, there is a trade off between compression ratio and energy cost: because of more compression ratio, xz compression API consumes more energy than zip and gzip compression APIs. Finally, we model the energy costs of APIs by polynomial regression to avoid repeated measurements.

An efficient file-aware garbage collection algorithm for NAND flash-based consumer electronics

The use of NAND flash memory is increasing in consumer electronics. Because an out-of-place update scheme is used to address the erase-before-write hardware constraint in NAND flash memory, a garbage collection algorithm should be designed into the flash translation layer (FTL) or the flashspecific file system to reclaim garbage pages and obtain free space. In this paper, an efficient file-aware garbage collection algorithm, called FaGC, is proposed for NAND flash memory systems in consumer electronics. The purpose of the proposed algorithm is to reduce garbage collection overhead and improve wear leveling in NAND flash memory systems. The experimental results show that the proposed algorithm outperforms existing garbage collection algorithms in terms of the number of copy operations, the number of erase operations, and the degree of wear leveling. Additionally, with limited cost, a desired degree of wear leveling can be achieved using a predesignated value, which is advantageous for NAND flash memory systems in consumer electronic devices.

Image Tampering with Evidence Algorithm Based on Copy and Paste

Authenticity, integrity and authentication primitive technology for digital image content case of digital image forensics, as one branch of information security technology, is not pre-embedded image watermarks to forensic identification. In this paper, a common digital image tampering copy and paste operations have been studied and proposed detection method for this operation to improve the robustness of the algorithm.

Round Descriptor Based on SIFT Operator Copy and Paste Forensics

Powerful digital cameras and image processing software, so that the image of tampering counterfeit technology is developing rapidly, the role of digital images to verify the authenticity and the beginning of forensics technology will become more important. For the most common digital image tampering copy and paste operation, this paper presents a round-based SIFT descriptor operator forensic image copy and paste algorithm that extracts the image to be detected circular feature vector descriptor, and using feature vectors copy and paste the image matching to detect and locate the area. Experiments show that the method of image rotation, zoom, blur, noise and other image processing operations are robust, able to quickly and effectively detect tampering in digital images traces copy and paste operations, and is able to copy and paste the region for accurate positioning.

Swap-aware garbage collection algorithm for NAND flash-based consumer electronics

NAND flash memory is a popular storage device for consumer electronics and it is exploited to be swap space for extending the limited main memory of consumer electronics. Due to the out-of-place update scheme provided by NAND flash memory to solve its erase-before-write hardware constraint, garbage collection should be performed to reclaim garbage in terms of invalid pages and obtain free space in terms of free blocks. The garbage collection, which consists of a series of copy operations and erase operations, is energy-consuming. In order to reduce the energy consumption, a swap-aware garbage collection algorithm for NAND flash-based consumer electronics is proposed in this paper. The proposed algorithm focuses on reducing the garbage collection overhead and improving the endurance of NAND flash memory. Experimental results show that the proposed algorithm is superior to the existing garbage collection algorithms in terms of the number of copy operations, the number of erase operations, the degree of wear-leveling, and energy consumption.

Sound input filter generation for integer overflow errors

We present a system, SIFT, for generating input filters that nullify integer overflow errors associated with critical program sites such as memory allocation or block copy sites. SIFT uses a static pro- gram analysis to generate filters that discard inputs that may trigger integer overflow errors in the computations of the sizes of allocated memory blocks or the number of copied bytes in block copy operations. Unlike all previous techniques of which we are aware, SIFT is sound -- if an input passes the filter, it will not trigger an integer overflow error at any analyzed site. Our results show that SIFT successfully analyzes (and therefore generates sound input filters for) 56 out of 58 memory allocation and block memory copy sites in analyzed input processing modules from five applications (VLC, Dillo, Swfdec, Swftools, and GIMP). These nullified errors include six known integer overflow vulnerabilities. Our results also show that applying these filters to 62895 real-world inputs produces no false positives. The analysis and filter generation times are all less than a second.

A real-time flash translation layer via adaptive partial garbage collection

In real-time embedded systems with flash storage memory, partial garbage collection is used to avoid long response latency and provide guaranteed response time upper bound. However, existing partial garbage collection schemes involve too many valid page copy and erase operations, which results in degradation in both system average performance and endurance of flash memory. To solve this problem, in this paper, we propose a real-time hybrid-level flash translation layer (FTL) called RAFTL – a real-time FTL using an adaptive partial garbage collection policy. RAFTL allocates physical blocks mapped to the same logical block on demand to postpone the partial garbage collection process. Moreover, we adopt an adaptive partial garbage collection policy, which combines the centralised and the distributed partial garbage collection policies. The experimental results show that our scheme reduces the valid page copy and erase operations significantly. Also, on the basis of providing a guaranteed worst case system response time, RAFTL provides an average write request response time which is approximate to the time to write one page.

A novel classification model for data theft detection using advanced pattern mining

One of the challenges in data theft detection is the difficulty to classify copy operation from other type of access (non-copy) operations. Existing work in this area focuses on the stochastic model of filesystem behavior to identify emergent patterns in MAC timestamps unique to copying. Such an approach produces lot of false positives because of the fact that patterns emerging due to copying are similar to other access operations like searching a file in folder, compressing a folder, scanning a folder by antivirus software and recursive listing of directory entries from a command prompt. A novel classification model is proposed for detection of data theft by means of copy operation. Experiments were conducted by making use of advanced pattern mining algorithms such as ANFIS (Adaptive Network-based Fuzzy Inference System), ANN (Artificial Neural Networks) and C&RT (Classification & Regression Trees). All the experiments were conducted on three different operating systems i.e. Windows XP, Ubuntu and Windows 7. Henceforth the approach is validated against a simulated data theft event and analysis of the results revealed that C&RT based approach is most appropriate for data theft detection. The proposed classification model can be used by digital forensic investigators to filter out the most important artefacts and prioritize their investigation while investigating a data theft case.

Graphics processing unit accelerated one‐dimensional blood flow computation in the human arterial tree

One-dimensional blood flow models have been used extensively for computing pressure and flow waveforms in the human arterial circulation. We propose an improved numerical implementation based on a graphics processing unit (GPU) for the acceleration of the execution time of one-dimensional model. A novel parallel hybrid CPU-GPU algorithm with compact copy operations (PHCGCC) and a parallel GPU only (PGO) algorithm are developed, which are compared against previously introduced PHCG versions, a single-threaded CPU only algorithm and a multi-threaded CPU only algorithm. Different second-order numerical schemes (Lax-Wendroff and Taylor series) are evaluated for the numerical solution of one-dimensional model, and the computational setups include physiologically motivated non-periodic (Windkessel) and periodic boundary conditions (BC) (structured tree) and elastic and viscoelastic wall laws. Both the PHCGCC and the PGO implementations improved the execution time significantly. The speed-up values over the single-threaded CPU only implementation range from 5.26 to 8.10 × , whereas the speed-up values over the multi-threaded CPU only implementation range from 1.84 to 4.02 × . The PHCGCC algorithm performs best for an elastic wall law with non-periodic BC and for viscoelastic wall laws, whereas the PGO algorithm performs best for an elastic wall law with periodic BC.

Data-assemblage: a translation-page-aware data block allocation strategy for flash-based solid state drives

Flash-based solid state drives (SSDs) are becoming popular as the storage media in recent years. In SSDs, translation pages normally store the address mapping information for data blocks. With the increasing capacity of SSDs, the management of translation pages is becoming a critical issue. In this paper, we present Data-Assemblage, a translation-page-aware data block allocation strategy for demand-based page-level address mappings in flash-based SSDs. Data-Assemblage is motivated by two observations: First, the translation page copy operations during garbage collection may significantly degrade the system performance. Second, the allocation of data blocks will directly impact the update operations in translation pages. By assembling write requests that share the same translation page into one data block, Data-Assemblage significantly reduces the page copies of translation pages and improves the average response time while retaining its space utilization and RAM cost. We evaluate Data-Assemblage using a set of benchmarks from both real-world and synthetic traces. Experimental results show that our scheme can achieve a 90.92 % reduction in the extra translation overhead and improve system performance by 22.14 % compared with the previous work.

A constraint programming approach for integrated spatial and temporal scheduling for clustered architectures

Many embedded processors use clustering to scale up instruction-level parallelism in a cost-effective manner. In a clustered architecture, the registers and functional units are partitioned into smaller units and clusters communicate through register-to-register copy operations. Texas Instruments, for example, has a series of architectures for embedded processors which are clustered. Such an architecture places a heavier burden on the compiler, which must now assign instructions to clusters (spatial scheduling), assign instructions to cycles (temporal scheduling), and schedule copy operations to move data between clusters. We consider instruction scheduling of local blocks of code on clustered architectures to improve performance. Scheduling for space and time is known to be a hard problem. Previous work has proposed greedy approaches based on list scheduling to simultaneously perform spatial and temporal scheduling and phased approaches based on first partitioning a block of code to do spatial assignment and then performing temporal scheduling. Greedy approaches risk making mistakes that are then costly to recover from, and partitioning approaches suffer from the well-known phase ordering problem. In this article, we present a constraint programming approach for scheduling instructions on clustered architectures. We employ a problem decomposition technique that solves spatial and temporal scheduling in an integrated manner. We analyze the effect of different hardware parameters—such as the number of clusters, issue-width, and intercluster communication cost—on application performance. We found that our approach was able to achieve an improvement of up to 26%, on average, over a state-of-the-art technique on superblocks from SPEC 2000 benchmarks.

Efficient and intelligent garbage collection policy for NAND flash-based consumer electronics

Because NAND flash memory provides the out-of-place update scheme to address its erase-before-write hardware constraint, garbage collection policy is included in the flash-aware file systems and flash translation layer (FTL) to reclaim garbage and obtain free space. In this paper, an efficient and intelligent garbage collection policy is proposed for NAND flash-based consumer electronics, which is called EIGC. EIGC introduces an efficient grey prediction model for forecasting the future I/O workload during the next garbage collection operation execution time interval and determines the number of victim blocks that should be selected for evicting according to the predicted I/O workload. In order to reduce the cleaning cost in terms of the cost for copying the valid pages to the free space of NAND flash memory and improve the degree of wear leveling, an efficient victim block selection scheme is included in the proposed EIGC policy. Trace-driven simulations show that the proposed EIGC policy is superior to the state-of-the-art policies in terms of the number of copy operations, the number of erase operations, and the degree of wear leveling.

SSR-CDPS: A Novel Continuous Data Protection System Supporting Service Recovery

With the rapid development of computer networks, invasion and attack becomes more and more frequent in network environment. Therefore, insuring the information system continuously and correctly working has become an urgent problem in the information security field. And continuous data protection (CDP) supporting service recovery provides us a good idea to resolve it. In this article, we have designed and implemented a continuous data protection system supporting service recovery, which is named SSR-CDPS. The basic design idea of the SSR-CDPS architecture is dividing the whole protection process into three stages: monitoring, protecting and recovery. Meanwhile, we propose a multi versioning data backup mechanism for the protecting process and a novel file failure recovery mechanism. Especially, we transfer the full copy operation of file contents into the merely slight modification operation on the FAT table, MFT table or other similar data structures; so that we achieve the aim of greatly reducing the direct disks read and write overhead. The test toward the SSR-CDPS prototype system shows that the system can significantly improve the efficiency of data protection within limited change to the existing file system; thus, it can meet the high real-time and the continuity requirements of the information system recovery applications.

Garbage collection policy to improve durability for flash memory

Flash memory adopts out-of-place update scheme to solve the erase-before-write constraint of flash memory and the free space of flash memory could be used up. Therefore, garbage collection policy is needed to reclaim garbage and obtain free space. The cleaning cost and the degree of wear-leveling are two primary concerns of garbage collection policy. To achieve these two design principles, we propose an efficient least-first garbage collection policy called LFGC to improve durability for flash memory. LFGC links all the dirty blocks by a list in order of the number of erase operations of each block and divides the list into two regions, which are resident region and candidate region. LFGC introduces an efficient victim block selection method to improve the durability for flash memory and prevent increasing the cleaning cost. An efficient cold-detection scheme is also introduced to identify hot valid page and cold valid page when the copy operation happens during the garbage collection policy. Experimental results show that our proposed LFGC outperforms existing garbage collection policies in terms of the number of copy operations, the number of erase operations, and the degree of wear-leveling.

Universal petri net

A universal inhibitor Petri net executing an arbitrary given inhibitor Petri net is constructed. An inhibitor Petri net graph, its marking, and transition firing sequence are encoded as 10 scalar nonnegative integer variables and are represented by the corresponding places of the universal net. An algorithm using only these scalar variables and executing an arbitrary inhibitor net is developed based on the state equation and is encoded by the universal inhibitor Petri net. Subnets that implement arithmetic, comparison, and copy operations are employed.

Eliminating read barriers through procrastination and cleanliness

Managed languages typically use read barriers to interpret forwarding pointers introduced to keep track of copied objects. For example, in a multicore environment with thread-local heaps and a global, shared heap, an object initially allocated on a local heap may be copied to a shared heap if it becomes the source of a store operation whose target location resides on the shared heap. As part of the copy operation, a forwarding pointer may be established in the original object to point to the copied object. This level of indirection avoids the need to update all of the references to the object that has been copied. In this paper, we consider the design of a managed runtime that eliminates read barriers. Our design is premised on the availability of a sufficient degree of concurrency to stall operations that would otherwise necessitate the copy. Stalled actions are deferred until the next local collection, avoiding exposing forwarding pointers to the mutator. In certain important cases, procrastination is unnecessary -- lightweight runtime techniques can sometimes be used to allow objects to be eagerly copied when their set of incoming references is known, or when it can be determined that having multiple copies would not violate program semantics. We evaluate our techniques on 3 platforms: a 16-core AMD64 machine, a 48-core Intel SCC, and an 864-core Azul Vega 3. Experimental results over a range of parallel benchmarks indicate that our approach leads to notable performance gains (20 - 32% on average) without incurring any additional complexity.

GReTL: an extensible, operational, graph-based transformation language

This article introduces the graph-based transformation language GReTL. GReTL is operational, and transformations are either specified in plain Java using the GReTL API or in a simple domain-specific language. GReTL follows the conception of incrementally constructing the target metamodel together with the target graph. When creating a new metamodel element, a set-based semantic expression is specified that describes the set of instances that have to be created in the target graph. This expression is defined as a query on the source graph. GReTL is a kernel language consisting of a minimal set of operations, but it is designed for being extensible. Custom higher-level operations can be built on top of the kernel operations easily. After a description of the foundations of GReTL, its most important elements are introduced along with a transformation example in the field of metamodel integration. Insights into the design of the GReTL API are given, and a convenience copy operation is implemented to demonstrate GReTL's extensibility.