CORDIC Research Articles

Energy Efficient Quality Tunable CORDIC for DSP Applications on Battery Operated Portable Devices

COrdinate Rotation DIgital Computer (CORDIC) is commonly utilized for the computation of cosine/sine i.e., the trigonometric functions, singular value decomposition, in digital signal processing (especially in image/video processing), etc. This paper introduces an energy efficient quality tunable CORDIC architecture that computes the cosine/sine values of any required angle in real-time, and is thus well suited for real time DSP applications, especially for image or video processing applications. The proposed architecture reduces the latency and overcomes data dependency by simultaneously performing all the five iterations, that may vary depending upon the desired energy efficiency. The novelty of this architecture is that, desired quality can be achieved by selecting one out of the available three modes. In order to assess the efficacy of the suggested architecture, some benchmark images are processed using the Discrete Cosine Transform (DCT) coefficients obtained via the proposed design. Energy saving is achieved at the cost of slight acceptable degradation in the output image quality. Further, the simulation results show that the proposed architecture is 92.3%, 2.8% and 49.08% more energy efficient than the existing basic, scale-free and lookahead CORDIC architectures, respectively.

Evaluation of a Heterogeneous Multicore Architecture by Design and Test of an OFDM Receiver

This paper presents an evaluation of a Heterogeneous Multicore Architecture (HMA) by implementing Orthogonal Frequency-Division Multiplexing (OFDM) receiver blocks as designs for the test of functionality. OFDM receiver consists of computationally intensive and general-purpose processing tasks that can provide maximum coverage to test and evaluate a massively-parallel as well as a general-purpose platform like the HMA. The blocks of the receiver are primarily designed by crafting template-based Coarse-Grained Reconfigurable Array (CGRA) devices and then arranging them in a sequence over a Network-on-Chip (NoC) structure along with a few RISC cores for complete OFDM processing. The OFDM blocks such as Fast Fourier Transform (FFT) and Time Synchronization are computationally intensive and require parallel processing. The OFDM receiver also contains tasks such as frequency offset estimation which require the processing of Taylor series and CORDIC algorithms that are serial in nature. Such a combination of serial and parallel algorithms can perform a thorough exploration and evaluation of almost all the design features of an HMA. The OFDM implementation has led to scale CGRAs to different dimensions, instantiate Processing Elements (PEs) as multiple arithmetic resources and to establish almost all possible ways of PE interconnections. It further explores time-multiplexed patterns for data placement in the CGRA memories. Nevertheless, the data can also be exchanged among different nodes over NoC structure simultaneously and independently by using direct memory access devices. In this experimental work, the performance of each CGRA, the collective performance of the whole platform and the NoC traffic are recorded in terms of the number of clock cycles and several high-level performance metrics. Today's HMAs are generally over or under resourced for the applications that they are designed for and thus not an optimal choice for the end user. Apart from the interesting comparisons to the other state-of-the-art, our experimental setup has provided important insight and guidelines that the designers can use to implement near-optimal solutions for their target applications.

Low-Complexity Methodology for Complex Square-Root Computation

In this brief, we propose a low-complexity methodology to compute a complex square root using only a circular coordinate rotation digital computer (CORDIC) as opposed to the state-of-the-art techniques that need both circular as well as hyperbolic CORDICs. Subsequently, an architecture has been designed based on the proposed methodology and implemented on the ASIC platform using the UMC 180-nm Technology node with 1.0 V at 5 MHz. Field programmable gate array (FPGA) prototyping using Xilinx’ Virtex-6 (XC6v1x240t) has also been carried out. After thorough theoretical analysis and experimental validations, it can be inferred that the proposed methodology reduces 21.15% slice look up tables (on FPGA platform) and saves 20.25% silicon area overhead and decreases 19% power consumption (on ASIC platform) when compared with the state-of-the-art method without compromising the computational speed, throughput, and accuracy.

Sine and Cosine Generator and FIR Filter Designing based on CORDIC Algorithm

Sine and Cosine Generator and FIR Filter Designing based on CORDIC Algorithm

Optimised CORDIC‐based atan2 computation for FPGA implementations

A method for the implementation of the atan2 operator based on the coordinate rotation digital computer algorithm is described. In the proposal, the computation of the z-path takes advantage of the look-up table-based FPGA resources to reduce by between 17 and 25%, without performance deterioration, the overall area of the unrolled architecture.

Simulation of FIR Filter Based on Cordic Algorithm

Simulation of FIR Filter Based on Cordic Algorithm

Givens rotation‐based QR decomposition for MIMO systems

QR decomposition is an essential operation in various detection algorithms utilised in multiple-input multiple-output (MIMO) wireless communication systems. This study presents a Givens rotation-based QR decomposition for 4 × 4 MIMO systems. Instead of performing QR decomposition by coordinate rotation digital computer (CORDIC) algorithms, LUT compression algorithms are employed to rapidly evaluate the trigonometric functions. The proposed approach also provides greater accuracy compared with the CORDIC algorithms. QR decomposition is performed by complex Givens rotations cascaded with real Givens rotations. In complex Givens rotations, a modified triangular systolic array is adopted to reduce the delay units of the design and hence, reducing the hardware complexity. The proposed QR decomposition algorithm is implemented in TSMC 90 nm CMOS technology. It achieves the throughput of 53.5 million QR decompositions per second when operating at 214 MHz.

CORDIC‐based Hann windowed sliding DFT architecture for real‐time spectrum analysis with bounded error‐accumulation

This study presents a COordinate rotation DIgital computer (CORDIC)-based novel architecture combining the sliding discrete Fourier transform (DFT) with Hann windowing to reduce the leakage effect of the DFT spectrum. The proposed architecture also presents a refreshing approach to minimise error due to the finite word-length in the output windowed spectrum compared with the existing method. The architecture can also be extended for other high order generalised cosine windows such as Blackman, Blackman-Harris, and flat-top. The post-route results on the Virtex-6 FPGA as well as the physical ASIC post-layout results are also presented for the proposed architecture.

Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC)

This paper proposes a new approximate scheme for coordinate rotation digital computer (CORDIC) design. This scheme is based on modifying the existing Para-CORDIC architecture with an approximation that is inserted in multiple parts and made possible by relaxing the CORDIC algorithm itself. A fully parallel approximate CORDIC (FPAX-CORDIC) scheme is proposed. This scheme avoids the memory register of Para-CORDIC and makes the generation of the rotation direction fully parallel. A comprehensive analysis and the evaluation of the error introduced by the approximation together with different circuit-related metrics are pursued using HSPICE as the simulation tool. This error analysis also combines existing figures of merit for approximate computing (such as the Mean Error Distance (MED) and MED Power Product (MPP)) with CORDIC specific parameters. It is shown that a good agreement between expected and simulated error values is found. The Discrete Cosine Transformation (DCT) and the Inverse DCT (IDCT) transformations as case study of approximate computing to image processing are investigated by utilizing the proposed approximate FPAX-CORDIC architecture with different accuracy requirements. The results confirm the viability of the proposed scheme.

A Modified Decomposed Vector Rotation-Based Behavioral Model With Efficient Hardware Implementation for Digital Predistortion of RF Power Amplifiers

This paper proposes a novel hardware implementation strategy to achieve low-cost design for digital predistortion of radio frequency power amplifiers (PAs) using a modified decomposed vector rotation-based behavioral model. To make the model hardware friendly, we first modify the model into a subdecomposed format, which significantly reduces the computational complexity in model extraction. We then reassemble the coefficients and propose a simple digital implementation structure for real-time signal processing in the transmit path. A new dual-direction coordinate rotation digital computer design is also proposed to simultaneously calculate both magnitude and ${e}^{j{\theta }_{n}}$ values to facilitate the model implementation. To validate hardware implementation, a wideband signal is employed to evaluate the performance with a Doherty PA. Experimental results show that the proposed approach can achieve comparable performance with much lower system complexity compared with that using the conventional approaches.

An FPGA implementation of novel smart antenna algorithm in tracking systems for smart cities

The area of digital signal processing (DSP) faces a great challenge in suppressing the noise and interference in the transmitting signal. A huge number of applications are in need of such control methods for good audio communication, etc., and the most widespread method for achieving this is through COordinate Rotation DIgital Computer (CORDIC) based on QRD-RLS. However, this method requires several iterations for its calculations, and therefore in order to reduce the complexity of the calculations and for faster calculation with a minimum number of iterations, a modified CORDIC based on the QRD-RLS algorithm for the purpose of beamforming is proposed in this paper and named mixed scaling rotation coordinate rotation digital computer (MSR-CORDIC). In this work, beamforming and direction of arrival (DOA) estimation will be achieved using the MSR-CORDIC and MUSIC algorithms respectively. The proposed algorithm is developed using Verilog HDL and implemented using the Xilinx field-programmable gate array (FPGA). In all cases, the proposed algorithm shows remarkable improvement compared with the conventional SCC (space code correlator) beamforming algorithm.

A CORDIC based Configurable Fixed-Point Design on FPGA using Minimal Hardware

Objectives: To design a COordinate Rotation DIgital Computer (CORDIC) based electrical signal processing system for efficient and minimalist electrical power processing. Methods: This stage of assessment describes the design and performance of a true RMS (Root-Mean Square) voltage meter on Xilinx SPARTAN 3E 1600 FPGA. Findings: The effectiveness of the proposed designs is assessed through FPGA implementations and error simulations. Measurement results show that the model can reproduce behaviors similar to the original model traditional use of multipliers, but with less resource consumption (hardware and processing time). Novelty: The use of CORDIC to reduce the computational cost of the algorithm, and its implementation in an embedded system.

Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design

In this paper, we have proposed an efficient method for integrating longer pipeline coprocessors with SPARCv8 compliant processor implementations that requires minimum changes in the existing processor pipeline. The proposed integration method is independent of the length of the coprocessor pipeline. We have used COordinate Rotation DIgital Computer (CORDIC) core as the coprocessor that has been integrated with SPARCv8 based LEON3 processor. Only a subset of the coprocessor instructions defined in the Instruction Set Architecture (ISA) are required in our proposed method. The required synchronisation of data and control signals between the coprocessor and LEON3 pipeline has been presented in detail. The performance of the resulting closely-coupled design is compared with bus-based integration in terms of speed, power and area in the System-on-Chip (SoC) design, and both FPGA and ASIC results are reported. Our proposed integration method shows significant improvements over bus-based method for applications that require consecutive coprocessor operations in terms of CPI metric along with substantial reduction in number of cycles. Similar strategy can be employed for integration with coprocessors having different pipeline lengths.

Development of a multi frequency impedance measurement system for use in MEMS flow cytometers

A novel MEMS based system for flow cytometry is presented based on a multispectral approach. The solution provides the ability to concurrently generate, detect and analyse the response from a biological cell using multiple narrow band signals with a frequency separation sufficient to evoke different cellular responses. The narrow band approach limits the energy required and provides an improved signal to noise ratio for a given transmitter energy, avoiding wide band signal power dissipation and dilution issues. It requires only a single transmitter and receiver interface to the MEMS device with no duplication of analogue signal paths. The design has the ability to generate a complex multi frequency waveform with a wide frequency separation. A digital approach based on the CORDIC algorithm (Volder, IRE Trans Electron Comput EC-8:330–334, 1959) was used to generate the required sinusoidal waveforms. The digital section of the design was implemented on an FPGA. It utilised a modified digital phase sensitive amplifier to provide enhanced signal to noise performance and harmonic rejection. A novel hybrid, cross channel electrode structure to implement the stimulus and response analysis sub-system has been designed. A fully functional macroscopic test bench has been constructed to demonstrate the viability of the approach. Both physical measurements and finite element data has been used to demonstrate the potential for migration into a MEMS based system.

Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm

CORDIC algorithm is suitable to implement sine/cosine function, but the large number of iterations lead to great delay and overhead. Moreover, due to finite bit-width of operands and number of iterations, the relative error of floating-point sine or cosine is terrible when the input angle is close to 0 or $\pi /2$ , respectively. To overcome these shortcomings, TCORDIC algorithm, which combines low latency CORDIC and Taylor algorithm, is presented. After analyzing the latency of traditional CORDIC, low latency CORDIC is proposed, which adopts the technique of sign prediction, compressive iterations, and parallel iterations. Besides, the calculating boundary ( $N$ ), which is used for determining whether Taylor algorithm is selected or not in TCORDIC algorithm, is evaluated to achieve a trade-off between area and delay. Truncated multipliers are used to reduce the area further. Finally, Using TCORDIC algorithm, pipelined and iterative structures are implemented for IEEE-754 double precision floating-point sine/cosine with the input $Z\epsilon [0,\pi /2]$ . Under typical condition (1V, 25 °C), our designs are synthesized with 40 nm standard cell library. For a pipelined structure, the frequency is up to 1.70 GHz and area $194049.64~\mu {\mathrm { m}}^{2}$ . Frequency decreases to 1.45 GHz for iterative structure, but the area requires only $110590.81~\mu {\mathrm { m}}^{2}$ . TCORDIC is efficient in controlling relative error, and achieves the accuracy within one ulp (unit in the last place) for floating-point sine/cosine function.

Field Programmable Gate Array (FPGA) Respiratory Monitoring System Using a Flow Microsensor and an Accelerometer

Abstract This paper describes a non-invasive system for respiratory monitoring using a Micro Electro Mechanical Systems (MEMS) flow sensor and an IMU (Inertial Measurement Unit) accelerometer. The designed system is intended to be wearable and used in a hospital or at home to assist people with respiratory disorders. To ensure the accuracy of our system, we proposed a calibration method based on ANN (Artificial Neural Network) to compensate the temperature drift of the silicon flow sensor. The sigmoid activation functions used in the ANN model were computed with the CORDIC (COordinate Rotation DIgital Computer) algorithm. This algorithm was also used to estimate the tilt angle in body position. The design was implemented on reconfigurable platform FPGA.

Implementation of wideband digital transmitting beamformer based on LFM waveforms

A wideband digital transmitting beamformer based on linear frequency modulation (LFM) signals is presented in this study. The wideband beamformer is realised as a combination of direct digital synthesisers and fractional delay (FD) filters in polyphase structure. By using coordinate rotation digital computer algorithm, high intermediate frequency wideband LFM signal is generated and phase compensation for beamforming is accomplished in field programmable gate array. The impact of different number of quantisation bits on signal generation is analysed. The results of waveform generation and FD filter design are given. At last, the transmitting beam pattern is simulated.

Implementation of GFSK Digital Receiver Based on CORDIC Algorithm

GFSK modulation is an wireless communication standard for the purpose of Automatic Meter Reading (AMR) in smart grid. This paper presents the implementation of GFSK digital receiver based on CORDIC algorithm. The receiver is made up of the frequency offset estimation, frequency compensation, bit synchronization and demodulation modules. The digital receiver is equipped with two identical baseband signal processing branches, in which a large carrier frequency offset can be accommodated.

Low-power DCT-based compressor for wireless capsule endoscopy

Discrete Cosine Transform (DCT) is known as one of the most significant, fundamental, and prevailing transforms in data compression, watermarking, and medical digital image processing applications for secure storing, sending, and transmitting in cyberspace. This paper addresses a low power, area efficient, and low complexity structure of COordinate Rotation Digital Computer (CORDIC)-based DCT for applying to the Wireless Capsule Endoscopy (WCE) application. In this work, a novel structure is developed called low-power Lookahead (LPLA) CORDIC to overcome the problems of power supply restriction and small dimensions while maintaining the image quality in the WCE. The key idea in the proposed structure is that the successive computations of CORDIC algorithm are performed by utilizing the pipeline property of Lookahead (LA) CORDIC. This leads to employ a single common hardware for the two CORDIC outputs. Thus, the number of the adder and shifter blocks required for CORDIC computation decreases in the proposed structure. Moreover, we utilize pipelining, clock gating and data gating techniques which result in further reduction of power consumption. The simulation results by TSMC 0.13 μm technology at 1.2v power supply demonstrate that the proposed LPLA CORDIC-based DCT structure averagely consumes 64% of the power, 43% of the area, and 8% of the power-delay-product (PDP) of the most efficient structures reported in the literature. Furthermore, by applying the proposed method to JPEG compression standard, it is shown that the reconstructed images of the proposed structure have favorable quality and compression ratio, in addition to achieving lower power consumption and area overhead. According to the aforementioned features, the proposed LPLA CORDIC-based DCT structure is suitable for utilizing in the compressor part of wireless endoscopy capsule and other low-power and high-quality systems which are battery-based.

Real-Time and High-Accuracy Arctangent Computation Using CORDIC and Fast Magnitude Estimation

This paper presents an improved VLSI (Very Large Scale of Integration) architecture for real-time and high-accuracy computation of trigonometric functions with fixed-point arithmetic, particularly arctangent using CORDIC (Coordinate Rotation Digital Computer) and fast magnitude estimation. The standard CORDIC implementation suffers of a loss of accuracy when the magnitude of the input vector becomes small. Using a fast magnitude estimator before running the standard algorithm, a pre-processing magnification is implemented, shifting the input coordinates by a proper factor. The entire architecture does not use a multiplier, it uses only shift and add primitives as the original CORDIC, and it does not change the data path precision of the CORDIC core. A bit-true case study is presented showing a reduction of the maximum phase error from 414 LSB (angle error of 0.6355 rad) to 4 LSB (angle error of 0.0061 rad), with small overheads of complexity and speed. Implementation of the new architecture in 0.18 µm CMOS technology allows for real-time and low-power processing of CORDIC and arctangent, which are key functions in many embedded DSP systems. The proposed macrocell has been verified by integration in a system-on-chip, called SENSASIP (Sensor Application Specific Instruction-set Processor), for position sensor signal processing in automotive measurement applications.