Conventional Fault-tolerant Techniques Research Articles

Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs

FPGAs are the most prominent electronic devices used in space, military, and commercial applications. This is because of the reprogrammable feature in FPGAs. The electronic and computational components are sensitive to various types of events caused by ionisation effects. The problem at hand is effectively addressed by a fault-tolerant method known as Triple Modular Redundancy (TMR). Triple Modular Redundancy (TMR) has been demonstrated as an effective and dependable technique for mitigating the impacts of single-event upsets (SEUs) and single-event transients (SETs). However, to ensure effective mitigation of SETs, an additional delay element is required. However, the implementation of a TMR system may incur higher costs due to the requirement for additional hardware resources. Subsequently, numerous studies have focused on conventional fault-tolerant techniques with the aim of reducing the hardware overhead associated with TMR, although these efforts have not yielded satisfactory results. In order to tackle this issue more effectively, this paper introduces a novel error analysis approach. This approach works based on the error percentage algorithm and also proposes the other method, a preferential method for reducing the overhead of the hardware in existing fault-tolerant techniques. The proposed work is applied to the multiplier circuit to analyse its efficiency. The proposed work reduces the hardware resources by 48% when compared with the existing work.

Fault-tolerant neural network training framework based on client-server

In order to realize low power consumption and real-time inference, AIoT devices have been applied in many fields of deep learning in recent years. However, some manufacturing processes cause some soft errors on AIOT devices in inference. For a neural network accelerator with a large amount of computation, it may lead to a large amount of computing error and a huge loss of prediction accuracy, which is intolerable for precision-sensitive applications such as autonomous drones. However, conventional fault tolerance techniques such as triple modular redundancy can incur considerable power consumption and performance penalty. In this paper, a client-server collaborative fault-tolerant neural network training framework is proposed. In the training, an AIoT processor with soft errors is used as the client, and the server learns the on-site computing errors with the application data of AIoT processor. Several representative neural network models were selected in the experiment. Compared with the off-line training model, the model trained by this method increases the top5 accuracy of the neural network by an average of 2.8%.

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy

Embedded soft-core processors are becoming the usual solution to deal with network and data communications inside FPGAs. However, when developing space-based applications, the designer must consider the effects of ionizing radiation such as Total Ionizing Dose (TID) and Single-Event Effect (SEE). The majority of techniques for mitigation of Single-Event Upsets (SEUs) on FPGAs are based on hardware spatial-redundancy. This work presents a fault-tolerance technique, based on the concept of temporal redundancy, with checkpoints and recovery for soft-core processors. The proposed modified architecture is aimed at embedded systems for space applications based on FPGAs. Our experimental results show that the Checkpoint Recovery technique is a valid alternative to traditional spatial-redundancy, especially when considering limited logic area and power budget present on a satellite. The results present levels of reliability comparable to those of the more conventional fault-tolerance techniques. Additionally, the proposed approach does not require modifications of the software source code or compiler.

Approximate Error Detection With Stochastic Checkers

Designing reliable systems, while eschewing the high overheads of conventional fault tolerance techniques, is a critical challenge in the deeply scaled CMOS and post-CMOS era. To address this challenge, we leverage the intrinsic resilience of application domains such as multimedia, recognition, mining, search, and analytics where acceptable outputs are produced despite occasional approximate computations. We propose stochastic checkers (checkers designed using stochastic logic) as a new approach to performing error checking in an approximate manner at greatly reduced overheads. Stochastic checkers are inherently inaccurate and require long latencies for computation. To limit the loss in error coverage, as well as false positives (correct outputs flagged as erroneous), caused due to the approximate nature of stochastic checkers, we propose input permuted partial replicas of stochastic logic, which improves their accuracy with minimal increase in overheads. To address the challenge of long error detection latency, we propose progressive checking policies that provide an early decision based on a prefix of the checker’s output bitstream. This technique is further enhanced by employing progressively accurate binary-to-stochastic converters. Across a suite of error-resilient applications, we observe that stochastic checkers lead to greatly reduced overheads (29.5% area and 21.5% power, on average) compared with traditional fault tolerance techniques while maintaining high coverage and very low false positives.

Survey on Fault-Tolerant Techniques for Power Electronic Converters

With wide-spread application of power electronic converters in high power systems, there has been a growing interest in system reliability analysis and fault-tolerant capabilities. This paper presents a comprehensive review of conventional fault-tolerant techniques regarding power electronic converters in case of power semiconductor device failures. These techniques can be classified into four categories based on the type of hardware redundancy unit: switch-level, leg-level, module-level, and system-level. Also, various fault-tolerant methods are assessed according to cost, complexity, performance, etc. The intent of this review is to provide a detailed picture regarding the current landscape of research in power electronic fault-handling mechanisms.

Fault-tolerant routing mechanism based on network coding in wireless mesh networks

As an essential part of next generation Internet, Wireless Mesh Networks (WMNs) have attracted much research attention due to their potential advantages, including low up-front cost, ease of deployment, enhanced capacity and service coverage. However, the inherit features of wireless channels (e.g., interference, noise, fading and limited bandwidth) have put forward a severe challenge for network reliability. Conventional fault-tolerant techniques either waste too many bandwidth resources or postpone the recovery speed. This paper proposes a random linear network coding based fault-tolerant routing mechanism to instantaneously recover the native packets omitted by the source. This mechanism couples the multi-path routing and random linear network coding technique by improving the conventional method of coding nodes selection. Simulation results demonstrate that our proposed fault-tolerant routing mechanism, which includes Random linear Network Coding in Multi-path with Source Coding (RNCM-SC) and Random linear Network Coding in Multi-path with Source Forwarding (RNCM-SF), perform better in terms of packet delivery ratio, resource redundancy degree, end-to-end delay and useful throughput ratio than the traditional method.

Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration

The construction of computer systems containing integrated circuit logic components with very large scale integration (VLSI), that is, many thousands of gates, is inevitable. Such levels of integration have already been achieved in memory components. There are significant problems in using some conventional fault-tolerant techniques in VLSI implementations for general purpose computers; consequently, modified approaches must be investigated.