Conventional Digital Computers Research Articles

Analog–digital hybrid computing with SnS2 memtransistor for low-powered sensor fusion

Algorithms for intelligent drone flights based on sensor fusion are usually implemented using conventional digital computing platforms. However, alternative energy-efficient computing platforms are required for robust flight control in a variety of environments to reduce the burden on both the battery and computing power. In this study, we demonstrated an analog–digital hybrid computing platform based on SnS2 memtransistors for low-power sensor fusion in drones. The analog Kalman filter circuit with memtransistors facilitates noise removal to accurately estimate the rotation of the drone by combining sensing data from the gyroscope and accelerometer. We experimentally verified that the power consumption of our hybrid computing-based Kalman filter is only 1/4th of that of the traditional software-based Kalman filter.

Period finding and prime factorization using classical wave superposition

Prime factorization is a procedure of determining the prime factors of a given number N that requires super-polynomial time for conventional digital computers. Peter Shor developed a polynomial-time algorithm for quantum computers. Period finding is the key part of the algorithm, which is accomplished with the help of quantum superposition of states and quantum entanglement. The period finding can be also accomplished using classical wave superposition. In this study, we present experimental data obtained on a multi-port spin wave interferometer made of Y3Fe2(FeO4)3. Number 817 was factorized by a sequence of phase measurements. We also present the results of numerical modeling on the prime factorization of larger numbers 334597,1172693,3377663,and9363239. The results of numerical modeling reveal significant shortcomings of the period-based approach. The major problems are associated with an inability to predict the period of the modular function, significant overhead over classical digital computers in some cases, and phase accuracy requirements. We argue that the same problems are inherent in classical analog and quantum computers.

Prime factorization using coupled oscillators with positive feedback

Prime factorization is a procedure of determining the prime factors of a given number N that requires super-polynomial time for conventional digital computers. In this work, we describe an approach to prime factorization using coupled oscillators with positive feedback. The approach includes several steps, where some of the steps are accomplished on a general type computer, and some steps are accomplished using coupled oscillators. We present experimental data on finding the primes of N = 817. The experiment is performed on a system of two coupled active ring oscillators. Each of the oscillators possesses its own set of eigenfrequencies that can be independently controlled by the external phase shifter. The coupling allows us to check on any common frequency that leads to the phase lock-in and power increase in the circuit. One of the ring oscillators includes a spin wave magnetic delay line made of Y3Fe2(FeO4)3, while the second oscillator includes an ordinary coaxial cable as a delay line. There are 22 eigenfrequencies for the spin wave oscillator and 4 eigenfrequencies for the oscillator with coaxial cable in the frequency band of operation. It takes less than 10 μs for the system to find the common frequency (if any). The most appealing property of the proposed circuit is that the processing time does not scale with the number of eigenfrequencies. Potentially, circuits with coupled active ring oscillators can be utilized to solve a variety of computational problems.

A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory

Quantum computing is regarded as the future of computing that hopefully provides exponentially large processing power compared to the conventional digital computing. However, current quantum computers do not have the capability to correct errors caused by environmental noise, so that it is difficult to run useful algorithms that require deep quantum circuits. Therefore, emulation of quantum circuits in digital computers is essential. However, emulation of large quantum circuits requires enormous amount of computations, and leads to a very large processing time. To reduce the processing time, we propose an FPGA emulator with high-bandwidth-memory to emulate quantum Fourier transform (QFT), which is a major part of many quantum algorithms. The proposed FPGA emulator is scalable in terms of both processing speed and the number of qubits, and extendable to multiple FPGAs. We performed QFT emulations up to 30 qubits using two FPGAs. According to the measured results, we have achieved 23.6 ~ 24.5 times speed-up compared to a fully optimized 24-core CPU emulator.

In-Memory Realization of Eligibility Traces Based on Conductance Drift of Phase Change Memory for Energy-Efficient Reinforcement Learning.

Reinforcement learning (RL) has shown outstanding performance in handling complex tasks in recent years. Eligibility trace (ET), a fundamental and important mechanism in reinforcement learning, records critical states with attenuation and guides the update of policy, which plays a crucial role in accelerating the convergence of RL training. However, ET implementation on conventional digital computing hardware is energy hungry and restricted by the memory wall due to massive calculation of exponential decay functions. Here, in-memory realization of ET for energy-efficient reinforcement learning with outstanding performance in discrete- and continuous-state RL tasks is demonstrated. For the first time, the inherent conductance drift of phase change memory is exploited as physical decay function to realize in-memory eligibility trace, demonstrating excellent performance during RL training in various tasks. The spontaneous in-memory decay computing and storage of policy in the same phase change memory give rise to significantly enhanced energy efficiency compared with traditional graphics processing unit platforms. This work therefore provides a holistic energy and hardware efficient method for both training and inference of reinforcement learning.

Deep Learning's Diminishing Returns: The Cost of Improvement is Becoming Unsustainable

Deep learning is now being used to translate between languages, predict how proteins fold, analyze medical scans, and play games as complex as Go, to name just a few applications of a technique that is now becoming pervasive. Success in those and other realms has brought this machine-learning technique from obscurity in the early 2000s to dominance today. • Although deep learning's rise to fame is relatively recent, its origins are not. In 1958, back when mainframe computers filled rooms and ran on vacuum tubes, knowledge of the interconnections between neurons in the brain inspired Frank Rosenblatt at Cornell to design the first artificial neural network, which he presciently described as a “pattern-recognizing device.” But Rosenblatt's ambitions outpaced the capabilities of his era—and he knew it. Even his inaugural paper was forced to acknowledge the voracious appetite of neural networks for computational power, bemoaning that “as the number of connections in the network increases…the burden on a conventional digital computer soon becomes excessive.” • Fortunately for such artificial neural networks—later rechristened “deep learning” when they included extra layers of neurons—decades of Moore's Law and other improvements in computer hardware yielded a roughly 10-million-fold increase in the number of computations that a computer could do in a second. So when researchers returned to deep learning in the late 2000s, they wielded tools equal to the challenge.

Memristive Crossbar Arrays for Storage and Computing Applications

The emergence of memristors with potential applications in data storage and artificial intelligence has attracted wide attentions. Memristors are assembled in crossbar arrays with data bits encoded by the resistance of individual cells. Despite the proposed high density and excellent scalability, the sneak‐path current causing cross interference impedes their practical applications. Therefore, developing novel architectures to mitigate sneak‐path current and improve efficiency, reliability, and stability may benefit next‐generation storage‐class memory (SCM). Moreover, conventional digital computers face the von‐Neumann bottleneck and the slowdown of transistors’ scaling, imposing a big challenge to hardware artificial intelligence. Memristive crossbar features colocation of memory and processing units, as well as superior scalability, making it a promising candidate for hardware accelerating machine learning and neuromorphic computing. Herein, first, crossbar architecture is introduced. Then, for storage, the origin of sneak‐path current is reviewed and techniques to mitigate this issue from the angle of materials and circuits are discussed. Computing wise, the applications of memristive crossbars in both machine learning and neuromorphic computing are surveyed, focusing on the structure of unit cells, the network topology, and the learning types. Finally, a perspective on future engineering and applications of memristive crossbars is discussed.

Photonic computing to accelerate data processing in wireless communications.

Massive multiple-input multiple-output (MIMO) systems are considered as one of the leading technologies employed in the next generations of wireless communication networks (5G), which promise to provide higher spectral efficiency, lower latency, and more reliability. Due to the massive number of devices served by the base stations (BS) equipped with large antenna arrays, massive-MIMO systems need to perform high-dimensional signal processing in a considerably short amount of time. The computational complexity of such data processing, while satisfying the energy and latency requirements, is beyond the capabilities of the conventional widely-used digital electronics-based computing, i.e., Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). In this paper, the speed and lossless propagation of light is exploited to introduce a photonic computing approach that addresses the high computational complexity required by massive-MIMO systems. The proposed computing approach is based on photonic implementation of multiply and accumulate (MAC) operation achieved by broadcast-and-weight (B&W) architecture. The B&W protocol is limited to real and positive values to perform MAC operations. In this work, preprocessing steps are developed to enable the proposed photonic computing architecture to accept any arbitrary values as the input. This is a requirement for wireless communication systems that typically deal with complex values. Numerical analysis shows that the performance of the wireless communication system is not degraded by the proposed photonic computing architecture, while it provides significant improvements in time and energy efficiency for massive-MIMO systems as compared to the most powerful Graphics Processing Units (GPUs).

Ising formulations of some graph-theoretic problems in psychological research: Models and methods

It has been established in the fields of computer science and physics that many NP-hard and NP-complete graph-theoretic problems can be formulated and solved as Ising spin models. We discuss several problems that have a history in mathematical psychology, most notably max-cut clustering, graph coloring, a linear ordering problem related to paired comparison ranking and directed acyclic graphs, and the problem of finding a minimum subset of points necessary to contain another point within a convex hull. New Ising spin models are presented for the latter two problems. Additionally, we provide MATLAB software programs for obtaining solutions via enumeration of all spin ensembles (when computationally feasible) and simulated annealing. We are not claiming that the Ising spin model should be the preferred approach for formulating and solving graph-theoretic problems on conventional digital computers but it does provide a unifying framework for these problems, which may lead to future computational improvements. Recent progress in the development of quantum computing architecture has shown that Ising spin models can afford enormous improvements in algorithm efficiency when implemented on these platforms, potentially leading to widespread use of the methodology in the future.

A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme

Reversible logic has been emerging as a replacement for conventional digital computers and has been found to be a promising technology for the future that can improve the quality of circuits in terms of power, speed, heat dissipation, life span, and input traceability. The new generation of quantum processors demands the efficient implementation of decimal data path elements in many commercial, financial, and Internet-based applications. Reversible binary-coded decimal multipliers are among the important circuits in quantum computers. In this approach, we propose a low-power reversible radix binary-coded decimal multiplier. The proposed methodology uses a novel 4221 reversible recorder gate to select precomputed constant multiples and binary to excess-six conversion reversible decimal adder for partial product compression. The proposed multiplier is designed with 180-nm application-specific integrated circuit technology using the Cadence EDA tool and is compared with state-of-the-art BCD algorithms designed using reversible gates. Experimental evaluations revealed that the proposed design demonstrates power and power-delay product reductions of 28% and 37%, respectively, compared to those of the best BCD algorithms implemented in reversible logic.

Hybrid digital-analog simulation of many-body dynamics with superconducting qubits

In recent years, there has been a significant progress in the development of digital quantum processors. The state-of-the-art quantum devices are imperfect, and fully-algorithmic fault-tolerant quantum computing is a matter of future. Until technology develops to the state with practical error correction, computational approaches other than the standard digital one can be used to avoid execution of the most noisy quantum operations. We demonstrate how a hybrid digital-analog approach allows simulating dynamics of a transverse-field Ising model without standard two-qubit gates, which are currently one of the most problematic building blocks of quantum circuits. We use qubit-qubit crosstalks (couplings) of IBM superconducting quantum processors to simulate Trotterized dynamics of spin clusters and then we compare the obtained results with the results of conventional digital computation based on two-qubit gates from the universal set. The comparison shows that digital-analog approach significantly outperforms standard digital approach for this simulation problem, despite of the fact that crosstalks in IBM quantum processors are small. We argue that the efficiency of digital-analog quantum computing can be improved with the help of more specialized processors, so that they can be used to efficiently implement other quantum algorithms. This indicates the prospect of a digital-to-analog strategy for near-term noisy intermediate-scale quantum computers.

IGZO-based floating-gate synaptic transistors for neuromorphic computing

Neuromorphic computing, that is expected to be implemented with emerging synaptic devices, may overcome the inherent efficiency bottleneck in conventional digital computers. In this article, low-temperature processed indium-gallium-zinc-oxide (FGST) based floating-gate synaptic transistors with Al2O3/ITO/Al2O3 gate dielectric stacks are proposed for neuromorphic computing. The synaptic weight is stored as the channel conductance (G) of the floating-gate synaptic transistor (FGST). Negative/positive electrical pulse stimuli are applied on the bottom gate electrode of the synaptic transistor to facilitate/depress the synaptic weight, respectively. The operation mechanism of such neuromorphic devices is discussed based on the electron direct tunneling. Furthermore, the retention of the synaptic weight and the device endurance characteristics of the synaptic transistors are also investigated. In addition, in simulations with the measured device properties, an artificial neural network consisting of such floating-gate synaptic transistors shows a high classification accuracy of 95.7% for small digits dataset. These results may provide insight into potential applications of the floating-gate oxide-based synaptic transistors for artificial neural networks.

Experimental and computational analysis of thermal environment in the operation of HfO2 memristors

Neuromorphic computation using nanoscale adaptive oxide devices or memristors is a very promising alternative to the conventional digital computing framework. Oxides of transition metals, such as hafnium (HfOx), have been proven to be excellent candidate materials for these devices, because they show non-volatile memory and analog switching characteristics. This work presents a comprehensive study of the transport phenomena in HfOx based memristors and involves the development of a fully coupled electrothermal and mass transport model that is validated with electrical and thermal metrology experiments. The fundamental transport mechanisms in HfOx devices were analyzed together with the local and temporal variation of voltage, current, and temperature. The effect of thermal conductivity of substrate materials on the filament temperature, voltage ramp rate, and set/reset characteristics was investigated. These analyses provide insight into the switching mechanisms of these oxides and allow for the prediction of the effect of device architecture on switching behavior.

3-D Synapse Array Architecture Based on Charge-Trap Flash Memory for Neuromorphic Application

In order to address a fundamental bottleneck of conventional digital computers, there is recently a tremendous upsurge of investigations on hardware-based neuromorphic systems. To emulate the functionalities of artificial neural networks, various synaptic devices and their 2-D cross-point array structures have been proposed. In our previous work, we proposed the 3-D synapse array architecture based on a charge-trap flash (CTF) memory. It has the advantages of high-density integration of 3-D stacking technology and excellent reliability characteristics of mature CTF device technology. This paper examines some issues of the 3-D synapse array architecture. Also, we propose an improved structure and programming method compared to the previous work. The synaptic characteristics of the proposed method are closely examined and validated through a technology computer-aided design (TCAD) device simulation and a system-level simulation for the pattern recognition task. The proposed technology will be the promising solution for high-performance and high-reliability of neuromorphic hardware systems.

Design of a precise subdivision system for gratings using a modified CORDIC algorithm

The authors have proposed a robust linearisation method for determining the angles of sinusoidal signals generated by gratings. This scheme solves the problem of non-linear subdivision by compensating sinusoidal signal. The conventional coordinate rotation digital computer (CORDIC) algorithm is optimised by double-rotation iteration, and the calculation accuracy of arcsine and arccosine functions is improved. A pipeline preprocessing circuit based on the CORDIC is designed for the signal compensation and digital subdivision. The two processes are implemented on a field-programmable gate array chip, which exhibits a wide input range and good dynamic response. A theoretical analysis using stable signals from a function generator verifies that the subdivision system achieves the ideal subdivision effect. The subdivision system is further applied to an angle-measuring device for a 16,384-line circular grating. The results of subdivision exhibit good linearity for the grating moire signal. Compared to the angular measurement by a laser interferometer within the three grating lines, the angle-measurement accuracy of ±0.000138° (0.5″) and the relative error is ±0.63% over a travel angle of three grating lines. Notably, the measurement error of the subdivision system is only half of that in a similar commercial product (MicroE system).

A poor man\u2019s coherent Ising machine based on opto-electronic feedback systems for solving optimization problems

Coherent Ising machines (CIMs) constitute a promising approach to solve computationally hard optimization problems by mapping them to ground state searches of the Ising model and implementing them with optical artificial spin-networks. However, while CIMs promise speed-ups over conventional digital computers, they are still challenging to build and operate. Here, we propose and test a concept for a fully programmable CIM, which is based on opto-electronic oscillators subjected to self-feedback. Contrary to current CIM designs, the artificial spins are generated in a feedback induced bifurcation and encoded in the intensity of coherent states. This removes the necessity for nonlinear optical processes or large external cavities and offers significant advantages regarding stability, size and cost. We demonstrate a compact setup for solving MAXCUT optimization problems on regular and frustrated graphs with 100 spins and can report similar or better performance compared to CIMs based on degenerate optical parametric oscillators.

Memristor‐Based Efficient In‐Memory Logic for Cryptologic and Arithmetic Applications

AbstractAs the era of big data dawns, conventional digital computers face increasing difficulties in performance and power efficiency due to their von Neumann architecture, leading to an urgent requirement for computing paradigms that can merge logic and memory. An efficient in‐memory logic approach based on unipolar memristors that is capable of implementing all 16 Boolean logic functions in the same cell in less than 3 logic steps using a thermochemical metallization cell, where the confinement of filament diameter and thus switching location have reduced the threshold voltages and improved the switching uniformity, is experimentally demonstrated. The high efficiency of the logic units allows for the construction of novel encryption hardware in which both the encryption and decryption processes are achieved by memristor logic while the encryption key is also generated from the intrinsic stochasticity of resistive switching. The memristive array is also used to implement the calculation of Hamming distance and 1‐bit binary full adder with high efficiency, thus paving a way for future non‐von Neumann computing architectures.

(Invited) Emerging Neuromorphic Devices for Carbon Nanotubes and Related Low-Dimensional Materials

The exponentially improving performance of conventional digital computers has slowed in recent years due to the speed and power consumption issues that are largely attributable to the von Neumann bottleneck (i.e., the need to transfer data between spatially separate processor and memory blocks). In contrast, neuromorphic (i.e., brain-like) computing aims to circumvent the limitations of von Neumann architectures by spatially co-locating processor and memory blocks or even combining logic and data storage functions within the same device. In addition to reducing power consumption in conventional computing, neuromorphic devices also provide efficient architectures for emerging applications such as image recognition, machine learning, and artificial intelligence. With this motivation in mind, this talk will explore the opportunities for carbon nanotubes and related low-dimensional materials in neuromorphic devices. For example, by combining p-type semiconducting carbon nanotubes with n-type two-dimensional transition metal dichalcogenides, gate-tunable diodes have been realized, which show anti-ambipolar transfer characteristics that are suitable for artificial neurons, competitive learning, and spiking circuits [1]. In addition, by exploiting field-driven defect motion mediated by grain boundaries in monolayer MoS2, gate-tunable memristive phenomena have been achieved, which enable hybrid memristor/transistor devices (i.e., "memtransistors") that concurrently provide logic and data storage functions [2]. The planar geometry of memtransistors further allows multiple contacts to the channel region that mimic the behavior of biological neurons such as heterosynaptic responses [3]. Overall, this work introduces new foundational circuit elements for neuromorphic computing in addition to providing alternative pathways for studying and utilizing the unique charge transport characteristics of low-dimensional materials [4]. [1] V. K. Sangwan, et al., Nano Letters, 18, 1421 (2018). [2] V. K. Sangwan, et al., Nature Nanotechnology, 10, 403 (2015). [3] V. K. Sangwan, et al., Nature, 554, 500 (2018). [4] D. Jariwala, et al., Nature Materials, 16, 170 (2017).

Design of Cascaded CORDIC Based on Precise Analysis of Critical Path

A conventional coordinate rotation digital computer (CORDIC) has a low throughput rate due to its recursive implementation of micro-rotations. On the contrary, a fully-pipelined cascaded CORDIC provides a very high throughput rate at the cost of high complexity and large area. In this paper, possible design choices of cascaded CORDIC are explored over a wide range of operating frequencies, throughput rates, latency, and area complexity. For this purpose, we present a fine-grained critical path analysis of the cascaded CORDIC in terms of bit-level delay. Based on the propagation delay estimate, we propose an algorithm for determining the required number of pipeline stages and locations of the pipeline registers in order to meet the time constraint in a particular application. A hybrid cascaded-recursive CORDIC is also proposed to increase the throughput rate, and to reduce the latency and energy per sample (EPS). From synthesis results, we show that the proposed pipelined cascaded CORDIC with only four pipeline stages requires 31.1% less area and 29.0% less EPS compared to a fully-pipelined CORDIC. An eight stage pipelined recursive cascaded CORDIC provides 18.3% less EPS and 40.4% less area-delay product than a conventional CORDIC.

Memristive Devices and Networks for Brain‐Inspired Computing

As the era of big data approaches, conventional digital computers face increasing difficulties in performance and power efficiency due to their von Neumann architecture. As a result, there is recently a tremendous upsurge of investigations on brain‐inspired neuromorphic hardware with high parallelism and improved efficiency. Memristors are considered as promising building blocks for the realization of artificial synapses and neurons and can therefore be utilized to construct hardware neural networks. Here, a review is provided on existing approaches for the implementation of artificial synapses and neurons based on memristive devices; and the respective advantages and disadvantages of these approaches are evaluated. This is followed by a discussion of hardware accelerators and neuromorphic computing systems that exploit the parallel, in‐memory and analog characteristics of memristive crossbar arrays as well as the intrinsic dynamics of memristors. Finally, the outstanding challenges are addressed that have not yet been resolved in the present studies, and future advances are discussed that might be needed for building intelligent and energy efficient neuromorphic systems.