Multi-chip parallel power modules are highly favored in applications requiring high capacity and high switching frequency. However, the dynamic current imbalance between parallel chips caused by asymmetric layouts limits the available capacity. This paper presents a method to optimize dynamic current distribution by adjusting the lengths and connection points of bond wires. For the first time, a response surface model and nonlinear constraint optimization algorithm are introduced, along with parameter analysis based on finite element methods, to establish the response surface models for the parasitic inductance of bond wires and DBC (direct bonded copper). By leveraging the optimization goals for parasitic inductance and the analytical expressions of all response surfaces, the dynamic current sharing issue was transformed into a nonlinear constrained optimization problem. The solution to this optimization problem identified the optimal connection points for the bond wires, enhancing dynamic current sharing performance. Simulations and experiments were conducted, revealing that the optimized automotive-grade module exhibited a significant reduction in current differences between parallel branches, from 41.7% to 5.03% compared with the original design. This indicated that the proposed optimization scheme for adjusting bond wire connection points could significantly mitigate current disparities, thereby markedly improving current distribution uniformity.
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