Inner Product Computation Research Articles

An Efficient Distributed Arithmetic-Based Realization of the Decision Feedback Equalizer

A distributed arithmetic (DA)-based decision feedback equalizer architecture for IEEE 802.11b PHY scenarios is presented. As the transmission data rate increases, the hardware complexity of the decision feedback equalizer increases due to requirement for large number of taps in feed forward and feedback filters. DA, an efficient technique that uses memories for the computation of inner product of two vectors, has been used since DA-based realization of filters can lead to great computational savings. For higher-order filters, the memory-size requirement in DA would be high, and so ROM decomposition has been employed. The speed is further increased by employing digit-serial input operation. Two architectures have been presented, namely the direct-memory architecture and reduced-memory architecture where the later is derived using the former. A third architecture has also been presented where the offset-binary coding scheme is employed along with the ROM decomposition and digit-serial variants of DA. Synthesis results on Altera Cyclone III EP3C55F484C6 FPGA show that the proposed DA-based implementations are free of hardware multipliers and use less number of hardware resources compared to the multiply-and-accumulate-based implementation.

The generation of arbitrary order, non-classical, Gauss-type quadrature for transport applications

A method is presented, based upon the Stieltjes method (1884), for the determination of non-classical Gauss-type quadrature rules, and the associated sets of abscissae and weights. The method is then used to generate a number of quadrature sets, to arbitrary order, which are primarily aimed at deterministic transport calculations. The quadrature rules and sets detailed include arbitrary order reproductions of those presented by Abu-Shumays in [4,8] (known as the QR sets, but labelled QRA here), in addition to a number of new rules and associated sets; these are generated in a similar way, and we label them the QRS quadrature sets.The method presented here shifts the inherent difficulty (encountered by Abu-Shumays) associated with solving the non-linear moment equations, particular to the required quadrature rule, to one of the determination of non-classical weight functions and the subsequent calculation of various associated inner products. Once a quadrature rule has been written in a standard form, with an associated weight function having been identified, the calculation of the required inner products is achieved using specific variable transformations, in addition to the use of rapid, highly accurate quadrature suited to this purpose. The associated non-classical Gauss quadrature sets can then be determined, and this can be done to any order very rapidly. In this paper, instead of listing weights and abscissae for the different quadrature sets detailed (of which there are a number), the MATLAB code written to generate them is included as Appendix D.The accuracy and efficacy (in a transport setting) of the quadrature sets presented is not tested in this paper (although the accuracy of the QRA quadrature sets has been studied in [12,13]), but comparisons to tabulated results listed in [8] are made. When comparisons are made with one of the azimuthal QRA sets detailed in [8], the inherent difficulty in the method of generation, used there, becomes apparent, with the highest order tabulated sets showing unexpected anomalies.Although not in an actual transport setting, the accuracy of the sets presented here is assessed to some extent, by using them to approximate integrals (over an octant of the unit sphere) of various high order spherical harmonics. When this is done, errors in the tabulated QRA sets present themselves at the highest tabulated orders, whilst combinations of the new QRS quadrature sets offer some improvements in accuracy over the original QRA sets.Finally, in order to offer a quick, visual understanding of the various quadrature sets presented, when combined to give product sets for the purposes of integrating functions confined to the surface of a sphere, three-dimensional representations of points located on an octant of the unit sphere (as in [8,12]) are shown.

On the geometry of stabilizer states

Large-scale quantum computation is likely to require massive quantum error correction (QEC). QEC codes and circuits are described via the stabilizer formalism, which represents stabilizer states by keeping track of the operators that preserve them. Such states are obtained by stabilizer circuits (consisting of CNOT, Hadamard and Phase gates) and can be represented compactly on conventional computers using Θ(n2) bits, where n is the number of qubits [18]. As an additional application, the work in [1, 2] suggests the use of superpositions of stabilizer states to represent arbitrary quantum states. To aid in such applications and improve our understanding of stabilizer states, we characterize and count nearest-neighbor stabilizer states, quantify the distribution of angles between pairs of stabilizer states, study succinct stabilizer superpositions and stabilizer bivectors, explore the approximation of non-stabilizer states by single stabilizer states and short linear combinations of stabilizer states, develop an improved inner-product computation for stabilizer states via synthesis of compact canonical stabilizer circuits, propose an orthogonalization procedure for stabilizer states, and evaluate several of these algorithms empirically.

On the geometry of stabilizer states

Large-scale quantum computation is likely to require massive quantum error correction (QEC). QEC codes and circuits are described via the stabilizer formalism, which represents stabilizer states by keeping track of the operators that preserve them. Such states are obtained by {\em stabilizer circuits} (consisting of CNOT, Hadamard and Phase gates) and can be represented compactly on conventional computers using $\Theta (n^2)$ bits, where $n$ is the number of qubits \cite{Gottes98}. As an additional application, the work in~\cite{Aaron, AaronGottes} suggests the use of superpositions of stabilizer states to represent arbitrary quantum states. To aid in such applications and improve our understanding of stabilizer states, we characterize and count nearest-neighbor stabilizer states, quantify the distribution of angles between pairs of stabilizer states, study succinct stabilizer superpositions and stabilizer bivectors, explore the approximation of non-stabilizer states by single stabilizer states and short linear combinations of stabilizer states, develop an improved inner-product computation for stabilizer states via synthesis of compact canonical stabilizer circuits, propose an orthogonalization procedure for stabilizer states, and evaluate several of these algorithms empirically.

An Auditory Model of Improved Adaptive ZCPA

An improved ZCAP auditory model with adaptability is proposed in this paper, and the adaptive method designed for ZCPA model is suitable for other auditory model with inner-hair-cell sub-model. The first step in the implement process of the proposed ZCPA model is to carry out the calculation of inner product between signal and complex Gammatone filters to obtain important frequency components of signal. And then, according to the result of the first step, the parameters of the basilar membrane sub-model and frequency box are automatically adjusted, such as the number of the basilar membrane filters, center frequency and bandwith of each basilar membrane filter, position of each frequency box, and so on. Lastly an auditory model is built, and the final output is auditory spectrum.The results of numerical simulation and experiments have showed that the proposed model could realize accurate frequency selection, and the auditory spectrum is more distinctly than that of conventional ZCPA model. Moreover, the proposed model can completely avoided the influence of the number of filter on the shape of auditory spectrum existing in conventional ZCPA model so that the shape of auditory spectrum is steady, and the data quantity is small. DOI: http://dx.doi.org/10.11591/telkomnika.v11i12.3989

Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic

This brief presents a novel pipelined architecture for low-power, high-throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA). The throughput rate of the proposed design is significantly increased by parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations. The conventional adder-based shift accumulation for DA-based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce the sampling period and area complexity. Reduction of power consumption is achieved in the proposed design by using a fast bit clock for carry-save accumulation but a much slower clock for all other operations. It involves the same number of multiplexors, smaller LUT, and nearly half the number of adders compared to the existing DA-based design. From synthesis results, it is found that the proposed design consumes 13% less power and 29% less area-delay product (ADP) over our previous DA-based adaptive filter in average for filter lengths N = 16 and 32. Compared to the best of other existing designs, our proposed architecture provides 9.5 times less power and 4.6 times less ADP.

An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture

A unique word-serial inner-product processor architecture is proposed to capitalize on the high-speed serial-link bus. To eliminate the input buffers and deserializers, partial products are generated immediately from the serial input data and accumulated by an array of small binary counters operating in parallel to form a reduced partial product matrix directly. The height of the resultant partial product matrix is reduced logarithmically, and hence the carry-save-adder tree needed to complete the inner-product computation is smaller and faster. The small binary counters act as active on-chip buffers to mitigate the workload of the partial product accumulator. Their ability to accumulate partial product bits faster than combinatorial full adder leads to a simple two-stage architecture of high throughput and low latency. The architecture consumes 46% less silicon area, 24% less energy per inner-product computation and 70% less total interconnect length than its merged arithmetic counterpart in 65 nm CMOS process. In addition, the architecture requires only 4 metal layers out of available 7 layers for signal and power routing. By emulating the on-chip serial-link bus architecture on both designs, it is demonstrated that the proposed design is most suited for high-speed on-chip serial-link bus architecture.

Computations in quantum tensor networks

The computation of the ground state (i.e. the eigenvector related to the smallest eigenvalue) is an important task in the simulation of quantum many-body systems. As the dimension of the underlying vector space grows exponentially in the number of particles, one has to consider appropriate subsets promising both convenient approximation properties and efficient computations. The variational ansatz for this numerical approach leads to the minimization of the Rayleigh quotient. The Alternating Least Squares technique is then applied to break down the eigenvector computation to problems of appropriate size, which can be solved by classical methods. Efficient computations require fast computation of the matrix-vector product and of the inner product of two decomposed vectors. To this end, both appropriate representations of vectors and efficient contraction schemes are needed.Here approaches from many-body quantum physics for one-dimensional and two-dimensional systems (Matrix Product States and Projected Entangled Pair States) are treated mathematically in terms of tensors. We give the definition of these concepts, bring some results concerning uniqueness and numerical stability and show how computations can be executed efficiently within these concepts. Based on this overview we present some modifications and generalizations of these concepts and show that they still allow efficient computations such as applicable contraction schemes. In this context we consider the minimization of the Rayleigh quotient in terms of the parafac (CP) formalism, where we also allow different tensor partitions. This approach makes use of efficient contraction schemes for the calculation of inner products in a way that can easily be extended to the mps format but also to higher dimensional problems.

On the calculation of inner products of Schur functions

Two methods for calculating inner products of Schur functions in terms of outer products and plethysms are given and they are easy to implement on a machine. One of these is derived from a recent analysis of the SO(8) proton-neutron pairing model of atomic nuclei. The two methods allow for generation of inner products for the Schur functions of degree up to 20 and even beyond.

Stochastic Arithmetic Theory and Experiments

Stochastic arithmetic has been developed as a model for exact computing with imprecise data. Stochastic arithmetic provides confidence intervals for the numerical results and can be implemented in any existing numerical software by redefining types of the variables and overloading the operators on them. Here some properties of stochastic arithmetic are further investigated and applied to the computation of inner products and the solution to linear systems. Several numerical experiments are performed showing the efficiency of the proposed approach.

Efficient FPGA implementation of sharp FIR filters using the FRM technique

A high-performance field programmable gate array (FPGA) implementation of full pipelined computation structure is proposed for sharp finite-impulse -response (FIR) filters using the frequency response masking (FRM) technique. The FRM-based FIR (FFIR) filter consists of a novel symmetrical systolic array of a interpolated FIR(IFIR) filter in cascade to a pair of nonsymmetrical systolic arrays of masking FIR filters mainly. These filters are designed based on inner-product computation involving MAC operation which can be realized by the DSP block in the latest FPGA device efficiently. The realization results on a Xilinx Virtex-5 chip show that the proposed FPGA implementation can obtain higher throughput but consumes less resource compared to the equivalent conventional sharp FIR (CSFIR) filter that developed by the Core Generator software tool.

FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic

In this paper, we present the design optimization of one- and two-dimensional fully pipelined computing structures for area-delay-power-efficient implementation of finite-impulse-response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. The systolic decomposition scheme is found to offer a flexible choice of the address length of the lookup tables (LUT) for DA-based computation to decide on suitable area time tradeoff. It is observed that by using smaller address lengths for DA-based computing units, it is possible to reduce the memory size, but on the other hand that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density, and energy throughput are estimated for different filter orders and address lengths. Analysis of the results obtained indicate that performance metrics of the proposed implementation is broadly in line with theoretical expectations. It is found that the choice of address length yields the best of area-delay-power-efficient realizations of the FIR filter for various filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter.

Delta-function potential with a complex coupling

We explore the Hamiltonian operator H=-d^2/dx^2 + z \delta(x) where x is real, \delta(x) is the Dirac delta function, and z is an arbitrary complex coupling constant. For a purely imaginary z, H has a (real) spectral singularity at E=-z^2/4. For \Re(z)<0, H has an eigenvalue at E=-z^2/4. For the case that \Re(z)>0, H has a real, positive, continuous spectrum that is free from spectral singularities. For this latter case, we construct an associated biorthonormal system and use it to perform a perturbative calculation of a positive-definite inner product that renders H self-adjoint. This allows us to address the intriguing question of the nonlocal aspects of the equivalent Hermitian Hamiltonian for the system. In particular, we compute the energy expectation values for various Gaussian wave packets to show that the non-Hermiticity effect diminishes rapidly outside an effective interaction region.

Approximate Volumetric System Models for MicroSPECT

A microSPECT system has been developed for the purpose of studying murine models of amyloidosis in vivo. The system is equipped with two detector heads, each consisting of a multi-anode photomultiplier tube coupled to a pixellated NaI(Tl) crystal array. Images are reconstructed using an OS-EM algorithm. In this paper, we describe the associated volumetric system models that we have developed in support of both pinhole and parallel hole collimation. These models, which are precomputed and stored to disk prior to reconstruction, are based on simple inner-product computations and a region-growing like search defined by the conic view that each detector pixel has of the image voxels. We provide illustrative experimental results based on phantom and mouse data

Numerical solution of linear integro-differential equation by using sine–cosine wavelets

We use the continuous sine–cosine wavelets on the interval [0, 1] to solve the linear integro-differential equation. To do so, we construct the quadrature formulae for the calculation of inner products of any functions, which are required in the approximation for the integro-differential equation. Then, we reduced the integro-differential equation to the solution of linear algebraic equations.

Phase–frequency transfer model of analogue and mixed-signal front-end architectures for system-level design

A framework to model the behaviour of front-end architectures is presented. To make the model useful for systematic architectural exploration during front-end system design, a wide range of architectures are represented. Compared to other models, it emphasises the information flow throughout the architecture and also enables incremental modelling to represent the system at lower levels of abstraction. All signals in the architecture are represented as polyphase harmonic signals which are transformed by the building blocks of the architectures in the phase-frequency space. Their linear transformation behaviour is modelled by a multiplication of a polyphase harmonic transfer matrix with the input signal. It is shown that this representation for a polyphase mixer can be easily derived from the harmonic transfer matrices for the individual mixers. Extensions to weakly nonlinear behaviour are realised by adding distortion tensors to the model which take both intermodulation and harmonic distortion into account. The nonlinear mapping operation is represented by a repeated calculation of inner products of the distortion tensor and the input signal. As an example, the model has been applied to a downconversion architecture. It is shown that the non-ideal behaviour of the architecture is the result of parasitic transfers between phases and frequencies within the phase-frequency space. This allows a clear identification of the causes of performance degradation and gives suggestions to improve the performance.

Uncertainty Propagation for a Turbulent, Compressible Nozzle Flow Using Stochastic Methods

A fully spectral, polynomial chaos method for the propagation of uncertainty in numerical simulations of compressible, turbulent flow is described. The method is applied to the flow in a quasi-one-dimensional nozzle. Results demonstrate the ability of the method to propagate accurately the uncertainty throughout the entire numerical field. Comparison and validation were made with the reference Monte Carlo method. An exact method and an approximate method for the computation of inner products are also discussed in terms of efficiency and number of operations required

Solving linear integro-differential equation system by Galerkin methods with hybrid functions

In this paper, we use the hybrid Legendre and Block–Pulse functions on interval [0,1) to solve the linear integro-differential equation system, and construct the quadrature formulae for the calculation of inner products of any functions, which are required in the Galerkin methods for integro-differential equation system.

Numerical solution of linear Fredholm and volterra integral equation of the second kind by using Legendre wavelets

Uses the continuous Legendre wavelets on the interval [0,1) in the manner of M. Razzaghi and S. Yousefi, to solve the linear second kind integral equations. We use quadrature formula for the calculation of inner products of any functions, which are required in the approximation for the integral equations. Then, we reduced the integral equation to the solution of linear algebraic equations.

Parallel Architectures and Adaptation Algorithms for Programmable FIR Digital Filters with Fully Pipelined Data and Control Flows

Previous designs of programmable finite impulse response (FIR) digital filters have demonstrated that the use of broadcast input data and control can lead to a high performance-to-cost ratio. As the technology moves into deeper submicron regimes, this approach should be reexamined by paying greater attention to the effect of interconnects. In this paper, we quantify the contribution of interconnect delay to the cycle time and demonstrate its negative effects on both scalability and cost-effectiveness of such broadcast designs. We further show how speed and density improvements secured through technology scaling can be maintained by a fully pipelined design in which both data and control signals are restricted to local connections. One important feature of our design is that the data input port is reused for delivering the new coefficients. Consequently, coefficients can be loaded in bit-parallel form with no increase in the number of input pins, thereby facilitating and speeding up run-time adaptation to the application environment. Another feature is that variable-precision coefficients can be accommodated easily and flexibly, with no speed penalty. Because the inner-product computation at the heart of a FIR filter occurs in many other signal processing applications, our design methods and conclusions are widely applicable to the design of application-specific and embedded parallel architectures.