Compositional Microprogram Control Unit Research Articles

Twofold Addressing of Microinstructions in CMCU with Common Memory

Introduction. Control unit (CU) is one of the most important blocks of practically any digital system. Its characteristics largely determine the characteristics of a system as a whole. As a rule, to synthesize CUs, the models of Mealy and Moore finite state machines (FSMs) are used. The article is devoted to compositional microprogram control units (CMCUs). A CMCU is a Moore FSM in which a state register is replaced by a microinstruction address counter. The choice of CMCU is an optimal solution for implementing linear control algorithms. When developing FSM circuits, it is necessary to optimize such characteristics as the performance and hardware amount. The methods of optimization depend strongly on logic elements used. Nowadays, FPGA chips are one of the most common logic elements for implementing digital systems. To implement the CMCU circuit, it is enough to use look-up table (LUT) elements, programmable flip-flops, embedded memory blocks, and programmable interconnections. The purpose of the article. In the article, there is proposed a CMCU design method improving such characteristics of CU as the number of logic levels and regularity of programmable interconnections. The main drawback of LUT is a small number of inputs. Modern digital systems can generate signals of logical conditions entering the control unit, the number of which is tens of times greater than the number of LUT inputs. Such a discrepancy between the characteristics of the control algorithm and the number of inputs of the LUT elements leads to multi-level control circuits with an irregular structure of programmable interconnections, and is the reason for a decrease in performance and an increase in chip area and power consumption. Results. A method for double addressing of microinstructions in CMCU with shared memory is proposed. The method is an adaptation of the two-fold state assignment of Mealy FSMs, the circuits of which are implemented with FPGAs. The proposed method makes it possible to obtain a microinstruction addressing circuit with two logic levels and a regular interconnection system. The paper considers an example of the synthesis of the CMCU circuit and analyzes the proposed method. Conclusions. The proposed method allows reducing hardware amount (the number of LUTs and their interconnections), time of delay and power consumption. Moreover, the more complex the control algorithm, the greater the benefit the proposed method gives. Keywords: compositional microprogram control unit, microinstruction, LUT, EMB, synthesis.

HDL Implementation of a Compositional Microprogram Control Unit with e-DIA

HDL Implementation of a Compositional Microprogram Control Unit with e-DIA

EXTENSION OF MICROINSTRUCTION FORMAT FOR CONTROL UNIT IMPLEMENTATION ON HYBRID FPGA

A synthesis method of compositional microprogram control unit on hybrid FPGA (that contain table elements, and programmable logic arrays) is proposed. The main purpose of the method is hardware amount reduction in the control unit circuit. Usage of classes codes of pseudoequivalent operational linear chains for hardware amount reducing in the circuit and overall cost reducing of the control device is proposed. An example of the proposed synthesis method application is given. It is shown that depending on the basis circuit parameters and characteristics of the control algorithm hardware resource saving can reach 30 % in comparison to the costs of basic circuit control device implementation. Time characteristics of control units of modified and base structured are equivalent.

The Application and Adaptation of the Two Sources of Code and Natural Encoding Method for Designing a Model of Microprogram Control Unit with Base Structure

The article presents a modification to the method which applies two sources of data. The modification is depicted on the example of a compositional microprogram control unit (CMCU) model with base structure implemented in the complex programmable logic devices (CPLD). First, the conditions needed to apply the method are presented, followed by the results of its implementation in real hardware.

Reduction of hardware expenses in control unit with code sharing

A method for reducing hardware expenses in compositional microprogram control unit and CPLD chips is proposed. This method is based on the use of pseudoequivalent operational linear chains, wide fan-in of PAL macrocells, and existence of free outputs of embedded memory block in CPLD chips. An example of applying the method is given. It is shown that the method reduces hardware expenses to 30%.

Modification of the microcommand addressing system in a control unit with code sharing

This article proposes two modifications of the microcommand addressing system in a compositional microprogram control unit with code sharing. The modifications are based on using FSM pseudoequivalent states to reduce the number of rows in the FSM transition table and thereby to reduce the complexity of the combinational part of the device. Methods are proposed for synthesizing compositional control units with a modified microcommand addressing system. The research results are presented and appropriate fields of application of the methods proposed are considered.

Compositional Microprogram Control Unit with Operational Automaton of Transitions

The using of operational automaton of transitions as the block of microinstruction addressing of compositional microprogram control unit is proposed. The new structure model of compositional microprogram control unit with reduced hardware amount is developed. The generalized structure of operational automaton of transitions is suggested. An example of process of synthesis of compositional microprogram control unit with operational automaton of transitions is given.

REDUCTION OF TERM MATRIX OF CONTROL UNIT WITH CODE SHARING

The structures of compositional microprogram control unit with code sharing are proposed. Structures allow reducing the complexity of the matrix realization in the device’s circuit. The proposed method is based on using of node’s address representation as a concatenation of OLC codes and code of OLC components. The proposed method allow reducing the complexity of the matrix realization in the device’s circuit.

Code conversion in compositional microprogram control units

The joint use of structural decomposition and code conversion is proposed. The method is oriented to reducing the hardware in compositional microprogram control units. This reduction is due to the decrease in the number of arguments for irregular functions and in the number of the functions themseves. Embedded memory blocks are used to implement regular functions. Design methods and an example are discussed. Experimental results are given.

EXTENSION OF MICROINSTRUCTION FORMAT IN COMPOSITIONAL MICROPROGRAM CON TROL UNIT WITH ELEMENTARIZATION OF OPERATIONAL LINEAR CHAINS

The modification of synthesis method of compositional microprogram control units is directed to decrease of hardware amount in scheme of control unit in FPGA basis. Reduction of complexity of block of microinstruction addressing is reached due to of field with pseudoequivalent operational linear chain class code. Conditions of proposed method usage possibility are given. The example of method implementation is shown.

Optimization of circuits of compositional microprogram control units implemented on FPGA

Two methods are proposed for microinstruction addressing in interpreting a control algorithm by a compositional microprogram control unit (CMCU). The method of refined addressing allows one to uniquely identify outputs of operational linear chains (OLCs) using a minimal number of address bits. The method of optimal addressing makes it possible to represent classes of pseudoequivalent OLCs using a minimal number of generalized intervals of the code space. The proposed methods are illustrated by examples. Both methods make it possible to reduce the number of look-up table (LUT) elements in a CMCU logic circuit in comparison with its base structure. In the majority of cases, the clock period decreases with decreasing the amount of hardware

Reduction in the number of LUT elements for control units with code sharing

Reduction in the number of LUT elements for control units with code sharingTwo methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.

Analysis of Resource Utilization in Compositional Microprogram Control Unit with Elementary Operational Linear Chains

Abstract This paper presents results of decreasing hardware resources usage for compositional microprogram control units with code sharing and elementary operational linear chains. Two types of microprogram control units are compared: a structure with address converter and without it. For synthesis and implementation of the microprogram control unit Xilinx ISE 8.2i package was used. Four optimization strategies available in the ISE package have been applied. The test results show that for some examples memory consumption drops even by 50% in comparison to the implementation without the address converter. It's important to notice that adding an additional block (address converter) to the microprogram control unit does not cause an increase in hardware resource use.

Synthesis of Microprogram Control Unit with Control Microinstructions

A method that consider optimization of the amount of PAL macrocells in the circuit of compositional microprogram control unit is proposed. The method is based on the introduction of additional microinstructions codes of the classes of pseudoequivalent operator linear chains. The proposed method is based on usage of the natural redundancy of embedded memory blocks which are used to implement the control memory. An example of application of the proposed method is given.

Partial reconfiguration of compositional microprogram control units implemented on FPGAS

The method of partial reconfiguration of Compositional Microprogram Control Units implemented on FPGAs is proposed. The method is based on the swapping of the content of Control Memory while the rest of the system is not modified. Such approach permits to decrease the size of a bit-stream that is sent to the device. Therefore time needed for device configuration is shorter. Proposed solution is much more safe due to less errors that can occur during reconfiguration of FPGAs. An example of proposed method application is discussed. The researches conducted by authors have shown that proposed method permits to decrease the size of a bit-stream that is sent to the device in comparison with traditional method even up to 95%.

OPTIMIZATION OF LUT-ELEMENTS AMOUNT IN CONTROL UNIT OF SYSTEM-ON-CHIP

The method of decreasing of the amount of feedback signal in the compositional microprogram control unit is proposed. Main idea of the method is to use a part of microinstruction address for the code representation of operational linear chain. The proposed method does not require any new structural elements and has no influence on performance of digital system with compositional microprogram control unit. An example of proposed method application is given.

OPTIMIZATION OF CONTROL UNIT WITH CODE SHARING

The method of design of compositional microprogram control unit with code sharing is proposed. The proposed method is based on application of special address transformer to form an address of microinstruction on the base of its representation as pair <code of operational linear chain, code of component>. Such approach permits to use all positive features of code sharing independently on characteristics of interpreted flowchart of algorithm, the optimal encoding of pseudoequivalent operational linear chains in particular. The proposed method permits to decrease the size of control memory in comparison with all known methods of such control units design. An example of proposed method application is given.

DESIGN OF COMPOSITIONAL MICROPROGRAM CONTROL UNITS WITH ELEMENTARY OPERATIONAL LINEAR CHAINS

A method of designing of Compositional Microprogram Control Units with Elementary Operational Linear Chains is proposed. The method is based on the special encoding of the Operational Linear Chains. Such an approach permits to decrease the number of logic blocks of the destination FPGA device. An exemplary application of the proposed method is discussed. The investigations conducted by the author have shown that the proposed method permits to decrease the usage of the logic blocks of destination device up to 20%.