Composite Transistor Research Articles

A technique to improve the drive current of high-voltage I/O transistors in digital CMOS technologies

By combining a 0.12-μm-long 1.2-V thin-oxide transistor with a 0.22-μm-long 3.3-V thick-oxide transistor in a 0.13-μm CMOS process, a composite MOS transistor structure with a drawn gate length of 0.34 μm is realized. Measurements show that at V/sub GS/=1.2 V and V/sub DS/=3.3 V, the composite transistor has more than two times the drain current of the minimum channel length (0.34 μm) 3.3-V thick-oxide transistor, while having the same breakdown voltage (V/sub BK/) as the thick-oxide transistor. Exploiting these, it should be possible to implement 3.3-V I/O transistors with better combination of drive current, threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and breakdown voltage in conventional CMOS technologies without adding any process modifications.

Improved In0.45Al0.55As/In0.45Ga0.55As/In0.65Ga0.35As Inverse Composite Channel Metamorphic High Electron Mobility Transistor

A δ-doped In0.45Al0.55As/InGaAs metamorphic high-electron-mobility transistor (MHEMT) using an In0.45Ga0.55As/In0.65Ga0.35As inverse composite channel has been fabricated successfully and demonstrated. The inverse composite channel significantly reduces Coulomb scattering and consequently improves electron mobility as well as carrier confinement. Experimentally, a high extrinsic transconductance of 321 mS/mm and a drain–source saturation current density of 342 mA/mm are obtained for a 0.65 ×200 µm2 gate at 300 K. Meanwhile, degradation of the studied device, in terms of parameters such as Gm,max, IDSS, and Vth, with increasing temperature is not evident. A positive temperature coefficient of Vth is observed. The measured fT and fmax for a 0.65-µm-gate device are 41.6 and 53 GHz, respectively. In addition, the studied device also shows good microwave performances in a flat and wide operation region. From VGS = -2.5 to 0.5 V, the values of fT and fmax are still over 33 GHz.

A compact composite transistor as a novel RF power cell for high-linearity power amplifiers

A novel composite transistor consisting of an inverted transistor parallel-connected to a standard RF power transistor is implemented to improve the linearity of the power amplifier. The inverted transistor facilitates the predistortion and feedback functions. The P1dB output power and IP3 of the composite transistor PA are increased by 5 and 7 dB, respectively. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 45: 483–485, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20859

Analog circuits in ultra-deep-submicron CMOS

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.

An analytical study of current-voltage characteristics and breakdown performance of GaInP∕GaAs composite collector double heterojunction bipolar transistor

An analytical model taking into account the nonlocal dead-space effects is developed to study the dc characteristics and avalanche multiplication of GaInP∕GaAs double heterojunction bipolar transistor (DHBT) incorporating composite collector designs. The dependence of the turn-on characteristics and the multiplication onset of the HBT on the device composite layer thickness and doping densities are investigated. In this paper, optimum combinations of composite parameters are presented to obtain zero spike effect in the base-collector heterojunction conduction band and to improve output breakdown voltages. The model is then applied to the GaInP∕GaAs DHBT with AlGaAs in the composite collector, which is found to have good I-V characteristics and high operating voltage range before the onset of avalanche multiplication.

Analytical investigation of dead space effect under near-breakdown conditions in GaInP/GaAs composite double heterojunction bipolar transistors

The dead space effect under near-breakdown conditions in GaInP/GaAs composite collector double heterojunction bipolar transistor (DHBT) is investigated analytically. Using the dead space corrected model, the breakdown voltage is found to decrease with GaAs spacer thickness as reported from experiments. The common-mode emitter IV characteristics for the DHBT are simulated until the onset of multiplication with good agreement with reported experimental results [IEEE Elec. Dev. Lett. 15 (1994) 10]. A proposed optimised structure is simulated with comparably good turn-on I– V characteristics and improved breakdown performance.

InGaP/GaAs/InGaP composite collector double heterojunction bipolar transistor with high breakdown, low offset, and knee voltage

A InGaP/GaAs/InGaP composite collector double heterojunction bipolar transistor (DHBT) has been designed and fabricated to combine the advantages of single heterojunction bipolar transistor (SHBT) and conventional DHBT. The device has low collector–emitter offset voltage (∼60 mV) and knee voltage (&amp;lt;1 V). The breakdown voltage of ∼14 V is as high as that of a conventional DHBT. Comparison was made with a GaAs homojunction bipolar transistor and InGaP/GaAs SHBT. Both homojunction transistor and composite collector DHBT show similar collector–emitter offset voltage dominated by the geometrical factor. The knee voltage of the composite collector DHBT is ∼0.15 V lower than that of the InGaP/GaAs SHBT. The results demonstrate the potential of composite collector DHBTs for practical power amplifier applications.

Nonlinear current-voltage characteristics of Pt nanowires and nanowire transistors fabricated by electron-beam deposition

We have fabricated Pt/C composite nanowires and nanowire transistors, using the technique of electron-beam-induced deposition. The current-voltage characteristics of the granular nanowires are strongly nonlinear at 4.2 K, and evidence for this nonlinearity is found to persist to room temperature. A voltage gap of order 0.1–0.2 V is observed at the lowest temperatures, and we suggest that this feature is consistent with single-electron tunneling via Pt nanocrystals that form in the wires during their fabrication. In order to further explore this possibility, we incorporate the nanowires into three-terminal transistor structures and find evidence for a gate-induced modulation of their voltage gap.

Harmonic and intermodulation performance of the Darlington composite bipolar junction transistor

New expressions, in terms of the ordinary and modified Bessel functions, are presented for the amplitudes of the output harmonic and intermodulation products of the Darlington composite bipolar junction transistor excited by a multisinusoidal input voltage. SPICE simulation results confirming the presented theory are included.

Analysis of collector-emitter offset voltage of InGaP/GaAs composite collector double heterojunction bipolar transistor

The Ebers–Moll-like terminal current expressions of a composite collector double heterojunction bipolar transistor (DHBT), which takes the recombination effect into account, have been formulated and an expression for collector-emitter offset voltage [VCE(offset)] has been derived. Factors affecting the VCE(offset) of a composite collector DHBT are investigated and good agreement between the calculated and reported experimental results is shown. Analytical results showed that the transmission coefficient of the base-collector (B-C) junction does not have a considerable effect on the VCE(offset), provided that the B-C junction is of good quality. Thus, despite its asymmetric structure, the VCE(offset) of an optimally designed composite collector DHBT could be as low as that of a conventional DHBT. Hence a composite collector DHBT with low saturation voltage and negligible VCE(offset) is possible if the two conditions: (i) good quality B-C junction, (ii) base transport factor, α≈1, are fulfilled.

A 0.15-μm 60-GHz high-power composite channel GaInAs/InP HEMT with low gate current

This letter presents recent improvements and experimental results provided by GaInAs/InP composite channel high electron mobility transistors (HEMT). The devices exhibit good dc and rf performance. The 0.15-/spl mu/m gate length devices have saturation current density of 750 mA/mm at V/sub GS/=+0 V. The Schottky characteristic is a typical reverse gate-to-drain breakdown voltage of -8 V. Gate current issued from impact ionization has been studied in these devices, in the first instance, versus drain extension. At 60 GHz, an output power of 385 mW/mm has been obtained in such a device with a 5.3 dB linear gain and 41% drain efficiency which constitutes the state-of-the-art. These results studied are the first reported for a composite channel Al/sub 0.65/In/sub 0.35/As/Ga/sub 0.47/In/sub 0.53/As/InP HEMT on an InP substrate.

Model for InGaP/GaAs/InGaP double heterojunction bipolar transistor

The current–voltage characteristics of an InGaP/GaAs/InGaP double heterojunction bipolar transistor (DHBT) are modeled where the tunneling effect at the base–collector (B–C) junction and base–emitter (B–E) junction is taken into account. Therefore, this model can be applied to both conventional DHBT and composite collector heterojunction bipolar transistor. The role of the n−GaAs layer and n+InGaP layer are discussed and the effects of variation in the doping level and thickness of these layers are considered in the model. Good agreement between our predictions of the model and reported experimental results is achieved.

Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to \vert {V_{t}}\vert +{2\,V_{ds,sat}} and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 μm N-well process with a 3 V supply are given.

A Low Power Dissipation Technique for a Low Voltage OTA

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (±1.5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang’s OTA to create another OTA, named Low Power Wang’s OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang’s OTA. Although the static power of Low Power Wang’s OTA is 122 μW, it has a sufficient input range, whereas conventional Wang’s OTA needs 703 μW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang’s OTA becomes larger.

A low-voltage low-power wide-range CMOS variable gain amplifier

In this paper, a compact low-power (LP) low-voltage (LV) metal-oxide-semiconductor-only (MOS-only) variable gain amplifier (VCA) is introduced. This amplifier based on complementary MOS (CMOS) transistors operating in strong inversion is composed of a pseudo-exponential current-to-voltage converter, analog multiplier, and output stage. The gain of the amplifier is controlled exponentially by a novel wide-range pseudo-exponential current-to-voltage converter implemented with two back-to-back connected current mirrors exhibiting superb exponential characteristic. Also, a new LV/LP composite transistor is introduced to increase the input dynamic range of the multiplier. The amplifier is fabricated using a 2-/spl mu/m MOSIS n-well process, and its simulation and measurement results are shown in detail.

New aspects and mechanism of kink effect in InAlAs/InGaAs/InP inverted HFETs

The kink effect in InAlAs/InGaAs/InP composite channel heterojunction field effect transistors (HFETs) was investigated as a function of temperature and optical excitation. Drain source and gate current measurements show that above 325 K the kink effect disappears while the impact ionization process is still present. The kink at low temperatures is suppressed by illumination with photons of energy above 1 eV. These results prove that this parasitic effect is mainly related to the presence of traps in the top layers.

Study of Ohmic contact resistance to Ga[sub (1−X)]In[sub (X)]As/InP composite channel InP high electron mobility transistors for X=35% to X=81%

This article reports the performance of alloyed Ohmic contacts to Ga(1−X)In(X)As/InP composite channel InP high electron mobility transistors for various indium compositions, from X=35% to X=81%. Both strained and pseudomorphic structures were utilized to observe the impact of the indium concentration on electron mobility, carrier concentration, sheet resistance, and specific contact resistance. The lowest specific contact resistance (Rt<0.16 Ω mm) was obtained for strained structures with indium concentrations of 74% and 81%. For strained structures with indium concentrations of 35%, we observe specific contact resistance of 0.35 Ω mm.

Effect of collector design on the d.c. characteristics of [formula omitted] heterojunction bipolar transistors

InGaP GaAs heterojunction bipolar transistors with various collector structures are compared. The dependence of d.c. device characteristics on the thickness of the n − GaAs spacer in the collector of composite collector devices is presented. Results indicate that the spacer thickness significantly affects the performance of the transistor. An n + doping spike on the InGaP side of the collector heterojunction is included in the collector design of the composite collector devices. Standard single-heterojunction d.c. results are compared to abrupt double- and composite collector heterojunction devices. Optimization of the spacer thickness, in conjunction with the n + doping spike, eliminates most of the detrimental effects associated with a double-heterojunction device while retaining the beneficial properties of a wide-gap collector. As expected, the composite collector structure produces devices with higher breakdown voltages and lower offset voltages than single heterojunction devices. In addition, optimizing the spacer thickness can reduce the collector current saturation voltage of the composite collector device below that of a single-heterojunction device. These characteristics make composite collector heterojunction bipolar transistors ideal candidates for high power microwave device applications.

Series-parallel association of FET's for high gain and high frequency applications

This paper presents a simple approach in the design of composite field effect transistors with low output conductance. These transistors consist of the series association of two transistors, with the transistor connected to the drain terminal wider than the transistor connected to the source terminal. It is shown that this composite transistor has the same DC characteristics as a long-channel transistor of uniform width. A composite transistor has two main advantages over its "DC equivalent" transistor of uniform width: significant area savings and a higher cutoff frequency. The main application is low-voltage, high-frequency analog circuits. The proposed technique is particularly suited for analog design in gate arrays.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed InGaAs/InP composite collector bipolar transistors

The authors describe a composite collector bipolar transistor structure capable of high-speed and high breakdown voltage (BV/sub CEO/). The structure uses a composite collector of InGaAs and InP. f/sub T/=120 GHz at V/sub CE/=1.5 V at a current density of 77 kA/cm/sup 2/ were obtained. The breakdown voltage BV/sub CEO/ is greater than 5 V, and the output conductance is essentially independent of the collector voltage. Microwave transistors with an emitter size of 3*10 mu m/sup 2/ were fabricated by a self-aligned process. Microwave measurements were made from 100 MHz to 40 GHz as a function of the collector current and V/sub CE/. The authors have also fabricated and tested transimpedance amplifiers based on the composite collector transistors.