Complex Digital Design Research Articles

Three-dimensionally printed implant surgical guide-related experience, knowledge, attitude, and professional behaviors among 2028 dentists in China: A cross-sectional study

Statement of problemResearch on the current place of 3-dimensionally printed implant surgical guides (3D-ISGs) among practicing dentists worldwide is lacking, with little research focused on dentists’ experience, knowledge, attitude, or professional behavior related to 3D-ISG or on the main obstacle to adoption. PurposeThe purpose of this cross-sectional study was to identify the adoption of 3D-ISG in dental practice in China and to determine factors that influence its further application and dentists’ attitudes and willingness. Material and methodsSemistructured questionnaires were sent to a sample of Chinese dentists composed of users and nonusers of 3D-ISG. The questionnaires were displayed and distributed through a professional online survey system (http://www.wjx.cn) and a social media platform (WeChat). The responses were analyzed with multivariable generalized equations, and the effect of various demographic variables was determined, including dentist experience, academic degree, and type of practice (public or private). ResultsA total of 2028 valid questionnaires were collected. In dental practice, 39.3% of the respondents used 3D-ISG. Respondents with a PhD (62.4%) used the 3D-ISG more than twice as frequently as respondents with a junior college degree or below (31.8%). The majority of the members of implantology departments (81.7%) applied 3D-ISG, but doctors in other departments used it at a rate of less than half. The 3D-ISG was most frequently used in the maxillary anterior area (78.4%), followed by the edentulous maxilla and mandible (61.0% and 60.5%, respectively). The main barriers were high initial cost, complex and time-consuming digital design, and lack of expertise in the proper use of 3D-ISG. ConclusionsMost dentists did not use 3D-ISG in dental practice. The 3D-ISG application rate was significantly associated with sex, academic degree, years of dental practice, department, monthly income, and type of healthcare facility. To improve the popularity of 3D-ISG, particularly among dentists without advanced degrees, it would be important to optimize the digital design software program and provide sufficient training.

Spatial confinement of multi-enzyme for cascade catalysis in cell-inspired all-aqueous multicompartmental microcapsules

Biocatalytic reaction networks in eukaryotic cells is realized by the immobilized and compartmental multi-enzymatic system. Inspired by the spatial localization of natural cells, multiple enzymes were confined within the multicompartmental microcapsules, which were created using a gas-shearing method coupled with surface-triggered in situ gelation strategy. Heterogeneous multicompartmental (two-, three-, four-, six-, or eight-faced) core particles, due to their capacity for positional assembly, were encapsuled in alginate hydrogel shells. The generated microcapsules integrate logic network to access complex digital design through a three-step convergent enzymatic cascade reaction as a model, and the capsules with high stability, recyclability and cytocompatibility are ideal enzymatic reactor systems to be used for biomimetic biocatalysis process.

Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications

A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.

Digitally Controlled Single-inductor Multiple-output Synchronous DC-DC Boost Converter with Smooth Loop Handover Using 55 nm Process

This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

FPGA-based elastic in-circuit debugging for complex digital logic design

In digital integrated circuit design, the emergence of intellectual property (IP) reuse technology reduces the complexity of system on chip (SoC) design, and makes the SoC have more and more powerful functions. Unfortunately, it also increases the verification difficulty, and extends the whole system design cycle. Aiming at the low efficiency of stimulating mechanism, the difficulty of real-time signal monitoring and non-reusability of module-level verification platform for IP design based on field-programmable gate array (FPGA), we propose a kind of elastic in-circuit debugging method for complex digital logic design so as to optimise the verification process. Based on the extension of traditional IP verification platform, we build the IP in-circuit debugging platform, which has some advantages such as elasticity, configurability, extensibility and humanisation. After verification of multiple IP instances, the results show that the method has strong universality and can improve the efficiency of IP verification.

FPGA-based elastic in-circuit debugging for complex digital logic design

FPGA-based elastic in-circuit debugging for complex digital logic design

Neural Controller for UPS Inverters Based on B-Spline Network

This paper proposes a controller for uninterruptible power supply inverters based on a particular type of online-trained neural network, which is called the B-spline network (BSN). Due to its linear nature and local weight updating, the BSN controller is more suitable for real-time implementation than conventional multilayer feedforward neural controllers. Based on a frequency-domain stability analysis, a design methodology for determining the two main parameters of the BSN are presented. The model is found to be similar to that of an iterative learning control (ILC) scheme. However, unlike ILC, which requires a complex digital filter design that involves both causal and noncausal parts, the design procedure of the proposed BSN controller is straightforward and simple. Experimental results under various conditions show that the proposed controller can achieve excellent performance, comparable to that of a high-performance ILC scheme developed earlier. The proposed controller is an attractive alternative to both the multilayer feedforward neural controller and iterative learning controller in this and similar applications.

Complex coefficient nonrecursive digital filter design using a least-squares method

A method for the design of complex-coefficient nonrecursive filters is described. In this method, a mean square error is formulated in a quadratic form. The filter coefficients are obtained by solving a system of linear equations using computationally robust and efficient algorithms. Examples are presented to demonstrate the efficacy of our method.

VHDL Motivation

The goals of the very high speed integrated circuit (or VHSIC) program are to reduce IC design time and effectively insert VHSIC technology into military systems. These goals, indicating the need for a standard means of communication to stream-line advanced digital design and documentation, motivated the development of a hardware description language. Requirements were analyzed during 1981; program organization was formulated during 1982; and the VHSIC hardware description language (or VHDL) program was launched in August, 1983. Acting as a standard design automation interface, VHDL will simplify complex digital system design. Acting as design documentation agent, it will facilitate design insertion into electronic systems. Organization of the VHDL program is detailed elsewhere.1 We will discuss elements motivating hardware description language use (VHDL in particular) and examine its impact on governmental, industrial, and academic participation in electronic research, business, and education.