Complementary Transistors Research Articles

Heterogeneous Integration of Complementary Field-Effect Transistors for High-Performance Micro LED Displays.

This study investigates a micro light-emitting diode (µLED) pixel circuit using the heterogeneous integration of complementary field-effect transistors (CFETs). The CFETs are fabricated using a semiconductor layer composed of tellurium (Te) and indium-gallium-zinc oxide (IGZO) layers. Te and IGZO layers in the heterostructure IGZO/Te film exhibit hexagonal and amorphous phases, respectively, indicating that each layer maintains independent material characteristics. The fabricated IGZO/Te CFETs exhibit ambipolar behavior with a turn-on voltage of 2.0V and field-effect mobility of 0.74 and 1.42 cm2 V-1 s-1 for p-type and n-type channels, respectively. Inverters comprising IGZO/Te CFET and IGZO TFT exhibit inverting behavior. A µLED pixel circuit is designed using IGZO/Te CFETs based on pulse width modulation (PWM). The proposed circuit uses an inverter structure with IGZO/Te and IGZO to control the emission time, suppressing the wavelength shift of µLEDs depending on the µLED current levels. The operation of the proposed pixel circuit is investigated through simulation and measurement of the fabricated circuit. The fabricated µLED pixel circuit successfully exhibits PWM operation, controlling the emission time and luminance. Consequently, IGZO/Te CFETs show promise as devices for high-quality µLED displays.

Flexible p-Type WSe2 Transistors with Alumina Top-Gate Dielectric.

Tungsten diselenide (WSe2) field-effect transistors (FETs) are promising for emerging electronics because of their tunable polarity, enabling complementary transistor technology, and their suitability for flexible electronics through material transfer. In this work, we demonstrate flexible p-type WSe2 FETs with absolute drain currents |ID| up to 7 μA/μm. We achieve this by fabricating flexible top-gated FETs with a combined WSe2 and metal contact transfer approach using WSe2 grown by metal-organic chemical vapor deposition on sapphire. Despite moderate WSe2 crystal grain size, our devices show similar or higher |ID| and ID on/off ratio (∼105) compared to most devices with exfoliated single-crystal WSe2 from the literature. We analyze charge trapping in our devices using pulsed and bias stress measurements. Notably, the high |ID| values are preserved during pulsing, where charge trapping is minimized. Overall, we demonstrate a fabrication approach advantageous for high drain currents in flexible 2D transistors.

(Keynote) Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices

After a short description of the evolution of metal-oxide-semiconductor (MOS) device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material properties of complicated Si/SiGe multi-layer stacks used for complementary field effect transistor (CFET) devices. They contain two different Ge concentrations and have been grown using conventional process gases. A relatively high growth temperature is used to obtain acceptable Si and SiGe growth rates. Still island growth has been suppressed for Ge concentrations up to 40%. Excellent structural and optical material properties of the Si/SiGe multi-layer stack will be reported, with up to 3 + 3 Si channels in the top and bottom part of the stack, respectively. The absence/presence of lattice defects has been verified by room temperature photoluminescence measurements. Photoluminescence measurements at low temperatures are used to study band-to-band luminescence from individual sub-layers and to illustrate the optical material quality of the CFET stack.

Source/Drain Epitaxy for Nanosheet-Based CFET Devices

This work reports the progress in source/drain (S/D) epitaxy development for nanosheet-based monolithic complementary field effect transistors (mCFET). S/D processes which were set-up for bulk finFET devices can be easily transferred to mCFET devices. Owing to the complicated integration and small dimensions of the highly scaled structures however, more attention is required for the pre-epi cleaning of the exposed channel interfaces and for the additional defectivity that arises from the merging of individual epitaxial growth fronts. Low-temperature epi processes can be structurally integrated in mCFET devices, to further reduce the transistor access resistance components and comply with thermal budget limitations.

Two-Dimensional Semiconductors for State-of-the-Art Complementary Field-Effect Transistors and Integrated Circuits.

As the trajectory of transistor scaling defined by Moore's law encounters challenges, the paradigm of ever-evolving integrated circuit technology shifts to explore unconventional materials and architectures to sustain progress. Two-dimensional (2D) semiconductors, characterized by their atomic-scale thickness and exceptional electronic properties, have emerged as a beacon of promise in this quest for the continued advancement of field-effect transistor (FET) technology. The energy-efficient complementary circuit integration necessitates strategic engineering of both n-channel and p-channel 2D FETs to achieve symmetrical high performance. This intricate process mandates the realization of demanding device characteristics, including low contact resistance, precisely controlled doping schemes, high mobility, and seamless incorporation of high- κ dielectrics. Furthermore, the uniform growth of wafer-scale 2D film is imperative to mitigate defect density, minimize device-to-device variation, and establish pristine interfaces within the integrated circuits. This review examines the latest breakthroughs with a focus on the preparation of 2D channel materials and device engineering in advanced FET structures. It also extensively summarizes critical aspects such as the scalability and compatibility of 2D FET devices with existing manufacturing technologies, elucidating the synergistic relationships crucial for realizing efficient and high-performance 2D FETs. These findings extend to potential integrated circuit applications in diverse functionalities.

Multi-objective optimization and inverse design of complementary field-effect transistor using combined approach of machine learning and non-dominated sorting genetic algorithms for next-generation semiconductor devices

Complementary field-effect transistors (CFETs), which are structures in which different types of transistors are vertically stacked with a shared control gate, are being focused on for continuing to satisfy Moore's law by overcoming the limitations in pitch scaling. The structures of semiconductor devices become more complex as technology node shrinks, and interrelated multivariate parameters increase. In addition, predicting problems and proposing solutions by identifying complex patterns within extensive data collected for emerging semiconductor designs pose significant computational challenges and are inherently difficult. As a breakthrough in design technology co-optimization for advanced devices, this study developed a novel optimization framework integrating technology computer-aided design simulations, machine learning, and non-dominated sorting genetic algorithms. The developed framework provides unbiased optimal solutions, even in a high-dimensional objective space, while considering the tradeoff relationships between multiple variables. In addition, it enables inverse design to identify the design parameters of devices that satisfy specific electrical performance criteria using only a forward model, while achieving an error rate of less than 2%. Using this framework, we analyzed the operational mechanism of CFETs by comparing the inverse designs of various devices. This novel approach is particularly important when the design space is complex and extensive and is well suited for developing devices that emerge with technological advancements in the semiconductor industry.

(Invited) Material Engineering for the GAA and Post-GAA Transistors and Interconnects

Feature scaling in advanced CMOS technology has been slowing down starting at 10 nm node and is expected to stop completely in the next few years. Nevertheless, transistor density scaling is continuing at a Moore’s law pace, driven by DTCO and 3D IC.Transistor dimensions and minimum metal pitch are expected to be massaged down only by 10% to 20% during the next decade. However, both the transistor and the interconnect will continue to evolve and improve both in performance and in variability.Currently, the industry is transitioning from FinFET technology to GAA (Gate All-Around) technology. The next transition, from GAA to the NMOS and PMOS GAA transistors stacked on top of each other (often referred to as CFET (Complementary Field Effect Transistor)) is expected in 8 to 10 years from now.The main methodology for GAA and CFET transistor engineering comes down to bandstructure engineering, where material composition, shape and thickness of different layers, and mechanical stress are engineered to tailor a bandstructure of the channel that maximizes on-state driving strength and minimizes off-state leakage and variability. The key methodology for bandstructure engineering is ab-initio analysis of transistor components and then transfer of the obtained bandstructure to transistor scale analysis to characterize its behavior.For the interconnect engineering, the tight metal pitches and increasingly tall and narrow vias dictate transition from copper to alternative metals, with a preference for the metals that can be etched and selectively grown. The key methodology for interconnect engineering is ab-initio analysis of electron scattering at the interfaces and grain boundaries. The scattering is then converted into interconnect resistance that defines speed and power consumption of the advanced CMOS circuits.This work introduces the concepts of transistor band structure engineering and interconnect scattering engineering and provides illustrations of these methodologies applied to GAA and post-GAA technologies.

Advances in CMOS Image Sensors and Transistors Leveraging Stochastic Nanomagnets: A Comprehensive Review

Accurate modeling and assessment of complex Complementary Metal-Oxide Semiconductor (CMOS) imaging sensors and transistors, in conjunction with randomized nanomagnets for distributed computation in radiated environments, are crucial for the development of robust electronic systems. The effectiveness and resilience of these intricate parts to radiation exposure is the subject of this study, which is becoming more and more important in applications including space missions, power plants, and high-altitude flying. To take into account the interaction between CMOS technology and the unpredictable behavior of nanomagnets, a comprehensive durability modeling technique is required. The methodology that has been suggested evaluates the susceptibility of image detectors and transistors to malfunctions caused by radiation, such as dislocation damage, single-event upsets (SEUs), and impacts of total ionizing dose (TID). The impact of radiation on the power characteristics and operational dependability of these components is investigated using state-of-the-art modeling tools and experimental data. The findings suggest that random nanomagnets can improve distributed computing devices' resistance to radiation-induced failures. Through the provision of insights into reliability challenges and solutions for enhanced CMOS image sensors and transistors, this work advances the field of radiation-tolerant technologies. Future electronic device developers will find the suggested reliability modeling and evaluation methodology to be a useful resource for creating reliable devices that can resist harsh radioactive environments. Keywords— Reliability Modeling; CMOS Image Sensors; Radiation Environment; Advanced Technology Node; Transistor Structures; Stochastic Nanomagnets; Heterogeneous Computing; Probabilistic Inference

Statistical analysis of vertically stacked nanosheet complementary FET based on polycrystalline silicon with multiple grain boundaries

In this study, a complementary field-effect transistor (CFET) based on a polycrystalline silicon (poly-Si) stacked-nanosheet (NS) structure with a grain boundary (GB) is designed and analyzed using a technology computer-aided design (TCAD) simulation. The advantage of the CFET using a poly-Si is that the active cell region can be reduced by 50 % because the p-type transistors are vertically stacked on the n-type transistors. In addition, it is possible to replace the conventional CMOS process and fabricate a three-dimensional vertically stacked structure at a low cost. To consider the effect of the GB in poly-Si, we assumed that there is a single GB at the center of the body region. By optimizing the geometrical parameters of the proposed CFET, the transfer characteristics of the NMOS and PMOS transistors, such as the threshold voltage (Vth), on current (Ion), off current (Ioff), and subthreshold swing (SS), are symmetrical. The proposed CFET demonstrated a superior logic performance of NML = 0.299 V and NMH = 0.297 V at an operation voltage of VDD = 0.65 V. To consider random GBs in the poly-Si, we assumed that five GBs existed in the proposed CFET, and the variation in CMOS logic inverter characteristics are statistically analyzed. As a result, the RSDs for Vm of the NMOS and PMOS transistors are 2.067 % and 0.293 %, and the RSDs of the pull-down delay time (tpHL) and pull-up delay time (tpLH) are 5.320 % and 3.244 %, respectively. An acceptor-like traps with high trap density are dominant in the proposed CFET, and this trend is similar across the 1024 samples. Nevertheless, most of the differences are within 5 % and the proposed CFET exhibited stability against GBs and the potential to replace the conventional CMOS logic inverters.

Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors.

The semiconductor industry is transitioning to the 'More Moore' era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe2 FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials' role in advancing M3D integration in complementary metal-oxide-semiconductor circuits.

Simulation of 2D ReS2/WSe2 based complementary field-effect transistors towards 1 nm technology node

Advanced Integrated Circuit technology demands high-performance channel materials and innovative device architectures to sustain the scaling of field-effect transistors. In this study, we simulate the electrical performance of rhenium disulfide and tungsten diselenide nanosheet FETs (NSFETs) with gate lengths ranging from 12 nm to 8 nm using Technology Computer-Aided Design method. The simulated high performance including 393 μA/μm on-state current and over 105 on/off ratio can meet the criteria for integrated circuit applications in the 1 nm technology node. Complementary FET (CFET) simulations are conducted through the vertical stacking of ReS2 and WSe2 NSFETs, exhibiting a small parasitic capacitance of 1.0 fF/μm, and notable noise margin (>235 mV) at different process corners. The construction and performance simulation of Static Random-Access Memory (SRAM) is realized through CFET interconnection, involving the calculation of read current and read/write noise margin. This research offers a forward-looking analysis of performance metrics for future 2D materials-based NSFETs, CFETs, and SRAMs.

Van der Waals polarity-engineered 3D integration of 2D complementary logic

Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis1–3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers with different carrier types6–8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9–17) and MoS2 (refs. 11,18–28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm2 V−1 s−1, on/off ratios reaching 106 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

From MOSFET to FinFET to GAAFET: The evolution, challenges, and future prospects

With the swift progression of semiconductor technology, the transition from Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) to Fin Field-Effect Transistors (FinFETs) and further to Gate-All-Around Field-Effect Transistors (GAAFETs) presents significant potential for the future of electronic devices and systems. This article delves into the intricate applications, challenges, and prospective evolutions associated with FinFET and GAAFET technologies. Findings suggest that these technologies are particularly apt for low-power logic systems, high-performance computing, and artificial intelligence domains. However, as dimensions shrink, challenges pertaining to heat dissipation, leakage, and manufacturing consistency become prominent. Despite these hurdles, the horizon for semiconductor technology remains bright, encompassing exploration of alternative materials such as Germanium and 2D compositions and innovative designs like U-shaped Field-Effect Transistors and Complementary Field-Effect Transistors. As the industry continues its relentless pursuit of even more efficient, smaller transistors, the exploration of alternative materials and diversification in architecture may play a pivotal role in future developments. In essence, while the semiconductor sphere confronts challenges, relentless innovation promises a future brimming with even more efficient and compact transistor technologies.

Two‐Dimensional Heterostructure Complementary Logic Enabled by Optical Writing

Integrated logic circuits using atomically thin, two‐dimensional (2D) materials offer several potential advantages compared to established silicon technologies such as increased transistor density, circuit complexity, and lower energy dissipation leading to scaling benefits. In this article, a novel approach to achieve tunable doping in 2D semiconductors is explored to achieve complementary transistors and logic integration. By selectively transferring WSe2 onto hBN and SiO2 substrates, complementary transistor behavior (n‐ and p‐type) was achieved using a UV light source and electrostatic activation. Furthermore, advanced characterization techniques, including high‐resolution transmission electron microscopy (HRTEM) and Kelvin probe force microscopy (KPFM), provided insights into the chemical composition and surface potential changes after UV writing. Finally, a logic inverter was successfully implemented using selectively photo‐induced doped WSe2 transistors, showcasing the potential for practical logic applications. This innovative method opens new avenues for designing energy‐efficient and reconfigurable 2D semiconductor circuits, addressing key challenges in modern electronics.

Complementary negative capacitance field-effect transistors based on vertically stacked van der Waals heterostructures

Complementary field-effect transistors (CFETs) with a vertically stacked n-FET/p-FET configuration can provide a promising solution to boost area efficiency. However, the substantial power dissipation exhibited by these CFET devices poses a notable challenge to the energy efficiency. By combining a negative-capacitance field-effect transistor (NCFET) and a CFET, the problem of excessive power consumption can be solved. By using a negative-capacitance gate stack, the supply voltage (Vdd) applied to the gate of the CFET is increased, resulting in a reduction in power consumption. Here, we experimentally demonstrate a vertically integrated complementary negative capacitance field-effect transistor (NC-CFET) that combines tungsten diselenide (WSe2) p-NCFET and molybdenum disulfide (MoS2) n-NCFET. With the hexagonal boron nitride/copper indium thiophosphate CuInP2S6 (CIPS) dielectric stack, both n-type and p-type van der Waals (vdW) NCFETs exhibit sub-60 mV/decade switching characteristics. The vdW NC-CFET exhibits a voltage gain of 78.34 and a power consumption of 129.7 pW at a supply voltage of 1 V. These device characteristics demonstrate the great potential of the vdW NC-CFET for high density and low power applications.

Compositional Engineering of Cu-Doped SnO Film for Complementary Metal Oxide Semiconductor Technology.

Metal oxide semiconductor (MOS)-based complementary thin-film transistor (TFT) circuits have broad application prospects in large-scale flexible electronics. To simplify circuit design and increase integration density, basic complementary circuits require both p- and n-channel transistors based on an individual semiconductor. However, until now, no MOSs that can simultaneously show p- and n-type conduction behavior have been reported. Herein, we demonstrate for the first time that Cu-doped SnO (Cu:SnO) with HfO2 capping can be employed for high-performance p- and n-channel TFTs. The interstitial Cu+ can induce an n-doping effect while restraining electron-electron scatterings by removing conduction band minimum degeneracy. As a result, the Cu3atom%:SnO TFTs exhibit a record high electron mobility of 43.8 cm2 V-1 s-1. Meanwhile, the p-channel devices show an ultrahigh hole mobility of 2.4 cm2 V-1 s-1. Flexible complementary logics are then established, including an inverter, NAND gates, and NOR gates. Impressively, the inverter exhibits an ultrahigh gain of 302.4 and excellent operational stability and bending reliability.

Design of BJT-JFET Operational Amplifiers on the Master Slice Array

The use of dual-gate field-effect transistors located on the base matrix crystal MH2XA031, controlled by a p–n junction needed to reduce the input current of operational amplifiers is studied. Typical circuits of operational amplifiers, containing: source repeaters connected to the inputs of the operational amplifier on complementary bipolar transistors; input differential stage on p-JFET with a “current mirror” load on n–p–n-transistors; input differential in the form of a “folded cascode” on a p-JFET are analyzed. To minimize the input current, it is re commended to use bootstrapped feedback to keep the drain-to-source voltage of the input JFETs low, independent of the input common-mode voltage, and to connect only the top gate of the dual-gate JFET to the op-amp input. The electrical circuits for MH2XA031 elements and the results of circuit simulation of the developed amplifiers, called OAmp10J, OAmp11.1, OAmp11.2, are presented. Accounting the established features of the input stages and operating modes of active elements in circuit design will allow to create an operational amplifier with the required combination of basic parameters.

Monolithically Integrated Complementary Ferroelectric FET XNOR Synapse for the Binary Neural Network.

Neuromorphic computing, which mimics the structure and principles of the human brain, has the potential to facilitate the hardware implementation of next-generation artificial intelligence systems and process large amounts of data with very low power consumption. Among them, the XNOR synapse-based Binary Neural Network (BNN) has been attracting attention due to its compact neural network parameter size and low hardware cost. The previous XNOR synapse has drawbacks, such as a trade-off between cell density and accuracy. In this work, we show nonvolatile XNOR synapses with high density and accuracy using a monolithically stacked complementary ferroelectric field-effect transistor (C-FeFET) composed of a p-type Si MFMIS-FeFET at the bottom and a 3D stackable n-type Al:IZTO MFS-FeTFT, achieving 60F2 per cell (2C-FeFET). For adjusting the threshold voltage and improving the switching speed (100 ns) of n-type ferroelectric TFT, we employed a dual-gate configuration and a unique operation scheme, making it comparable to those of Si-based FeFETs. We performed array-level simulation with a 512 × 512 subarray size and a 3-bit flash ADC, demonstrating that the image recognition accuracies using the MNIST and CIFAR-10 data sets were increased by 3.17 and 14.07%, respectively, in comparison to other nonvolatile XNOR synapses. In addition, we performed system-level analysis on a 512 × 512 XNOR C-FeFET, exhibiting an outstanding throughput of 717.37 GOPS and an energy efficiency of 196.7 TOPS/W. We expect that our approach would contribute to the high-density memory systems, logic-in-memory technology, and hardware implementation of neural networks.

Compact Model Build Upon Dynamic Weighting Artificial Neural Network Approach for Complementary Field Effect Transistors

Compact Model Build Upon Dynamic Weighting Artificial Neural Network Approach for Complementary Field Effect Transistors

CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing

CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing