Complementary MOS Transistors Research Articles

Silicon-gate CMOS frequency divider for electronic wrist watch

An integrated complementary MOS transistor scale-of-two counter for applications in electronic wrist watches has been realized. Silicon-gate technology applied to a very simple but safe dividing circuit has resulted in a substantial reduction of the total area of the integrated structure with the following performance. At a supply voltage of 1.35 V the maximum frequency is 2 MHz and the dynamic power consumption per stage is 1.6 nW/kHz. The complementary substrate is obtained by a sealed-capsule low-surface concentration diffusion and doped oxides as impurity sources are used to allow simultaneous diffusion of both types of MOS transistors. A simple dynamic circuit derived from the basic structure is described.

The preparation and properties of chemically vapor deposited silicon on sapphire and spinel

A comparison is made between the semiconducting properties of thin silicon films epitaxially grown, by chemical vapor deposition processes, on single crystal sapphire and spinel. The relationship between the epitaxial growth conditions and the electrical properties is examined. Within a wide range of growth conditions, the as-deposited thin film properties appear to be dominated by the surface finishing and crystalline nature of the substrate. The change in the electrical properties during thermal oxidation is associated with the presence of impurities introduced from the substrate, and the magnitude of the change is a strong function of the epitaxial growth conditions. Despite the many factors which limit the carrier mobility in the heteroepitaxial thin films, complementary pair MOS transistors have been fabricated in silicon thin films on sapphire and spinel which have distinct advantages over similar devices fabricated in bulk silicon.

Complementary MOS—Bipolar transistor structure

Bipolar transistors can be used to increase the driving capabilities of complementary MOS transistors while retaining the low power dissipation feature. The fabrication of n-p-n bipolar transistors is compatible with the fabrication of the complementary MOS transistors in a monolithic structure. Common collector n-p-n transistors can be fabricated using a diffused n+source-drain region as emitter, a diffused p-isolation region as base and an n-substrate as collector with a h fe greater than 100. Lateral n-p-n transistors can be fabricated using a diffused n+source-drain region as emitter and collector, and p-isolation region as base with a h fe greater than 10.

Complementary MOS-bipolar structure

Medium and large scale integrated arrays employing complementary MOS transistors, are capable of driving low capacitive loads only. An n-p-n bipolar transistor with an isolated collector is needed when an integrated circuit is required to drive large capacitive loads without deterioration in the maximum operating frequency.

Thin-film silicon: Preparation, properties, and device applications

This paper will review the properties of thin silicon films deposited on sapphire (SOS) and magnesium aluminate spinel by the pyrolysis of silane in the temperature range 900-1200°C. Variations of carrier mobility, free-carrier concentration, minority carrier lifetime, crystalline perfection, and surface quality will be discussed as a function of substrate crystal and growth parameters. MOS transistors exhibiting field-effect mobility close to that obtained with bulk silicon have been fabricated and a complementary MOS transistor memory cell has been constructed with a WRITE-READ delay of 6 ns. The standby power for the cell is typically 10 µW. Other CMOS circuits display a pair-delay of 1.5-2.0 ns. AIl-epitaxial bipolar transistors with a current gain of 5 and f T of 350 MHz have been made in which all layers are sequentially deposited during one high-temperature operation. Recent improvements in bipolar fabrication techniques have lead to current gains as high as 25 at 10 mA.

Complementary-MOS low-power low-voltage integrated binary counter

An integrated complementary MOS-transistor binary counter stage, particularly suited to low-power low-voltage applications, has been realized in monolithic form. The topology of the circuit allows one to group together all p-channel MOSTs and all n-channel MOSTs within two distinct surface areas. This feature results in an appreciable reduction of the surface necessary for a given circuit function. Dynamic current consumption is about 10 nA per kHz at a supply voltage of 1.35 volts. The complementary type of substrate is obtained by etching and epitaxially refilling wells in the original substrate material. Technological problems which had to be solved in order to achieve low-power low-voltage operation in complementary integrated MOS circuits will be discussed.

A Low-Power Multiphase Circuit Technique

The principle of multiphase MOS digital circuits is briefly discussed and the features of some presently used multi-phase schemes are given. The basic theory and implementation of a six-phase scheme, which make use of a basic principle not normally considered in low-power digital circuitry, are then described, and the first-order equations for power dissipation are derived. The theoretical power dissipation of a six-phase shift register is compared to the power dissipation of equivalent shift registers using other low-power circuit techiques, including the complementary MOS transistor technique, and it is shown that the six-phase technique has the lowest power dissipation from very low frequencies up to a limiting high frequency. Finally, the power dissipation of an actual six-phase circuit is compared to the dissipation predicted from the derived equations.

Contour deposition—A new epitaxial deposition technique for semiconductor devices and integrated circuits

One limitation of the use of epitaxial deposition in semiconductor device integrated circuit design and construction has been the unsuitability of the process to produce regions with well defined doping and accurately controlled geometry in a crystal with a flat surface. A new process called “Contour Deposition” overcomes this limitation. This process exploits the observed phenomenon that epitaxial deposition of silicon tends to follow the contour of the substrate surface. A depression etched into a semiconductor substrate before epitaxy is filled during the subsequent deposition. If the crystal is polished subsequently, the structure obtained has a flat surface and an epitaxially deposited region. With sufficient attention given to polishing techniques the process was found very reproducible and epitaxial pockets up to 20 μ deep were produced with a tolerance of ±1 μ on the depths over the whole are of the silicon slice. An application of the technique is to widen the range of devices that could be built into a semiconductor crystal with compatible techniques, MOS transistor devices with junction transistors, n-p-n, p-n-p transistor pairs, complementary pair MOS transistors. The technique can also be used to produce isolated regions in a semiconductor integrated circuit with low parasitic capacitance because of the favourable geometry and doping of the isolation p-n junction. Highly conducting layers can be buried either by diffusion prior to epitaxy, or formed during epitaxy to reduce series resistance.