Complementary Metal Oxide Semiconductor Technology Research Articles

High-Sensitivity, High-Resolution Miniaturized Spectrometers for Ultraviolet to Near-Infrared Using Guided-Mode Resonance Filters

Miniaturized spectrometers have significantly advanced real-time analytical capabilities in fields such as environmental monitoring, healthcare diagnostics, and industrial quality control by enabling precise on-site spectral analysis. However, achieving high sensitivity and spectral resolution within compact devices remains a significant challenge, particularly when detecting low-concentration analytes or subtle spectral variations critical for chemical and molecular analysis. This study introduces an innovative approach employing guided-mode resonance filters (GMRFs) to address these limitations. Functioning similarly to notch filters, GMRFs selectively block specific spectral bands while allowing others to pass, maximizing energy extraction from incident light and enhancing spectral encoding. Our design incorporates narrow band-stop filters, which are essential for accurate spectrum reconstruction, resulting in improved resolution and sensitivity. Our spectrometer delivers a spectral resolution of 0.8 nm over a range of 370–810 nm. It achieves sensitivity values that are more than ten times greater than those of conventional grating spectrometers during fluorescence spectroscopy of mouse jejunum. This enhanced sensitivity and resolution are particularly beneficial for chemical and biological applications, facilitating the detection of trace analytes in complex matrices. Furthermore, the spectrometer’s compatibility with complementary metal oxide semiconductor (CMOS) technology enables scalable and cost-effective production, fostering broader adoption in chemical analysis, materials science, and biomedical research. This study underscores the transformative potential of the GMRF-based spectrometer as an innovative tool for advancing chemical and interdisciplinary analytical applications.

Reservoir Computing System with Diverse Input Patterns in HfAlO-Based Ferroelectric Memristor.

Ferroelectric memristors, particularly those based on hafnia, are gaining attention as potential candidates for neuromorphic computing. These devices offer advantages over perovskite-based ferroelectric memristors owing to their simpler structures, compatibility with complementary metal-oxide semiconductor technology, and low-power consumption characteristics. Additionally, improvements in ferroelectric memristor's performance, such as enhancing tunneling electro resistance (TER) and polarization retention, can be achieved using methods like aluminum doping and insulating film deposition. In this study, we implement a physical reservoir computing (RC) system utilizing the metal-ferroelectric-insulator-semiconductor-structured ferroelectric memristor based on Al-doped HfO2 as an artificial synapse. Specifically, we ensure the universality and diversity of the system by experimentally demonstrating a robust reservoir layer capable of handling various types of input pulses. To utilize the ferroelectric memristor in the reservoir layer of the RC system, we employ partial polarization switching of ferroelectric materials. We measure the retention loss characteristics of the device for pulse amplitude, interval, and width, and quantify the time constant values by fitting them to a stretched exponential function. Additionally, we validate the suitability of the fabricated device as an artificial synapse by mimicking various short-term plasticity functions of biological synapses. Furthermore, we experimentally demonstrate various applications related to learning and memory of the brain, such as image training and Pavlov's experiment, utilizing the short-term memory characteristics of the fabricated device. Lastly, we evaluate the robustness of the RC system under various input conditions by employing the fabricated device as a reservoir layer.

3D Nano Hafnium‐Based Ferroelectric Memory Vertical Array for High‐Density and High‐Reliability Logic‐In‐Memory Application

AbstractA new type of ferroelectric memory device with high reliability and complementary metal‐oxide‐semiconductor (CMOS) compatibility characteristics is an important condition for achieving integrated memory and computing chips. Here, 3D stacked ferroelectric memory devices based on ferroelectric materials of HfO2 are fabricated. The device exhibits high speed (50 ns), low read voltage (0.5 V), and great reliability with no substantial degradation after 1010 cycles and a 10‐years data retention at 85 °C. The IMP and NAND logic are achieved with stable memory window (>200 mV) across the vertical devices’ interconnection. On this basis, combining with the traditional CMOS logic device, multiple combination logic functions containing NOT, AND, and NOR are achieved by simulation. The collaboration of devices in the vertical direction providing the possibility of combining multi‐bit logic in memory functions and paves the way for the implementation of high‐density, high‐reliability, and low‐energy consumption computing‐in‐memory chips compatible with the CMOS technology.

High-speed voltage level-up shifter with wide range conversion for system-on-chip applications

Abstract The purpose of this investigation is to demonstrate a level shifter circuit that enhances voltage switching capacity while simultaneously reducing latency by employing a cascaded current mirror, input, and output inverters. We improved our design using multi-threshold Complementary metal oxide semiconductor (MTCMOS) technology by adding stackable transistors, super-cutoff mechanisms, and cascaded techniques. The level shifting between voltage ranges of 0.3 V and 2.0 V is accomplished by the proposed level shifter. Our design has been fine-tuned to meet the needs of system-on-chip applications by meticulously optimizing performance characteristics like energy usage, latency, and space utilization. The proposed level shifter has an area of 6.936 µm2 and a power consumption of 17 nW, with a delay of 90.64 ps. The proposed work has been done on the Cadence Virtuoso Tool using 45 nm technology. Our suggested level shifter is more effective than earlier methods in terms of latency and conversion range. In addition to delivering considerable reductions in space and power consumption, the suggested design promises a 50-fold increase in operating speed.

CMOS Pulse Oximeter

Abstract: This paper presents the design and implementation of a non-invasive pulse oximeter based on Complementary MetalOxide-Semiconductor (CMOS) technology, aimed at enhancing the accuracy and accessibility of blood oxygen saturation measurements. Pulse oximetry is a critical tool in clinical and personal health monitoring, providing vital information about respiratory function. The integration of CMOS technology allows for miniaturization and energy efficiency, facilitating the development of compact, wearable devices capable of continuous monitoring. The proposed system utilizes advanced signal processing techniques, including lock-in detection and dual-wavelength illumination, to improve the reliability of photoplethysmographic (PPG) signal acquisition under various conditions. Experimental validation demonstrates the device's capability to deliver accurate SpO2 readings even in the presence of motion artifacts and ambient light interference. Furthermore, the calibration methods employed ensure that measurements are consistent and precise across different users. By leveraging the advantages of CMOS technology, this study not only highlights the potential for improved patient comfort and compliance but also opens new avenues for the application of pulse oximetry in diverse environments. The findings underscore the effectiveness of CMOS-based pulse oximeters in advancing non-invasive health monitoring solutions, ultimately contributing to enhanced patient care and outcomes.

Performance Analysis of 8x4 Barrel Shifters in CMOS and FINFET Technology

Shifters are essential components in digital circuits, enabling data manipulation and routing for a wide range of computational tasks. This study presents a comprehensive performance analysis of 8x4 barrel shifters implemented in two distinct semiconductor technologies: Complementary Metal-Oxide-Semiconductor (CMOS) and FinFET. This study compares and evaluates the important parameters for these shifters at both technological nodes, such as power consumption. Additionally, we examine the effects of scaling on CMOS barrel shifters. Conversely, FinFET technology, recognized for overcoming certain limitations of CMOS, is assessed for its potential to enhance performance while preserving energy efficiency. Through detailed simulation and analysis, this study offers valuable insights into the benefits and limitations of CMOS and FinFET implementations for 8x4 barrel shifters. The circuit is implemented using Cadence Virtuoso and optimized to leverage the unique features and address the limitations of 45nm CMOS and 22nm FinFET technologies. Furthermore, the study offers recommendations for selecting the appropriate technology based on specific performance criteria and application needs. The findings aim to guide future design decisions and improvements in shifter technology.

Voltage Differencing Buffered Amplifier Realisation Using 32 nm FinFET Technology and Universal Filter Applications

This paper presents high-frequency universal filter applications based on a voltage differential buffered amplifier (VDBA) using 32 nm fin field effect transistor (FinFET) technology. FinFET technology is a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology to avoid the problems caused by the decrease in transistor size as the technology evolves. In addition to the manufacturing process being similar to CMOS technology, FinFET technology offers many advantages, such as reduced short channel effects, higher drain current, reduced static leakage current, faster switching time, lower supply voltage, lower power consumption, and higher efficiency. The VDBA active circuit block, which has high input impedance and low output impedance, is preferred for high-frequency and high-bandwidth applications. It is advantageous to design active filter circuits using VDBA because of its superior features, such as lower power consumption, higher bandwidth, wider range linearity, and the ability to implement the proposed circuits without external resistors. In this study, FinFET-based VDBA and filter application are simulated with the Spice simulation programme using 32 nm PTM technology parameters. Simulation results using 32 nm FinFET technology are compared with those using 0.18 µm TSMC technology. It is concluded that 32 nm FinFET technology reduces power consumption by 98.8 % and increases bandwidth by 145 times. The successful results show that FinFET technology is superior to CMOS technology in analogue circuit design. FinFET-based VDBA circuits and filters will be more advantageous in the design of signal processing and biomedical applications.

Ion-migration-induced synaptic plasticity in high ion-storable fluorine graphdiyne for information processing

Neuromorphic devices encounter constraints associated with complementary metal–oxide–semiconductor technology, such as intricate electronics and high power consumption. Recently, solid polymer electrolytes (SPE) have gained attention in electronic devices for constructing artificial synapses, primarily due to their low-voltage operation enabled by ion-assisted signal transmission. This study presents a two-terminal artificial synapse fabricated using fluorine graphdiyne (F-GDY) synthesized through chemical vapor deposition and ion-doped SPE. The device architecture consists of Au/SPE/F-GDY/Si, which operates by ion migration induced by external potential pulses. Electrical measurements are conducted to depict the synaptic plasticity of the devices. Among devices employing different ion-doped SPEs (Li-SPE, Na-SPE, K-SPE, and Ca-SPE), the one utilizing Li-SPE demonstrates the highest synaptic weight. This is attributed to the superior Li+ ion storage capacity of F-GDY. Hence, Li-SPE/F-GDY was chosen for in-depth examinations of synaptic activity presenting long-term potentiation, short-term depression, and pair-pulse facilitation. The device has good durability and stability and can respond to low action potential with power consumption at the pJ level. Furthermore, Modified National Institute of Standards and Technology simulations reveal its learning and pattern recognition capability with 91.3 % accuracy after 10 training epochs. Finally, flexible substrate-based SPE/F-GDY devices integrated with gate electrodes were fabricated to record physiological signals, showing promise for in-sensing applications. This work shows the potential of F-GDY/Li-SPE devices for low-power neuromorphic computing, though real-time parallel processing and multimodal integration (e.g., visual, auditory) remain unexplored. Even so, the biocompatibility and efficient ion-assisted transmission of F-GDY suggest promising future applications in these areas.

Efficient quantum-dot adder optimisation and analysis for future circuits

ABSTRACT In recent years, the rapid scaling of transistors has necessitated the exploration of advanced alternatives to Complementary metal oxide semiconductor(CMOS) technology for future progress. Quantum-dot cellular automata(QCA) technology has emerged as a promising solution, offering highly dense, high-speed, and low-power circuits. Among the critical digital building blocks, adder circuits play a crucial role in arithmetic and logic units. Consequently, optimising these circuits in terms of area, delay, and quantum cost is essential for the development of efficient designs. This paper presents effective multi-layer n-bit ripple carry adder(RCA) circuits, utilising full adder(FA) circuit. The outputs are generated in distinct layers and verified using the QCADesigner-Ev2.2 tool with bi-stable and coherence vector energy setups, employing Euler and Runge-Kutta methods.Additionally, the proposed designs are evaluated for various design metrics at three different scale factors(1,0.8889,and 0.7778), corresponding to cell sizes of 18 × 18 nm , 16 × 16 nm , and 14 × 14 nm respectively. The temperature’s impact on the average output polarisation of the FA is explored. The research demonstrates an n-bit-RCA surpassing existing designs with cost optimisations of 89.5%, 86%, and 90.3% for 4-bit,8-bit and 16-bit circuits, respectively. The paper also provides a thorough energy dissipation analysis for the proposed adder design.

Design of SRAM cell using an optimized D-latch in quantum-dot cellular automata (QCA) technology

A newer nanoscale technology called quantum-dot cellular automata (QCA) has been used by researchers to design digital circuits in place of the more traditional complementary metal–oxide semiconductor (CMOS) technology. This recent development in the technology change is due to the problems faced by CMOS technology in terms of power consumption and physical limitations. The advantages of QCA technology over CMOS technology are high density, low power consumption, high-speed operation, and less footprint area. This research provides a novel circuit for D-latch and static random access memory (SRAM) cells based on QCA technology. Initially, a D-latch circuit is proposed with a layout area of 0.01 μm2, a 0.5 clock cycle delay (latency), and a cell count of 18 QCA cells. Furthermore, an SRAM cell is proposed using the same D-latch circuit, which uses cell counts of 26 QCA cells and contributes to a layout area of 0.02 μm2 with a 0.75 clock cycle delay (latency). It is observed that our proposed circuits have a smaller layout area, fewer QCA cell counts, and a lower clock cycle delay (latency) than existing circuits.

ITO-Based Electrically Tunable Metasurface for Active Control of Light Transmission.

In recent years, the rapid development of dynamically tunable metasurfaces has provided a new avenue for flexible control of optical properties. This paper introduces a transmission-type electrically tunable metasurface, employing a series of subwavelength-scale silicon (Si) nanoring structures with an intermediate layer of Al2O3-ITO-Al2O3. This design allows the metasurface to induce strong Mie resonance when transverse electric (TE) waves are normally incident. When a bias voltage is applied, the interaction between light and matter is enhanced due to the formation of an electron accumulation layer at the ITO-Al2O3 interface, thereby altering the resonance characteristics of the metasurface. This design not only avoids the absorption loss of metal nanostructures and has a large modulation depth, but also shows compatibility with complementary metal oxide semiconductor (CMOS) technology.

Recent trends in neuromorphic systems for non-von Neumann in materia computing and cognitive functionalities

In the era of artificial intelligence and smart automated systems, the quest for efficient data processing has driven exploration into neuromorphic systems, aiming to replicate brain functionality and complex cognitive actions. This review assesses, based on recent literature, the challenges and progress in developing basic neuromorphic systems, focusing on “material-neuron” concepts, that integrate structural similarities, analog memory, retention, and Hebbian learning of the brain, contrasting with conventional von Neumann architecture and spiking circuits. We categorize these devices into filamentary and non-filamentary types, highlighting their ability to mimic synaptic plasticity through external stimuli manipulation. Additionally, we emphasize the importance of heterogeneous neural content to support conductance linearity, plasticity, and volatility, enabling effective processing and storage of various types of information. Our comprehensive approach categorizes fundamentally different devices under a generalized pattern dictated by the driving parameters, namely, the pulse number, amplitude, duration, interval, as well as the current compliance employed to contain the conducting pathways. We also discuss the importance of hybridization protocols in fabricating neuromorphic systems making use of existing complementary metal oxide semiconductor technologies being practiced in the silicon foundries, which perhaps ensures a smooth translation and user interfacing of these new generation devices. The review concludes by outlining insights into developing cognitive systems, current challenges, and future directions in realizing deployable neuromorphic systems in the field of artificial intelligence.

Wafer-Scale Atomic Layer-Deposited TeOx/Te Heterostructure P-Type Thin-Film Transistors.

There is an increasing demand for p-type semiconductors with scalable growth, excellent device performance, and back-end-of-line (BEOL) compatibility. Recently, tellurium (Te) has emerged as a promising candidate due to its appealing electrical properties and potential low-temperature production. So far, nearly all of the scalable production and integration of Te with complementary metal oxide semiconductor (CMOS) technology have been based on physical vapor deposition. Here we demonstrate wafer-scale atomic layer-deposited (ALD) TeOx/Te heterostructure thin-film transistors with high uniformity and integration compatibility. The wafer-scale uniformity of the film is evidenced by spatial Raman mappings and statistical electrical analysis. Furthermore, surface accumulation-induced good ohmic contact has been observed and explained by the unique band alignment of the charge neutrality level inside the Te valence band. These results demonstrate ALD TeOx/Te as a promising p-type semiconductor for monolithic three-dimensional integration in BEOL CMOS applications incorporated with well-established n-type ALD oxide semiconductors.

Complementary Metal-Oxide-Semiconductor-Based Magnetic and Optical Sensors for Life Science Applications.

Optical and magnetic sensing methods are integral to both research and clinical applications in biological laboratories. The ongoing miniaturization of these sensors has paved the way for the development of point-of-care (PoC) diagnostics and handheld sensing devices, which are crucial for timely and efficient healthcare delivery. Among the various competing sensing and circuit technologies, CMOS (complementary metal-oxide-semiconductor) stands out due to its distinct cost-effectiveness, scalability, and high precision. By leveraging the inherent advantages of CMOS technology, recent developments in optical and magnetic biosensors have significantly advanced their application in life sciences, offering improved sensitivity, integration capabilities, and reduced power consumption. This paper provides a comprehensive review of recent advancements, focusing on innovations in CMOS-based optical and magnetic sensors and their transformative impact on biomedical research and diagnostics.

Topological van der Waals Contact for Two-Dimensional Semiconductors.

The relentless miniaturization inherent in complementary metal-oxide semiconductor technology has created challenges at the interface of two-dimensional (2D) materials and metal electrodes. These challenges, predominantly stemming from metal-induced gap states (MIGS) and Schottky barrier heights (SBHs), critically impede device performance. This work introduces an innovative implementation of damage-free Sb2Te3 topological van der Waals (T-vdW) contacts, representing an ultimate contact electrode for 2D materials. We successfully fabricate p-type and n-type transistors using monolayer and multilayer WSe2, achieving ultralow SBH (∼24 meV) and contact resistance (∼0.71 kΩ·μm). Simulations highlight the role of topological surface states in Sb2Te3, which effectively mitigate the MIGS effect, thereby significantly elevating device efficiency. Our experimental insights revealed the semiohmic behavior of Sb2Te3 T-vdW contacts, with an exceptional photoresponsivity of 716 A/W and rapid response times of approximately 60 μs. The findings presented herein herald topological contacts as a superior alternative to traditional metal contacts, potentially revolutionizing the performance of miniaturized electronic and optoelectronic devices.

ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars

Recent advancements in the fabrication of Resistive Random Access Memory (ReRAM) devices have led to the development of large-scale crossbar structures. In-memory computing architectures relying on ReRAM crossbars aim to mitigate the processor-memory bottleneck that exists with current complementary metal-oxide semiconductor technology. With this motivation, several synthesis and mapping approaches focusing on the realizations of Boolean functions in the ReRAM crossbars have been proposed earlier. Thus far, the verification of the designs realized on ReRAM crossbars is done either through manual inspection or using simulation-based approaches. Since manual inspections and simulation-based approaches are limited to smaller designs, they cannot be applied to the verification of complex designs on large-scale ReRAM crossbars. Motivated by this, we propose, for the first time, an automatic equivalence checking flow that determines the equivalence between the original function specification (e.g., Majority-inverter Graph ) and the crossbar micro-operations file formats. We consider two crossbar structures, zero-transistor, one-memristor (0T1R) and one-transistor, one-memristor (1T1R) to implement the micro-operations. While the micro-operations file format exists for 0T1R crossbar structures, no representations for micro-operations to be executed in 1T1R crossbars exist yet. In this work, we introduce the micro-operation file format for 1T1R crossbar structures to efficiently represent the micro-operations as ReRAM crossbar netlists. Afterwards, we introduce two intermediate data structures, ReRAM Sequence Graph for 0T1R crossbars (ReSG-0T1R) and for 1T1R crossbars (ReSG-1T1R) , that are derived from the 0T1R and 1T1R crossbar micro-operations file formats, respectively. These ReSGs are then translated into Boolean Satisfiability (SAT) formula, and then the verification is done by checking the generated SAT formulae against the golden functional specification (represented in Verilog) using Z3 Satisfiability solver. Experimental evaluations confirm the effectiveness of the proposed verification methodology on MCNC and ISCAS benchmarks.

Digital Modulator using Digitally Programmable Complementary metal–oxide–semiconductor Differential Voltage Current Conveyor

This study aims to Developing a digital modulation system using a new technology and idea, which is the digitally programmable CMOS (Complementary metal–oxide–semiconductor), Integrate the CMOS DVCC circuit as a modulator in the communication systems, as will be explained in chapter 3, Finally, simulate this new idea in communication by using a simulation program, which is PSpice software, and analyzing the results. By focusing on How to use digital programmable CMOS (Complementary Metal–Oxide–Semiconductor) in a communication system as a digital modulator, Verifying the effectiveness of the study using simulation software such as PSpice and MATLAB, and Analyzing and verifying the effectiveness of the three modified modulation techniques. Digitally programmable Binary Amplitude shift keying (DP BASK), Digitally programmable Binary Phase shift keying (DP BPSK), And Digitally programmable Binary Frequency shift keying (DP BFSK). This study adopts an applied research approach. The study demonstrated that the CMOS DVCC circuit could be successfully integrated into communication systems as a digital modulator. The study recommended to conduct further research on the noise resistance capabilities of the DP modulation techniques, and explore additional modulation techniques that could benefit from digitally programmable CMOS technology, such as Quadrature Amplitude Modulation (QAM) or Orthogonal Frequency-Division Multiplexing (OFDM).

Test generation algorithm for QCA circuits targeting novel defects and its corresponding fault models

Considering the scaling limitations of current Complementary Metal Oxide Semiconductor (CMOS) technology, Quantum-dot-Cellular Automata (QCA) is emerging as one of the alternatives. QCA being at the molecular scale, defects are more likely to occur in it. Therefore, substantial development of QCA-oriented defects, its corresponding fault models and test generation is required. In this paper, a test generation algorithm for a QCA combinational circuit is proposed. The FAN (A Fanout Oriented) test generation algorithm is extended for QCA. The proposed Automatic Test Pattern Generator (ATPG) for QCA targets Single Stuck at Fault (SSF) set produced by novel Multiple Missing Cells (MMC) defects. The proposed ATPG is based on the QCA-oriented test generation properties and guided by proposed testability measures.The MCNC benchmark circuits are synthesized into QCA using proposed synthesis algorithms to check the effectiveness of the proposed ATPG. The ATPG is developed using C++ and tested on MCNC benchmark circuits. Further, ATPG-generated test vectors are validated at the QCA device level to demonstrate their correctness. The QCADesigner-E tool is used for the device-level implementation of the MCNC benchmark circuit.

Integrated package and calibration of high-g MEMS ASIC acceleration sensor

To achieve the intelligentization and miniaturization goals of high-g acceleration sensors, this paper proposes a super high-g accelerometer using ASIC (Application-Specific Integrated Circuit) and MEMS (Micro-Electro-Mechanical Systems) integrated packaging. The sensor structure is a membrane island structure and the ASIC interface is manufactured using 0.35 µm CMOS (Complementary Metal-Oxide-Semiconductor) technology. Two prototypes were calibrated and the sensitivities are 0.206 µV/g and 0.337 µV/g. The package frequency of sensors is 74.5 kHz. The sensor range is 200,000 g, with an overload resistance of up to 250,000 g, the enhancement of overload resistance of sensors with integrated ASIC chips has been achieved. The resolution of the prototype is 371.10 g, which is 71.95 % higher compared to the sensor without integrated ASIC. The signal-to-noise ratio (SNR) is 72.363 dB, which has been improved by 24.73 %, verifying the effective improvement of resolution and SNR of the sensors with the addition of ASIC chips.

Past, present, and future of hybrid plasmonic waveguides for photonics integrated circuits

This article addresses the past, present, and future status of hybrid plasmonic waveguides (HPWs). It presents a comprehensive review of HPW-based photonic integrated circuits (PICs), covering both passive and active devices, as well as potential application of on-chip HPW-based devices. HPW-based integrated circuits (HPWICs) are compatible with complementary metal oxide semiconductor technology, and their matched refractive indices enables the adaptation of existing fabrication processes for silicon-on-insulator designs. HPWs combine plasmonic and photonic waveguide components to provide strong confinement with longer propagation length Lp of HP modes with nominal losses. These HPWs are able to make a trade-off between low loss and longer Lp, which is not possible with independent plasmonic and photonic waveguide components owing to their inability to simultaneously achieve low propagation loss with rapid and effective all-optical functionality. With HPWs, it is possible to overcome challenges such as high Ohmic losses and enhance the functional performance of PICs through the use of multiple discrete components. HPWs have been employed not only to guide transverse magnetic modes but also for optical beam manipulation, wireless optical communication, filtering, computation, sensing of bending, optical signal emission, and splitting. They also have the potential to play a pivotal role in optical communication systems for quantum computing and within data centers. At present, HPW-based PICs are poised to transform wireless chip-to-chip communication, a number of areas of biomedical science, machine learning, and artificial intelligence, as well as enabling the creation of densely integrated circuits and highly compact photonic devices.